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22 Threads found on edaboard.com: Plb Bus
In Xilinx Platform Studio, MPMC ip core is avaiable to access ddr memory. It implement Microblaze interfacing with MPMC core through plb. When you point your linker script to DDR2 memory. You can store image as array and do image processing algorithm.
Hello! I have a XUPV5 board. I am trying to create a DMA engine peripheral on the plb bus. After designing and implementing the peripheral, I developed a testbench. The waveforms comply with the plb standard, as written in the plb_slave_burst and plb_master_burst user guides from Xilinx. During (...)
Hi all I am using EDK 11.1. I have generated a TEMAC core in ISE using core generator, wrote some VHDL code to handle data packets. I have added this TEMAC core to my xmp project i.e. microblaze as a custom IP through plb. Now my aim is to write data from microblaze to custom IP so that it will take it as data and use that data for transfer. Also
what is the difference between OPB, LMBplb (busses) in soft core microblaze?
in xilinx plb bus and axi bus are used on xps where i would like to know what are the signals are same between them not same and functional difference between them
Dear all, I really need urgent help in this matter, I have an xilinx image processing pipeline block which consists of few IP cores ( pixel correction, gamma correction, cfa,etc) build around a standard streaming video signal bus and Processor local bus 4.6. Is it possible to replace this plb to wishbone bus (...)
I am not sure how to connect two peripherals (SRAM controller and Wishbone to plb Bridge) to each other in EDK. I have an SRAM controller that interfaces to user logic using wishbone signals and a Microblaze processor with a plb bus. How do I use the bus selection in EDK to identify that the SRAM controller wishbone (...)
Hello. I am having weird problems with my design and I suspect that perhaps it is a timing error. I don't know what else to assume. I am using microblaze. I want to connect a peripheral with the plb bus. So, in my design, I have an asynchronous block, communicating with an external peripheral, the external peripheral provides the clock. Th
Hi all, I have a SoC with an AMBA bus but now I have to add a module that has an plb interface. So I am wondering if anyone did this in the past and can tell me what is the best approach. Is there maybe something like a "tutorial" where I am told which plb signals map to which AMBA signals? Many thanks, Martin
hi all i want to know the operating speed of FSL and plb bus interfaces in microblaze processor thanks
1- depend of your system clock 2- ahb with high data rate, plb with less data through put requires.
create and import perpheral wizard should let you attach a custom IP core to your MicroBlaze through the plb this what are you looking for???
Hi everyone, I'm using EDK10.1 with Xilinx Vertex5 to simulate my Custom IP I've got problems access plb bus I wrote my own wrapper user_logic to access plb in Burst Read & Burst Write Mode(file is in attachment) When I add my IP in the EDK and tried to use C code to test it(C code is in attachment too) I found out that the (...)
Hi I don't know your application. But I create custom IP and interface MB via plb bus it's work for me.
Hello, For example if i have some custom IPIF interface, and i want to use it to connect my peripherals to the plb bus. How can i import that custom interface to my EDK system? And if i have other peripherals connected to it through Xilinx IPIF... Do i have to change them also? Or i can have my own custom IP be connected to plb (...)
My question: How can I write to DDR SDRAM from a custom IP core on the plb bus in a Virtex II Pro FPGA? Background: I am developing a custom IP core for a Virtex II Pro based system (the Xilinx XUP board). This core captures video data using the Digilent VDEC1 board at a pixel rate of 13 MHz. I would like to write several video frames to memor
Hello All, I am using Virtex II pro for a design with PPC,Timer, Bram, OCM, plb,OPB. The Bram is attached on the OCM bus. I have done the Bram's PORT_B ports as external in order to load a stimuli vhdl file(as testbench) in order to load address and data and then these to be read through Port_A from the PPC. I came along some p
Hi, i got the message from the uclinux forum like this 1 make EDK 8.1 MicroBlaze system (W32 host) 2 TFT LCD ref from Ml300 ref design (needs tweaking in EDK to enable plb bus for Spartan 3 architecture) 3 build uClinux (only step that requires linux machine or emulator!) 3 get CYGWIN 4 get GNU C source for MB from Xilinx 5 run bu
really depends on the processor u're using. for arm, use amba; for mips; use ec bus; for powerpc, use plb(?).
Hi does anyone know how to write a peripheral in verilog in xilinx EDK 6.3 peripheral mode??? i was trying to write a peripheral in verilog for the plb bus in virtex II pro. but after using the peripheral creation wizard it gave a template in VHDL. it is given in documentation that verilog periherals are not supported???!!!! 8O 8
hi all, i'm doing a project on plb(processor local bus) slave ip interface.i need some help on the following 1.plb bus has a compress signal i could not find what type of compression algorithm is used. 2.what does well behaved memory means.its comes in guarded access of plb bus. (...)
hi all, i'm doing a project on plb(processor local bus) slave ip interface.i need some help on the following 1.plb bus has a compress signal i could not find what type of compression algorithm is used. 2.what does well behaved memory means.its comes in guarded access of plb bus. (...)