1000 Threads found on edaboard.com: Pll As Demodulator
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Electronic Elementary Questions :: 01-29-2006 20:46 :: IanP :: Replies: 6 :: Views: 1889
is there anybody who could provide me some documents on the pll-based demodulator. I am the very beginner, so anything is welcome.
Or any suggestions on how to design such a circuit is also appreciated.
Thanks in advance!
Analog IC Design and Layout :: 12-16-2009 07:44 :: abcyin :: Replies: 0 :: Views: 573
You can't use just one pll for making a PSK modulator.
There is a possibility to use two synchronized pll's (working as phase/frequency modulators) with summed outputs, and a phase shifter.
RF, Microwave, Antennas and Optics :: 02-22-2011 04:51 :: vfone :: Replies: 3 :: Views: 1092
how transistor work in unlinear statues and as demodulator?Theory and practical?
books or any reference that know more
RF, Microwave, Antennas and Optics :: 06-06-2012 09:36 :: baby_1 :: Replies: 8 :: Views: 1047
For FM demodulation: If modulation index is low (max. phase deviation less than 1 radian), you could use a narrow-band pll as a phase demodulator. The output is the ouput of the phase detector, that after derivation gives the frequency.
This can work for low-index FM but not for FSK.
Why do you need a method other than take the control voltage o
Analog IC Design and Layout :: 02-22-2010 11:36 :: zorro :: Replies: 1 :: Views: 1244
U can use the pll as a frequency synthesizer or as a fixed clock generator, it will depend on the the divider and ur application.
Electronic Elementary Questions :: 11-24-2005 07:13 :: eng_Semi :: Replies: 2 :: Views: 609
it will depend on the pll usage
if u will use it as frequency synthizer the phase noise will be ur major target , and loop speed "settling time" , and for sure stabilty
if u will use it as demodulator the loop bandwidth , and speed will be ur major concern , and so on
Analog Circuit Design :: 04-22-2006 19:37 :: khouly :: Replies: 11 :: Views: 1058
We using FM pll demodulator with a data slicer as FSK demodulator, my question is what is it a coherent demodulator or non-coherent demodulator?
And FSK demodulator has two another method:
1: general band pass filter and envelope comparator
2: match filter BPF and envelope comparator (...)
Digital communication :: 06-24-2007 23:16 :: wwfhm2002 :: Replies: 2 :: Views: 1930
Just a general statement:
think about the pll as an amplifier that works on phase rather tahn voltage and think about the VCO as a noise generator.
When you close the VCO in the loop the effective phase noise is reduced by a factor equal to the loop gain of the pll ...
... got the idea ?
Analog IC Design and Layout :: 12-22-2004 05:08 :: nathan :: Replies: 7 :: Views: 2394
To add to the last reply, Digital plls are only good for speeds not exceeding 250Mhz mostly because standard digital cells do not run faster than 500Mhz reliably and even at thos speed have excessive jitter. So if you need higher speeds design your vco and filter in anlog and your divider circuit needs to be designed using custom cell design techni
Analog Circuit Design :: 09-11-2005 00:50 :: rakko :: Replies: 5 :: Views: 921
Is the VCO gain larger, the output jitter more serious?
If it is ture, we should reduce the gain to get better performance.
But if design the pll as a synthetizer, and it has a widely output
frequency range, for example, 100Mhz ~ 1000Mhz, the VCO gain
is very huge to meet the spec. How to solve this conflict?
Analog Circuit Design :: 09-02-2005 10:09 :: Analog_starter :: Replies: 7 :: Views: 1298
when u azalyze the pll as a feedback system we use S domain , which mean that u assume that the pll is a countinuse time system
but actually pll is sampled system cause it contain a digital part PFD
so we need the bandwidth of the loop to be at leat 1/10 of the refernce frequency to insure that any variation id the loop condition will (...)
Analog Circuit Design :: 10-18-2005 02:49 :: khouly :: Replies: 4 :: Views: 1262
Actually if we use a phase detector in the pll, then we use LPF only to cut the transients that comes out from the detector along with a DC voltage that denotes the phase error.Because only when the control voltage to the VCO is stable, it can work properly.
If we make use of a Frequency detector instead of Phase detector, what would be the reas
Electronic Elementary Questions :: 01-24-2006 03:29 :: gayu :: Replies: 4 :: Views: 1282
i think half and full rate phase decetors are used in CDR "clock and data recovery"
but in pll as a frequency multiplier or Frequency synthizer " usually use the charge PUMP with PFD
Analog IC Design and Layout :: 08-15-2006 05:30 :: khouly :: Replies: 9 :: Views: 1701
frist of all u need to study the pll as a system well , and check by urself how the LPF will affect the loop ,
then u should know ur application well , demodulation , FS , and so on , to see if there are any constraints on ur filter bw or not , and then begin ur desgin
Analog IC Design and Layout :: 10-24-2006 18:11 :: khouly :: Replies: 4 :: Views: 887
u can think of as the pll response to the changes in the input signal according to the pll's BW (related also to LPF BW) , so fast signals affecting the input faster than the pll wont really affect the output , where fast signals in time are high frequency which u could say are averaged by the pll as the (...)
Analog Circuit Design :: 10-25-2006 16:05 :: safwatonline :: Replies: 7 :: Views: 863
What is the impact of pll BW on its performance? What's its other trade-offs?
Analog IC Design and Layout :: 02-15-2007 10:02 :: ahmad_abdulghany :: Replies: 5 :: Views: 808
Dear Biff , it is a great example , and explanation of the pll
RF, Microwave, Antennas and Optics :: 02-23-2007 11:27 :: khouly :: Replies: 8 :: Views: 1864
The main principal of the pll is to tune the VCO frequency and to lock the VCO to that frequency with a certain amount of accuracy and to protect it from temperature, components tolerances and noise effects.
RF, Microwave, Antennas and Optics :: 08-03-2007 16:01 :: BigBoss :: Replies: 11 :: Views: 975
and then implement this pll using VHDL in FPGA design？
I am very intrested in it.
Added after 25 minutes:
sorry. add another question.
Which book is OK when start FPGA design using matlab?
Digital communication :: 07-11-2007 03:19 :: FPGAs :: Replies: 2 :: Views: 2606
I am designing a CMOS pll IC using cadence. The pll, as we all know, consists of a VCO, a high frequency first divider stage, a series of low frequency dividers followed by a PFD etc.
My question is about the interfacing of the VCO with the first divider stage and
the subsequent divider stages...
1. A buffer is needed after the VCO to avoid
RF, Microwave, Antennas and Optics :: 12-10-2007 05:57 :: haadi20 :: Replies: 1 :: Views: 702
I don't think that you can directly plot phase and amplitude response of the pll. This is due to the special nature of the pll as the signal changes its domain from one point to another. For example, the signal after the loop filter is voltage but after the VCO it's freq/phase.
Analog IC Design and Layout :: 05-05-2008 06:25 :: ieropsaltic :: Replies: 2 :: Views: 712
i have deisgned a pll as a frequency synthesizer
i designed the loop filter using matlab using S domain.
All blocks, Charge pump pfd, vco and divider are done in transistor level
when i simulate them all in feedback loop, using transient analysis in cadence
the curve of voltage control has a strange behaviour.
first, it goe
Analog IC Design and Layout :: 07-06-2008 15:40 :: mohamedabouzied :: Replies: 8 :: Views: 836
Can someone explain or point me to the right link on how a pll is used to demodulate a FM carrier? Every book I read tells me it can be done but not specific enough on how it is done. I have read Horowitz & Hill: The Art of Electronics 2nd edition and RF Engineering for Wireless Networks by Daniel M. Dobkins.
RF, Microwave, Antennas and Optics :: 09-05-2008 16:52 :: robismyname :: Replies: 14 :: Views: 18185
You would find out by opening up the unit and seeing if there is a "digital pll chip" inside somewhere. 98% of plls today are "digital".
RF, Microwave, Antennas and Optics :: 10-04-2008 10:16 :: biff44 :: Replies: 6 :: Views: 1040
This looks like to be a great forum and its my first post here.
I'm simulating a 6.4 GHz pll in Simulink with the models available in the analog-mixed signal library (AMS).
My aim is to use the pll as a clock generator and hence, I need to minimize jitter and have low pll closed-loop bandwidth. However, if I keep my (...)
Analog Circuit Design :: 10-22-2008 13:46 :: mika_g :: Replies: 0 :: Views: 885
As all we know, now a days there are pll included in almost all FPGA. I'm keen to know whether we (a programmer ) can select a perticular pll for his application like clk synchronoization, or a tool itself does this task wherever it is required without informing to user....
The other way arround if i Know at this perticular stage/ locati
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-23-2009 23:57 :: amitjagtap :: Replies: 1 :: Views: 658
For your typical modern frequency synthesizer, one that contains some sort of integrating function in the loop filter, they are probably the same.
I can think of some scenarios where they might be different, though.
Lets say I was using a pll as a receiver, say for a satellite system. On first turn on, the pll might simply sit there unlocke
Analog Circuit Design :: 05-07-2009 07:42 :: biff44 :: Replies: 9 :: Views: 7609
I wish to know if there is any other circuit in pll which is sensitive to supply voltage apart from VCO.
As I have an problem with my pll as it is only able to lock back after a long time ( ~ 5minutes) or if I reduce the VCO supply voltage. Do you guys have any idea of which circuit which might possible cause this problem?
BTW, the PL
Analog Circuit Design :: 07-29-2009 07:27 :: yellowperil :: Replies: 2 :: Views: 884
Lock time is inverse proportional to pll filter bandwidth.
You should 2 things simultaneously
Also, you have to find a optimum way between trade-off
RF, Microwave, Antennas and Optics :: 03-13-2010 16:08 :: BigBoss :: Replies: 5 :: Views: 893
as the topic title it too tough to code a pll using VHDL for a beginer? is ready made open source code available on the net?
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-28-2010 01:25 :: bhargavz :: Replies: 2 :: Views: 1605
A pll as a center frequency of 10^5 rad/s, Ko=10^3 rad/s/v, Kd=1V/rad.
Assume there is no other gain in the loop.
Ask: 1. Determine the loop bandwidth in the first-order loop configuration.
2. Determine the single-pole, loop-filter pole location to give the closed-loop poles located on 45 degree radials from the origin of the complex frequ
Analog Circuit Design :: 04-06-2011 15:05 :: ethan :: Replies: 0 :: Views: 731
How to simulate pll loop filter noise by cadence spectre?
I used 3ord LPF in pll.
As attached figure, dashed lines are resistors noise in LPF and solid lines are output noise after transfer function.
Who can help me about LPF noise simulation by cadence spectre.
thank you very much.
Analog Circuit Design :: 06-22-2011 12:55 :: cwcgo :: Replies: 0 :: Views: 872
I have to realize in VHDL a frequency synthesizer in order to generate frequencies from 5Khz to 20Khz with 1Hz step or more if not possible so fine frequencies.
This is the
The N divider is made in VHDL(others are ex
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-15-2012 09:50 :: franticEB :: Replies: 1 :: Views: 402
My thesis in year 1979 was a simple demodulator for Double Sideband Suppressed Carrier (DSB-SC) signal.
At that time, I did it for the IF AM frequency 455 KHz by using CD4046 (pll IC) and LM339 (quad comparator IC) to recover the phase and frequency of the suppressed carrier. But after I built the project I didn?t find the time to submit its paper
Electronic Elementary Questions :: 07-16-2013 10:15 :: KerimF :: Replies: 7 :: Views: 1432
I am designing a behavioral model for a pll. As I am new to this language, I have decided to start with the oscillator. I have just to copied and paste a piece of code that I found on Cadence's documentation.
The problem is that I get an error which I cannot solve.
Some lines of the code:
Analog IC Design and Layout :: 10-30-2013 07:38 :: netbug :: Replies: 0 :: Views: 186
I just wrote a time-domain pll behavior model including VCO phase noise and non-idealities from other blocks. I have generated the time-domain open-loop VCO 1/f^3+1/f+white phase noise as shown below:
In the pll time-domain behavior model, I inserted the above VCO open-loop phase noise at the output of the
Analog Circuit Design :: 11-13-2013 10:29 :: carl_chao :: Replies: 0 :: Views: 245
I used the MC3362DW but unfortunately this chip does not exists anymore.. How would one construct a narrowband FM crystal driven receiver ? (1.8 to 5 volts power supply)
Any suggestions welcome.
Why is double posting occured ?? I don't know ! Anyways even with a pll as frequency synthesis.. I still would be happy.. Anoying this double
Hobby Circuits and Small Projects Problems :: 04-10-2004 15:02 :: henrik2000 :: Replies: 5 :: Views: 1677
Long ago I was busy with this topic. I also didn't believe this law, but as I can remember: for a LTI (linear time independent system) it is true as I verified myself.
You may not mix up settling time and tau!!! In (almost?) every case tau is shorter than the settling time, depending on the order of the system and its parameters.
RF, Microwave, Antennas and Optics :: 04-15-2004 06:38 :: eda4you :: Replies: 6 :: Views: 3368
You will have to put a psk detector at the end of the IF chain in place of the AM detector. It might be easier to use FSK and have a pll as the FSK detector. If you do need the PSK, look up "costas loop' on the web or in a communication theory textbook for circuits.
You could even use on-off keying and the AM receiver would work as is.
Analog IC Design and Layout :: 02-02-2005 00:53 :: flatulent :: Replies: 3 :: Views: 3122
You will have touse VCO controlled by a pll loop (example NE564: ). First you will need to reduce the frequency to, say 2MHz (divisinon by 3 and 2 - to provide 50% duty ratio) and then use this signal as reference to pll. As signals from VCOs are in square wave form you will need to imp
Analog Circuit Design :: 04-14-2005 03:14 :: IanP :: Replies: 3 :: Views: 715
Is the Dc support the output of the pll as the mbist clock, if I want to combine the mbist with the JTAG, I
should setup the bist_clock(high speed) and bist_clock_lu(connect with JTAG TAP).
I have 2 problem.
1. can the pll output clock act as the bist_clock?
2.why the bist_clock should be the integer of the bist_clock_lu, why?
3. which on
ASIC Design Methodologies and Tools (Digital) :: 04-27-2005 13:12 :: davidyu :: Replies: 4 :: Views: 911
What is the ENvelope Detector For FM? How iTs work? Please Give the schematic and The reference...I really need it for my School Task
RF, Microwave, Antennas and Optics :: 08-05-2005 20:28 :: Elits :: Replies: 2 :: Views: 2875
I had a bizzare experience today. I was testing a simple band pass filter in the lab. I had connected the output to a speaker. As I was setting up the ckt for testing, I hear the local FM station in the speaker. I was loud and clear. I couldn't believe it. How can that happen. The FM station's antenna is very close to my lab, but that doesn't expla
RF, Microwave, Antennas and Optics :: 12-26-2005 09:21 :: magnetra :: Replies: 2 :: Views: 554
Would someone please enlighten what is the difference between a Pre-scaler and Divider within a Phase Locked Loop(pll). As both are some form of divider then what is the need for a pre-scaler within a pll.
RF, Microwave, Antennas and Optics :: 01-02-2006 00:05 :: wchu01 :: Replies: 4 :: Views: 700
use the pll as the FSK transmitter and the receiver
RF, Microwave, Antennas and Optics :: 03-08-2006 20:41 :: springf2000 :: Replies: 8 :: Views: 4351
pll simplest cheapest ...
Analog Circuit Design :: 07-02-2006 11:35 :: aandrew :: Replies: 6 :: Views: 1268
If the VCO frequency is drifting more, the Phase Noise it will increase, because the pll is trying more to compensate for this drift.
RF, Microwave, Antennas and Optics :: 07-28-2006 15:39 :: vfone :: Replies: 2 :: Views: 703
Normaly the pahse margin is only computed for a linear model of the pll. as mentioned before a step response of the loop filter gives the correct answer. i am sure you will find in literature the equation where you can e.g. compute the phase margin with the first two overswing amplitudes.
Analog IC Design and Layout :: 10-19-2006 08:39 :: eda4you :: Replies: 4 :: Views: 1101
can we clock EC1 family device with pin which is not having dual functionality as pll, which may be simple IO pin??????????
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-30-2007 06:24 :: dipti :: Replies: 5 :: Views: 591