12 Threads found on edaboard.com: Pll Lock Measurement
Inject noise model in the pll then you can measure the output and caculate the jitter from hspice simulation .
Analog Circuit Design :: 31.12.2004 06:48 :: Nobody :: Replies: 13 :: Views: 4689
VCOs are very sensitive to control voltage. So you need to filter it as much as you can. Supply voltage has to be filterd also, and a shield for the board can be necessary.
A good way to measure it is lock with a pll with a very small loop bandwidth. For freqs larger then the loop bandwidth you'll see the VCO phase noise.
A more expensive solutio
Analog IC Design and Layout :: 12.09.2006 09:17 :: Mazz :: Replies: 3 :: Views: 907
The suggested method is ok, but suffer from inaccuracies; let me explain better. Suppose that your KVCO is 100 MHz/V and you want to know when the pll has settled his freq whithin a range of 10 KHz. The voltage accuracy has to be 1^4/1^8<1 mV!!
One more accurate method is, with a spectrum analyzer that is able to demodulate the signal, use freq
RF, Microwave, Antennas and Optics :: 11.06.2007 01:08 :: Mazz :: Replies: 10 :: Views: 1677
pll chip :adf4106
charge pump current:2.5mA
loop bandwidth: 800Hz
PHD frequency(reference frequency):3MHz
loop type type A
I want to konw the probably cause.
RF, Microwave, Antennas and Optics :: 03.03.2009 03:40 :: fnx7 :: Replies: 10 :: Views: 2163
For those of us without the latest gear, we can use a diode detector to measure the amplitude of the rf output; and can use a delay line frequency discriminator (signal splitter, delay line, mixer, manual phase shifter) which can tell you both when the frequency is settled, and when the phase is settled, by watching the mixer IF output on an osci
RF, Microwave, Antennas and Optics :: 08.12.2009 12:13 :: biff44 :: Replies: 4 :: Views: 721
Can some please help for dsPIC 30F3011 Mplab c30 compiler code for filters and phase lock loop.
Digital Signal Processing :: 20.02.2010 00:15 :: Sujitha Dilip :: Replies: 3 :: Views: 1564
I have met a problem on pll lock time. I found that the pll with 10MHz PFD
freq has a great smaller lock time than a pll with 30MHzPFD,although they have
the same loop band width and phase margine. this is an experiment
I once use (...)
RF, Microwave, Antennas and Optics :: 29.06.2010 21:40 :: fenfei :: Replies: 0 :: Views: 480
I am trying to get a simple frequency multiplication scheme to work, but am having trouble getting the pll to lock.
Background:I am sampling (frequency measurement) my signal at 1Hz, I can not sample any slower, and need to get a measurement resolution of 0.1Hz minimum. My input signal goes from 0-1kHz, so at the very low (...)
Analog Circuit Design :: 06.04.2011 12:40 :: abrand :: Replies: 0 :: Views: 1269
Here i attached the control voltage to the VCO of pll.
From this i know my pll(2nd order pll) is going to lock that is the input of the VCO well known from PSS analysis.
But i got some oscillation while locking the phase of the signal(2nd wave)
(Measured by delta cursor i got 50
Analog Circuit Design :: 01.08.2011 08:06 :: vasusathiyam :: Replies: 4 :: Views: 699
I'm not aware of any oscilloscope, that has built-in a similar analysis function. You should consider, that it would be only reasonable for those signals, that have a clear, dominant frequency. Many signals presented to an oscilloscope don't have it.
It's however possible to generate a similar frequency plot by signal processing of aquired data.
Analog Circuit Design :: 13.09.2011 19:05 :: FvM :: Replies: 11 :: Views: 1831
i want to ask a question regarding the measurement of the frequency
i am looking for a particular signal
the signal to noise ration is not very high
i am detecting the presence of the signal via measuring the amplitude of signal
whenever the strength of the signal is higher then noise level , infact quite high
then i can detect the pr
Analog Circuit Design :: 26.08.2009 07:49 :: malik_123 :: Replies: 1 :: Views: 1636
Depends on the frequency and amount of noise. A couple of comparators which may need hysteresis if the signal is very noisy. Then measure each cycle and do a lot of averaging.
Hi Keith - I would like to drive the laser at at least 1MHz, potentially significantly faster.
I was assuming I'd have to pu
Analog Circuit Design :: 21.08.2011 13:56 :: uoficowboy :: Replies: 5 :: Views: 447