66 Threads found on edaboard.com: Power Clamp Circuit
I am working on a RFID front-end. The very first component is the clamp circuit that limits the RF input to a modest range. However, this simple clamp circuit (see figure) wouldn't work. The reason is that if the input signal is a 50% modulated ASK signal, at high power level, the output of this (...)
Analog IC Design and Layout :: 06.06.2006 13:04 :: EMfox :: Replies: 1 :: Views: 946
i am designing io&esd circuit using HV process(18v),
Can i use rc -invertor power clamp for a switch controlled PAD ?
which device can i use in power rail to rail (or power cut) esd circuit , using hv process or normal process diode ?
Analog Circuit Design :: 28.06.2006 11:39 :: vivsim :: Replies: 2 :: Views: 664
how to simulate ESD power clamp? how the stimulus look like? how long RC constant require?
Analog Circuit Design :: 19.12.2007 06:05 :: surianova :: Replies: 4 :: Views: 820
the attachment is the power clamp use for ESD. The RC constant is 1 us. The inductor is assume 1n for package model. The power suppy is ramp up from 0 to 3.3v in 1 us. But suprising the circuit oscillate as show in the attachment. My question is how this circuit can become an oscillator? And if i (...)
Analog Circuit Design :: 11.01.2008 01:02 :: surianova :: Replies: 1 :: Views: 750
power clamp is referred to power supply I/O, and it often includes ESD clamp devices.
Analog IC Design and Layout :: 25.02.2008 08:03 :: mqc_hn :: Replies: 4 :: Views: 998
for power clamp, it has its own gnd called gndesd. And the other analog block of the circuit use analog gnd called gnda. The question is where should connect the substract of nmos in power clamp. To gndesd or gnda?
Analog IC Design and Layout :: 23.11.2008 19:52 :: surianova :: Replies: 1 :: Views: 593
I have a question about gate-coupled NMOS for ESD protection. Usually the GCNMOS is used as power clamp between VDD to VSS. P+ poly resistor and MOS capacitance are used to set the RC time constant to sense the ESD stress to help triggering the NMOS clamp, so, when you design this RC triggering circuit, how much (...)
Analog IC Design and Layout :: 10.01.2009 02:34 :: prcken :: Replies: 2 :: Views: 1935
Before you start desiging a new 5V power clamp you should find out some requirements for this clamp. Most important is to define the so-called ESD design window. There are 3-4 main questions to define this ESD design window
- What ESD specification do you target? The standard 2kV HBM? Some MM requirement? Or do you have (...)
Analog IC Design and Layout :: 27.03.2009 05:10 :: ESDSolutions :: Replies: 4 :: Views: 2095
Here is an example of a sourcing current source, clamped at 5V.
The output current is 20mA, fixed. To adjust it, you can change R1:
Iout=Vref/R1, where Vref=2.5V
The output is clamped by the precision clamp IC1B, D1. For the clamp to work, the current should be maintained below 20mA. For higher currents, you would (...)
Hobby Circuits and Small Projects Problems :: 07.02.2006 20:52 :: VVV :: Replies: 4 :: Views: 1618
It is not "back" or "front".
It is flyback or forward topology,is basic switch-mode power supply!
Professional Hardware and Electronics Design :: 01.06.2004 01:30 :: alphi :: Replies: 7 :: Views: 832
It sounds like you may be getting non-destructive latch-up. The charge from the cable injects charge into your circuit causing an SCR type action.
You could put some voltage suppression (MOV, Zener, etc) to clamp the voltage to your power supply level. There are several external protection circuits that are available on (...)
Analog Circuit Design :: 28.01.2005 19:20 :: DoctorProf :: Replies: 3 :: Views: 935
Hi, every one. I have a simple question about the power measurement of a circuit which is powered by battery. Can I just disconnect the positive wire from the battery to circuit, and use a current meter to read the current while the circuit is operation?
And should I measure the DC current or AC current? (...)
Electronic Elementary Questions :: 01.12.2005 03:35 :: epp :: Replies: 4 :: Views: 601
It sounds like you need bypassing. For your power supply pins, tie 10uF capacitor at each of your power pins to ground. For your op-amps and device with power pins, tie 4.7uF and 0.1uF capacitors very close to the pins.
In the case you have really bad spikes coming from your supply, put 2 clamping diodes at the (...)
Electronic Elementary Questions :: 17.12.2005 08:09 :: Eric Best :: Replies: 4 :: Views: 602
Thnx for your explanation, it is stated in a foundry design manual an ESD power clamp is required if the capacitance is less than 100nF betweed Vdd and Gnd. Is it possible to avoid this clamp if I place a MOS cap between Vdd and Gnd, with capacitance more than 0.1pF?. Thanks in advance
RF, Microwave, Antennas and Optics :: 13.06.2006 10:24 :: hrkhari :: Replies: 2 :: Views: 989
Can somebody provide me with some information about powerclamps in IC design?
What is it doing,why is it needed, how to implement it
Also any papers, related chapters of E-books ...
Analog IC Design and Layout :: 20.07.2006 12:49 :: E-goe :: Replies: 9 :: Views: 873
IGBTs are controlled in the exact same was as if it were a MOSFET.
so search for "mosfet driver" also. you will find lots of companies offer mosfet driver solution all in one chip.
depends on your power level and circuit topology after that before more detail can be given.
Analog Circuit Design :: 25.01.2008 20:25 :: Mr.Cool :: Replies: 11 :: Views: 14393
Seems like you don't quite understand the ESD triggering using this approach. In order to be safer,
I suggest you to replace the final transistor to an NMOS transistor with gate connected to Vb, which is then a typical RC gate coupled structure for you to be more familiar with the basics first. Otherwise, you may fail finally in rea
Analog Circuit Design :: 01.03.2007 23:02 :: firstname.lastname@example.org :: Replies: 7 :: Views: 1223
It's RC based ESD power supply clamp. When ESD event is occured, this ckt shorts VDD and GND rails.
Analog Circuit Design :: 12.03.2007 04:24 :: DenisMark :: Replies: 7 :: Views: 512
optocoupler temperature coefficient..Soft-start controller is gentle on loads..Method offers fail-safe
variable-reluctance sensors..circuit forms adjustable bipolar clamp..Analog switch expands I2C interface..circuit safely applies power to ICs..Simple circuit forms peak/clipping indicator...
eng raafat tannir
Other Design :: 27.05.2007 17:00 :: marcony :: Replies: 0 :: Views: 804
actually removing a snubber typically improves performance, or at least efficiency as its no longer consuming any power, though you basically are asking murphy to cook your ic's and transistors
Analog Circuit Design :: 27.06.2007 10:28 :: ender84567 :: Replies: 2 :: Views: 666
Hi, I facing a problem here on ibis model, there is couple of question about generating this ibis model.
1. How to extract the C_comp value through simulation? Although the cook book show that we can perform AC analysis using tanks circuit, and get the resonant frequency.. but I wonder how should I do the connectivity for the method.
2. How s
PCB Routing Schematic Layout software and Simulation :: 27.07.2007 05:39 :: skynet :: Replies: 2 :: Views: 1308
What is the diference between GGMOS and GCMOS? Why is GGMOS using as input PAD ESD protection and GCMOS using as clamp circuit between the power rail and vss?
Analog Circuit Design :: 01.10.2007 02:12 :: sissi :: Replies: 4 :: Views: 1139
There is no limitation the gcmos can not used as input pad esd protection circuit,
but it can influence the bandwith of the input signal.
Added after 2 minutes:
use gcmos clamp vcc to gnd,
Analog Circuit Design :: 16.10.2007 11:38 :: Areky_qin :: Replies: 3 :: Views: 1868
i want to drive tcd2557(a ccd of toshiba) with dallas mcu ds89c40,could somebody give me some links or help?
many thanks first
Driving CCD, right ? Dallas MCU DS89C40 or DS89C420/450? it must be DS89C420/450, as far i know, its MCU, not have internal ADC, which should be introduce on designing CCD based project.
Microcontrollers :: 13.12.2007 01:07 :: zetd :: Replies: 3 :: Views: 1069
I am learning the flyback power convert circuits. But I am quite puzzled by the attached circuit. There are seven red circles in question. Could anybody explain what these components are meant for? The nominal input voltage is 24VDC and output is 36VDC.
Thanks in advance.
Electronic Elementary Questions :: 24.07.2008 22:36 :: bittware :: Replies: 1 :: Views: 652
According to this figure: -2kV (negative zap) is applied at pin 1 with pin 2 at ground.
According to the figure (green reference line) there was a forward diode from pin 1 to pin 2 and some element for the reverse stress case (power clamp, local clamp or diode up + power clamp).
Analog IC Design and Layout :: 25.04.2009 05:45 :: ESDSolutions :: Replies: 3 :: Views: 1860
i want to drive a high power buzzer of 12v from 8051 using uln2003 and relay ckt,
can any one suggest me how do i hav to connect the circuit.
please help its urgent.
Electronic Elementary Questions :: 23.07.2009 05:44 :: wajbharath :: Replies: 2 :: Views: 4107
I'm redoing control of Microcannel Plate.Sorry for incomplete info, and yes it was error. I just finished fully redraw it. I'm reconstructing schematics from existing PCB. Here it is. It was part of big device which I dont know.
There is HV power supply with 2 outputs - one is +400V...-2000V and second +100V...+2000V. The voltage of each HV ou
Analog Circuit Design :: 06.02.2010 13:16 :: karnel :: Replies: 18 :: Views: 837
In a power IC the bandgap and any cascoding is unlikely to
be significant in the end, area-wise. It's the power devices' area.
The current for a reference and housekeeping analog should
not need much device width.
Stacked MOS diodes and a resistor make a good enough shunt
regulator, a pass follower (high voltage capable) makes
Analog IC Design and Layout :: 25.02.2010 09:56 :: dick_freebird :: Replies: 3 :: Views: 1321
It depends on how much current you allowed it to draw. When you reverse the power connections, all the input protection diodes conduct at once. They will clamp the voltage across the IC to a safe level as long as they can withstand the current themselves. They can usually only handle a few mA though.
If the current was limited, you might be luck
Microcontrollers :: 31.05.2010 08:29 :: betwixt :: Replies: 3 :: Views: 424
do you have experinece in using high voltage (e.g. 3.3V) device as ESD device for low voltage(e.g. 1.8V/1.2V) device domain protection?
usually, from circuit design perspective, he/she will not connect 3.3V device to 1.8V/1.2V power supply.
i saw the 1.8V power clamp ESD device failed in several projects. while (...)
Analog IC Design and Layout :: 13.06.2010 09:39 :: prcken :: Replies: 15 :: Views: 1574
During low voltage design, we would like to connect a cap between vin and ground to clean the power supply. And if we use a nmos as the cap, how could we protect its gate?
I have draw a pic to illustrate the question
Analog IC Design and Layout :: 12.10.2010 02:18 :: refugee :: Replies: 10 :: Views: 1154
Do you have the chip at your fingers? Use a multimeter to know the answer.
The datasheet's maximum ratings suggest diodes of both polarities, but you can't be sure. So why not simply shutting down the input signals before the power supply?
Analog Circuit Design :: 01.02.2011 10:00 :: FvM :: Replies: 5 :: Views: 600
MOSFET aren't generally provided with a clamp diode at the gate. They may possibly have ESD protection. Which transistor type you are referring to?
All power MOSFET have bulk (substrate) connected to source and a built-in drain-to-substrate diode, necessary by technology. It's not provided for a particular purpose, but must be considered in cir
Analog Circuit Design :: 04.05.2011 05:08 :: FvM :: Replies: 7 :: Views: 2050
The easier way is put a clamp meter on the main line (Phase) and measure the current consumption when you want to know of the time consumption. The after Ohm's Law multiply this reading with the supply voltage, you wattage (consumption of that time) will be available. Or you see the power consumption labels of all the equipment which you want to us
Electronic Elementary Questions :: 26.11.2011 13:46 :: Raza :: Replies: 4 :: Views: 377
Ok, maybe I don;t get something, but how did you come up with 15 ohm resistor for continuity checking. When power is applied but before microcontroller does anything there is 9V/(5+15R)=0.45 A flowing through squib to GND. I'd aim at something like 1k+1k in series (gives 4.5 mA and ). This gives voltage divider allowing small current to flow throu
Analog Circuit Design :: 08.12.2011 08:06 :: poorchava :: Replies: 6 :: Views: 267
Thermal stream units can produce static charge (triboelectric?)
if not well grounded. The test floor should have air ionizers and
ESD mats & wrist straps over the place.
But you also need to look at the test program and hardware.
Many tests can put more power into an ESD clamp than it can
take (clamps are sized for the ESD strike, peak (...)
Analog IC Design and Layout :: 09.02.2012 10:38 :: dick_freebird :: Replies: 2 :: Views: 377
Hello ! I consulted power Integrations about a power supply design using one of their TOPSwitch IC's. The details of my questions are here:
Need to design for 380 VAC mains 240 W power supply | power Integrations
Analog Circuit Design :: 14.02.2012 18:02 :: obiwan :: Replies: 13 :: Views: 1168
In order for you circuit to work there must be a return path for the signal, either through the ground or through the plus voltage supply. Is your circuit power (positive and negative) connected to the signal power source?
Analog Circuit Design :: 05.09.2012 13:36 :: crutschow :: Replies: 6 :: Views: 459
I have a PFET which is suffering the following power dissipation , but only at switch on.......
power dissipation in TO220:
.....this PFET has no heatsink, will it explode?
..here is the circuit in which it is is a current clamp, which limits inrush current at start up.
Power Electronics :: 13.10.2012 08:28 :: treez :: Replies: 2 :: Views: 175
The overshoot of clamped output voltage is mainly caused by the delayed action of the OP slewing out of saturation. That's an intrinsic disadvantage of this cicruit, when operated with fast input signals. The FET clamp circuit suffers from the same problem and most likely additionally from charge injection, particularly when using a (...)
Analog Circuit Design :: 26.10.2012 16:26 :: FvM :: Replies: 8 :: Views: 399
temperature range (-45 to 85 C)
That's the hard part.
The main problem with the circuit you showed earlier is that it compares the voltage across the current sensing resistor with the Vbe of a transistor, and the Vbe changes with temperature.
The trick is to use a precision voltage reference that doesn't vary with t
Analog Circuit Design :: 14.04.2013 11:12 :: godfreyl :: Replies: 20 :: Views: 616
There are several devices sold for this purpose. One is a shunt zener type circut. Many companies sell these. Harris is one. They clamp the voltage levels. A cheap thing is to put diodes from the line to the positive and negative power rails.
If your circuit can operate with a little series resistance in the signal lines, putting (...)
Professional Hardware and Electronics Design :: 18.07.2003 11:20 :: flatulent :: Replies: 1 :: Views: 1094
It only powers on for about a sec. then it turns off. If you attempt to turn it back on after it turns off, it will not turn on. Its like it has a self reseting circuit breaker or somethhing.
Hobby Circuits and Small Projects Problems :: 05.08.2004 03:51 :: david90 :: Replies: 3 :: Views: 2555
Rescently When i was constructing the project of automated fishing ,
I encountered the powerful EMI from three Small toy motors (brush type , permanent magnet) , it was so powerfull that , the controller 89C51 was almost unable to work , even after connecting 0.1uf and 1000uf capacitors at all the supply lines. After using two different pow
Hobby Circuits and Small Projects Problems :: 26.10.2004 09:27 :: Shashank_parab :: Replies: 14 :: Views: 3240
IRF540 is fine to use at 10V. you do not need a transistor front end.
first remove the 555 timer and see if you can at least turn the solenoid ON. what is the pull-in current of your solenoid? Size your current limiting resistor for this +20% and make sure resistor is rated for continuous power loss (even though you plan on pulsing the circuit)
Electronic Elementary Questions :: 13.01.2005 22:14 :: Mr.Cool :: Replies: 41 :: Views: 19174
I need help in designing transient voltage suppressors in PSPICE. I need circuit diagram for a transient voltage suppressor which can clamp voltages up to
5 Kilo Volts. I dont know about peak power rating and the reverse breakdown voltage. Please help me in this regard. I need this information very (...)
Analog Circuit Design :: 06.12.2006 18:07 :: dolu :: Replies: 0 :: Views: 653
hi , I am afraid that you made sth wrong. The circuit can work properly only when the op is powered by two power supply----a postive one and a negative one.Since Vout should be a negative voltage.
Analog Circuit Design :: 24.08.2007 02:48 :: niezimei :: Replies: 10 :: Views: 980
The bottom trace is the drain source voltage? Where did you get the transformer, that?s quite the spike for what looks like a 30 or 40V input (If I?m reading your scope shot right). Or is this a high cu
Analog Circuit Design :: 22.11.2007 20:59 :: max0412 :: Replies: 6 :: Views: 1206
Do you need to simulate a full DC_DC convertor using only BJT (lots of BJT :D ) or just using a normal dedicated controller and some externals power BJT?
Analog Circuit Design :: 04.03.2008 02:51 :: mister_rf :: Replies: 5 :: Views: 698