11 Threads found on edaboard.com: Power Clamp Circuit
The overshoot of clamped output voltage is mainly caused by the delayed action of the OP slewing out of saturation. That's an intrinsic disadvantage of this cicruit, when operated with fast input signals. The FET clamp circuit suffers from the same problem and most likely additionally from charge injection, particularly when using a (...)
Analog Circuit Design :: 10-26-2012 16:26 :: FvM :: Replies: 8 :: Views: 610
how to calculate total power consumed by a circuit driven by an A.C source?
Electronic Elementary Questions :: 11-26-2011 11:20 :: nitin.maurya1 :: Replies: 4 :: Views: 501
It depends on how much current you allowed it to draw. When you reverse the power connections, all the input protection diodes conduct at once. They will clamp the voltage across the IC to a safe level as long as they can withstand the current themselves. They can usually only handle a few mA though.
If the current was limited, you might be luck
Microcontrollers :: 05-31-2010 08:29 :: betwixt :: Replies: 3 :: Views: 527
I have a question about gate-coupled NMOS for ESD protection. Usually the GCNMOS is used as power clamp between VDD to VSS. P+ poly resistor and MOS capacitance are used to set the RC time constant to sense the ESD stress to help triggering the NMOS clamp, so, when you design this RC triggering circuit, how much (...)
Analog IC Design and Layout :: 01-10-2009 02:34 :: prcken :: Replies: 2 :: Views: 2309
for power clamp, it has its own gnd called gndesd. And the other analog block of the circuit use analog gnd called gnda. The question is where should connect the substract of nmos in power clamp. To gndesd or gnda?
Analog IC Design and Layout :: 11-23-2008 19:52 :: surianova :: Replies: 1 :: Views: 699
the attachment is the power clamp use for ESD. The RC constant is 1 us. The inductor is assume 1n for package model. The power suppy is ramp up from 0 to 3.3v in 1 us. But suprising the circuit oscillate as show in the attachment. My question is how this circuit can become an oscillator? And if i (...)
Analog Circuit Design :: 01-11-2008 01:02 :: surianova :: Replies: 1 :: Views: 926
how to simulate ESD power clamp? how the stimulus look like? how long RC constant require?
Analog Circuit Design :: 12-19-2007 06:05 :: surianova :: Replies: 4 :: Views: 1014
optocoupler temperature coefficient..Soft-start controller is gentle on loads..Method offers fail-safe
variable-reluctance sensors..circuit forms adjustable bipolar clamp..Analog switch expands I2C interface..circuit safely applies power to ICs..Simple circuit forms peak/clipping indicator...
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Other Design :: 05-27-2007 17:00 :: marcony :: Replies: 0 :: Views: 934
I need help in designing transient voltage suppressors in PSPICE. I need circuit diagram for a transient voltage suppressor which can clamp voltages up to
5 Kilo Volts. I dont know about peak power rating and the reverse breakdown voltage. Please help me in this regard. I need this information very (...)
Analog Circuit Design :: 12-06-2006 18:07 :: dolu :: Replies: 0 :: Views: 888
i am designing io&esd circuit using HV process(18v),
Can i use rc -invertor power clamp for a switch controlled PAD ?
which device can i use in power rail to rail (or power cut) esd circuit , using hv process or normal process diode ?
Analog Circuit Design :: 06-28-2006 11:39 :: vivsim :: Replies: 2 :: Views: 801
It sounds like you may be getting non-destructive latch-up. The charge from the cable injects charge into your circuit causing an SCR type action.
You could put some voltage suppression (MOV, Zener, etc) to clamp the voltage to your power supply level. There are several external protection circuits that are available on (...)
Analog Circuit Design :: 01-28-2005 19:20 :: DoctorProf :: Replies: 3 :: Views: 1112