1000 Threads found on edaboard.com: Power Delay Profile
I'm working on FDTD + CPML and for now my objective is to plot the power delay profile or for other words a graph with time in order of power.
I´m using TEz mode.
The manner that I´m calculating the power in dBW is:
where I admite that (...)
Electromagnetic Design and Simulation :: 05-28-2009 09:37 :: roldao :: Replies: 0 :: Views: 1381
Is the power delay profile dependent on the carrier frequency?
I have read in many books that the delay spread for outdoor environment is in the order of 1 us. But that is for carrier frequency of around 900 Mhz. (cellular communication). I need the power delay profile (...)
Digital communication :: 06-27-2009 08:49 :: shekar1989 :: Replies: 0 :: Views: 720
I have some channel measurement data obtained in frequency domain using vector network analyzer. I would like to plot the power delay profile(PDP) of this data in Matlab. Can anyone tell me how to do this??
It is urgent...
RF, Microwave, Antennas and Optics :: 03-09-2011 07:29 :: Mesrop :: Replies: 0 :: Views: 1263
does the code bellow generate the 16-path rayleigh fading with uniform power delay profile?
Digital communication :: 05-20-2012 05:52 :: afrasiabi :: Replies: 0 :: Views: 654
Could anyone please send me MATLAB code for PDP path searcher?
PDP path searcher is one finger is Rake receiver in WCDMA
My undergraduate titile is power delay profile path searcher and i have already search about PDP path searcher and try to begin the transceiver WCDMA in MATLAB, then i'm confused to simulated path searcher..
Digital communication :: 04-17-2013 03:23 :: shivensoul :: Replies: 0 :: Views: 312
How to generate a channel with exponential power delay profile?
Thanks in advance
Digital communication :: 11-14-2011 15:39 :: David83 :: Replies: 0 :: Views: 396
Study material how to write loop in netlist to calculate power,delay bandwidth,
etc in win spice.
Analog Circuit Design :: 06-13-2006 15:49 :: ajeet_india :: Replies: 1 :: Views: 1085
could someone please tell me the speed,power-delay and power dissipation of the following devices in order.
4)emitter coupled logic
Digital communication :: 07-30-2006 03:08 :: dilip_devaraj :: Replies: 0 :: Views: 523
Energy delay product and power delay product are the two Design Parameters that has to considered when u are designing an application, say handheld battery operated device.
It depends upon which application u are going to design, In some application the Energy delay product is much important and in some appplication (...)
ASIC Design Methodologies and Tools (Digital) :: 11-29-2006 01:56 :: au_sun :: Replies: 3 :: Views: 6238
What does each metric stand for? Energy * delay and power * delay? Which of the two qualifies best a design?
Thanx in advance!!!!
ASIC Design Methodologies and Tools (Digital) :: 02-19-2009 05:35 :: kouretas :: Replies: 0 :: Views: 510
The power delay profile from the original document for the PEC situation, the power is almost always at the same level (for example the multipath components are almost always in 12dB) , and in my simulation, the power is always decreasing with time.
What kind of excitation do you use? If you use a (...)
Electromagnetic Design and Simulation :: 05-26-2009 21:04 :: iyami :: Replies: 3 :: Views: 1583
I have some measurements by a VNA and I want to plot the power delay profil and fing the rms delay spread. Can anybody vould help me.
Thanks a lot....
Digital communication :: 10-29-2009 11:42 :: alphaandomega :: Replies: 0 :: Views: 504
I'm measuring the frequency response and calculating the power delay profile. In between the transmitter and receiver, i kept the box with water(level-24cm). I'm measuring in indoor environment and also in Anechoic chamber. I calculated the rms delay spread for both cases. Indoor environment has 22ns rms (...)
RF, Microwave, Antennas and Optics :: 06-08-2012 07:14 :: david87 :: Replies: 1 :: Views: 583
I am trying to learn how to calculate power delay profile in a ray-tracing situation like this:
3-Dimensional room, Origin (0, 0, 0) at a corner.
room_dim = ;
receiver_pos = ; src_pos = ;
(distance between the Tx and Rx is sqrt((1-0)**2 + (1-1)**2 + (1-1)**2 ) = 1m
Some additional parameters:
Digital communication :: 07-24-2012 13:52 :: x201s :: Replies: 0 :: Views: 390
In digital electronics, the power?delay product is a figure of merit correlated with the energy efficiency of a logic gate or logic family. Also known as switching energy, it is the product of power consumption (averaged over a switching event) times the input?output delay, or duration of the switching event. It has the (...)
ASIC Design Methodologies and Tools (Digital) :: 08-01-2012 08:10 :: yadavvlsi :: Replies: 1 :: Views: 611
1. since you have already mentioned transmitter/receiver correlation, I guess "uncorrelated rayleigh fading" is in temporal sense.
2. regarding the power delay profile, you can refer to 3GPP specification on MIMO channel "Spacial channel model for Multiple Input Multiple Output (MIMO) simulations", see attached
Digital communication :: 04-30-2006 00:31 :: changfa :: Replies: 3 :: Views: 1319
Would anyone please have any idea about how to find the h values of a channel when you know the power delay profile of this channel
I have tried using the rayleighchan and filter commands I dont know how to find the h though which one is which. I have a 6 ray model
Digital communication :: 12-27-2008 20:58 :: leonidas790 :: Replies: 1 :: Views: 1354
I'm simulating according to the existing paper. However, I dont understand some parameters and dont know how to generate them.
Could anyone please help me?
"The variance fo additive white gaussian noise at each receiver is assumed equal and unified. The fading channel is three-path Rayleigh fading channel with exponential power delay prof
Digital communication :: 03-16-2009 04:26 :: honhungoc :: Replies: 0 :: Views: 862
I´m computing a FDTD simulator to study the radio channel characteristics using power delay profile. I use a scenario 2550px x 2550px and I need more than 2 hours to have some kind of results. I´m reading about parallel computing with parallel computing toolbox and I tried some stuff...without good results...
Tried to (...)
PC Programming and Interfacing :: 06-04-2009 12:47 :: roldao :: Replies: 0 :: Views: 1171
I´m working with FDTD+CPML with the objective of do the characterization of a radio channel.
I have done from the power delay profile, if the channel suffers from frequency selectiveness or flat fading.
Now I need to calculate the coherence distance to calculate the coherence time in order to know if the channel (...)
Electromagnetic Design and Simulation :: 06-23-2009 11:08 :: roldao :: Replies: 1 :: Views: 942
I think I need to narrow down what I want to do.
Today I thought may be I should simulate power delay profile as a fingerprint for my indoor localization project, using a ray tracer.
I found a ray tracing tool written in Java, called RAPSOR, in Sourceforge.
Unfortunately, I could not make it work (it needs netnbeans) and there is no (...)
Digital communication :: 12-17-2011 11:43 :: tienshan :: Replies: 1 :: Views: 403
I would like to generate a discrete-time time-varying multipath (doubly selective) channel. How can I do that? Also, I need the power delay profile of the multipath channel to decay exponentially. Any help will be highly appreciated.
Digital communication :: 03-06-2013 11:00 :: David83 :: Replies: 10 :: Views: 432
I want to estimate a channel based on LTE 3GPP EVA with given power delay profile (set of average power and delay of channel taps).
tau = ; % relative delay (s)
pdb = ;
Digital Signal Processing :: 03-18-2013 17:49 :: siato :: Replies: 0 :: Views: 239
I am not from a communication background and keenly interested in some advice on some problems.
I am working on a TDMA system having time slot of 14.167ms for each frame. In which 255 pi/4 QPSK modulated symbols are transmitted. Symbol time is about 55.55 us.
System have 25khz band width and system throughput is 36kbps. My fading channel mode
Digital Signal Processing :: 05-07-2009 15:13 :: moona.sheikh :: Replies: 0 :: Views: 651
as the pic shows , i design a delay cell by long channel length MOS, but the delay time is variant by VLV .
Is any possible we can design a simple circiut by only simple modified inverter and it won't be infleuence by Vcc ?
Analog Circuit Design :: 10-30-2009 04:44 :: pianomania :: Replies: 2 :: Views: 1929
propagation delay should be measured between input and output nodes..
and transcient dissipation means the switching currents of the logic..
If you want to know power dissipation.. just give 0 or 1 and measure the current through it..
Analog IC Design and Layout :: 01-10-2014 01:45 :: kenambo :: Replies: 1 :: Views: 560
I have been working in the ALU desigh using tanner EDA.
I didn't know how to calculate the delay, power delay product, etc..
Please help me in calculate this
ASIC Design Methodologies and Tools (Digital) :: 02-22-2006 04:38 :: sekartut :: Replies: 2 :: Views: 1030
I have carefully calculated the relation between SNR and Eb/N0, and currently because I simulate an OFDM system and I only use SNR on the receiver anttenna as the x-asix of the plot. I have already normalize the power of the wireless multipath channel to 1.
In the paper for comparision the detail of the channel model was not described clearly,
Digital communication :: 04-02-2006 23:12 :: carpa :: Replies: 4 :: Views: 1195
How does one simulate PDP or EDP (energy delay product)? Which parameter is normally varied? I want to obtain this result for a source-coupled logic MOS circuit I came up with but don't know how to go about simulating it. Would I sweep bias current, supply voltage or something else? Thanks.
ASIC Design Methodologies and Tools (Digital) :: 08-18-2010 17:33 :: oermens :: Replies: 0 :: Views: 1137
Can anyone help me in implementation of Tapped delay line discrete multipath channel in Matlab
h(τ) = c0δ + c1δ + c2δ + c3δ + c4δ
where multipath delay profile is given by Ac(τ) = exp(-τ/Tm) where Tm=1?sec
Digital communication :: 03-03-2012 14:19 :: vin_66_sag :: Replies: 0 :: Views: 946
@pavan garate: As supply voltage is reduced,the power delay Product of CMOS circuits decreases & delay increases.
Hence,while it is desirable to use the lowest possible supply voltage,in practice only as low a supply voltage can be used as corresponds to a delay that can be compensated by other means.
Analog Circuit Design :: 06-10-2013 05:26 :: rahdirs :: Replies: 3 :: Views: 240
FET technology iis based on the existance of a conducting channel connecting the 2 majority areas. That means for an NMOS that between 2 n+ regions must stand an n-channel. The difference between the 2 options is physially:
Depletion: the channel exists by manufacturing and when we connect the fet to voltage we control its capacitance (and ihe cur
Electronic Elementary Questions :: 07-28-2004 05:29 :: ramone :: Replies: 11 :: Views: 34315
I heard that if you want to test a new standard cell (area, power, delay ...), everybody should use ISCAS benchmark circuits (see site: )
If I design a set of standard cell (OR, INV, NAND ...) in full-custom design, how can I test my logic gates with ISCAS benchmark ?
If anybody has some example or do
ASIC Design Methodologies and Tools (Digital) :: 05-03-2006 22:23 :: hoangthanhtung :: Replies: 5 :: Views: 6454
does antenna increase the distance of transmission or send wave only??
RF, Microwave, Antennas and Optics :: 06-29-2007 13:35 :: mr_byte31 :: Replies: 6 :: Views: 727
If I use RC circuit to enlarge the power rising time to the inverter and the input rising time to inverter follows the I/O rising timing set by FPAG without RC power delay.
What is the result?
Some guy said if use this way the inverter can be damaged.
Electronic Elementary Questions :: 07-29-2007 07:54 :: EDA_hg81 :: Replies: 1 :: Views: 590
what are all the channels model for supporting wimax networks( like bad-urban delay profile etc)
Differences between them and which one is efficient for 802.16 network.
Digital communication :: 08-24-2007 02:58 :: vkekk :: Replies: 0 :: Views: 617
Why Nand gate i preferred Over Nor gate in fabrication?
Added after 2 minutes:
I know this thing that NAND gate is faster than NOR but how it is faster can anybody explain it??
ASIC Design Methodologies and Tools (Digital) :: 03-10-2008 08:21 :: gurpreet.singh :: Replies: 2 :: Views: 10676
hey buddies !!!
can ne 1 guide me ....how to plot power delay product (PDP) Vs vdd using spectre (cadence) linked with virtouso.
thnx in advanced..........
m waiting 4 a favourable reply......:
ASIC Design Methodologies and Tools (Digital) :: 06-11-2008 00:39 :: shweta_eda :: Replies: 0 :: Views: 790
another explaination: Figure of Merit
FOM is a quality representation of a design, such as power delay product in buffer desin, power gainbandwidth product in amplifier design, and so on, as far as I know.
Electronic Elementary Questions :: 09-17-2008 04:21 :: iamxo :: Replies: 2 :: Views: 1348
I'm working in FDTD+CPML and I need urgent help.
I´m simulating the situation of the paper that I send in attach.
In the case of PEC buildings, I can´t get the results of power delay profiles shown in the paper. I use a different mode than they, I use TEz mode, with the same characteristics dt and dx that they use.
Electromagnetic Design and Simulation :: 05-28-2009 11:55 :: roldao :: Replies: 0 :: Views: 1074
Simulate Rayleigh Flat Fading Channel
A broadband radio channel needs to be speciﬁed in two aspects. The power-delay
proﬁle describes a statistical power distribution of the channel over time for a signal
transmitted for only an instant. On the other hand, the Doppler power spectrum oﬀers
Digital communication :: 10-03-2010 16:30 :: alshehri :: Replies: 2 :: Views: 611
hiiiiiiii....i am new to prime time......i need to calculate the power & delay of the logic circuit which i hav....i hav simulated it in xilinx....the vhdl code is working properly bt we cant find power dissipation in xilinx na dats y i am gng for primetime tool for finding dem.......can anybody suggest me what is the next step which i (...)
ASIC Design Methodologies and Tools (Digital) :: 02-08-2011 08:34 :: nagssmiles :: Replies: 5 :: Views: 711
The concept of gradual sizing is called Logical effort.. this can be applied to all gates provided they are properly constructed with basic inverter characterized. search Google for logical effort+ stanford handout. u will find a good lecture pdf on the topic. the gradual sizing optimizes power delay product.
Analog IC Design and Layout :: 02-22-2011 13:22 :: steadymind :: Replies: 6 :: Views: 716
hi i want to design a 8 bit barrel shifter and i want to do some hand calculation such as power ,delay, noise margin.after that i should draw a schematic and do simulation.then draw layout for that.finally i must extract the circuit and do a post layout simulation for that.but i have problems. what must i see in the first simulation and how i can
Software Problems, Hints and Reviews :: 01-28-2012 02:01 :: atefehn :: Replies: 1 :: Views: 1131
Hello to everyone,
I am currently working on a MATLAB project regarding the implementation of different adapting modulaction and coding (AMC) algorithms for a mobile TDMA communication system based on an existing Matlab simulation tool developed in cooparation with my university and a company.
This project runs about 1 year now. It has been alr
Digital communication :: 04-22-2012 12:54 :: KostasN :: Replies: 0 :: Views: 897
iam using spartan3 & virtex 2pro board.i want to known how to calculate number CLB utilised in my design?is there any formula.
also need to calculate area ,power,delay plz help me
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-15-2012 00:36 :: manasasn :: Replies: 1 :: Views: 265
I want to design a 16-bi adder in 0.35um process,vdd=3.3,output load=5unit inverter, clk freq=1Ghz
I want to design with minimum power consumption.
what should I do?which methode is right?
ASIC Design Methodologies and Tools (Digital) :: 09-09-2012 11:06 :: paramis :: Replies: 4 :: Views: 392
Can anyone let me know to calculate dynamic power & delay in tanner 13 ?
And any schematics for Current Comparators using CMOS logic?
Analog Circuit Design :: 12-14-2013 11:54 :: Avinash1111 :: Replies: 0 :: Views: 259
I need a timer that after applied 127VAC/60Hz it counts let's say 20 seconds and then turn on a relay and stays on, using a transformerless power supply and a LM555 timer.
Hobby Circuits and Small Projects Problems :: 05-06-2005 19:30 :: fjpompeo :: Replies: 5 :: Views: 9560
Whichever circuit you choose, think about how it will respond to a momentary power dip.
Many products in the world don't reset properly under such conditions.
Hobby Circuits and Small Projects Problems :: 08-08-2005 07:11 :: echo47 :: Replies: 10 :: Views: 1191