10 Threads found on edaboard.com: Precharge Circuit
I wonder if the circuit has any practical use. It will take really a long to time to charge in real life, so in simulation. If finding .IC values by trial and error is too inelegant, you can spend your time in designing a behavorial precharge circuit. Not sure which approach will succeed faster.
Elementary Electronic Questions :: 04-27-2016 12:41 :: FvM :: Replies: 2 :: Views: 317
I have designed a 6T SRAM cell along with precharge circuit as depicted in attached Fig. However, I dont know what pulse is appropriate for the gate of precharge circuit (ΦB`) since precharge circuit bears the responsibility of making both BL and BLB high only before read action. (...)
Analog Circuit Design :: 12-25-2014 02:31 :: electronics20 :: Replies: 1 :: Views: 575
I am designing single ported SRAM with 6T cell. I am using cadence virtuoso.The components would be write circuit, precharge, sense amplifier, 6T cell, address decoders. It has to be 4 banks of 256 bits so muxes would also be required. How do I size each of them? All I know is about sizing 6T cell to minimum so it saves area.
ASIC Design Methodologies and Tools (Digital) :: 04-19-2014 19:30 :: Kathan Shah :: Replies: 3 :: Views: 587
I have a problem with my spice codes. When I add the precharge circuit, the error appears.
I have this problem only with finfet model. With other types, it works.
.option accurate=1 method=gear delmax=30p
.OPTIONS ABSTOL=1p VNTOL=1u
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-04-2010 07:19 :: rosaeidi :: Replies: 6 :: Views: 2378
For read operation, we need a precharge circuit to charge the bit lines. I know the precharge circuit for two bit lines.
How the precharge circuit for single bit line would look like???
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-10-2010 09:07 :: raman_87 :: Replies: 1 :: Views: 772
post the clock waveform and input waveforms... the problem is due to the timing difference between the input waveforms only... the precharge cycle is generally used to avoid problem due to difference in the arrival of the input signals...
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-12-2007 16:06 :: A.Anand Srinivasan :: Replies: 5 :: Views: 1248
The bypass capacitor of the LDO makes a very long start-up time. I want to design a LDO which can start-up within 40us, so I need a power-on circuit to precharge the bypass capacitor. Could you give me some advice in how to design a power-on circuit?
Thank you very much!
Analog Circuit Design :: 06-26-2007 09:44 :: ken_cn :: Replies: 3 :: Views: 845
most on-chip buses / interconnects are of static type buses, as opposed to dynamic logic type ones that uses a precharge and evaluation periods.
what i want to know is, are there any bus implemented using dynamic logic? and what is the purpose? i know dynamic logic will save space, and it can speed up a logic circuit. but does this also apply fo
ASIC Design Methodologies and Tools (Digital) :: 08-21-2006 15:24 :: irfansyah :: Replies: 0 :: Views: 552
In Domino circuit, there are two phases 1.precharge phase
if u take a inverter, between pmos and nmos u'r domino logic will be there.
MODL is basically used for iterative purposes.
You can read this concepts in Industrial cmos design techniques by Uyemura
Elementary Electronic Questions :: 10-26-2004 02:58 :: carrot :: Replies: 4 :: Views: 1797
I need to design a circuit to generate 1.5v~2.4v precharge voltage for large cap load(10pf).
But the working environment is too tough:1.6v~6v,
Besides the time response should not too slow(10ns~20ns).
Any suggestion or comment on it?
thanks in advance!
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-26-2004 05:00 :: jordan76 :: Replies: 0 :: Views: 1353