17 Threads found on edaboard.com: Precharge Circuit
I need to design a circuit to generate 1.5v~2.4v precharge voltage for large cap load(10pf).
But the working environment is too tough:1.6v~6v,
Besides the time response should not too slow(10ns~20ns).
Any suggestion or comment on it?
thanks in advance!
Analog IC Design and Layout :: 26.05.2004 05:00 :: jordan76 :: Replies: 0 :: Views: 943
In Domino circuit, there are two phases 1.precharge phase
if u take a inverter, between pmos and nmos u'r domino logic will be there.
MODL is basically used for iterative purposes.
You can read this concepts in Industrial cmos design techniques by Uyemura
Electronic Elementary Questions :: 26.10.2004 02:58 :: carrot :: Replies: 4 :: Views: 1494
The bypass capacitor of the LDO makes a very long start-up time. I want to design a LDO which can start-up within 40us, so I need a power-on circuit to precharge the bypass capacitor. Could you give me some advice in how to design a power-on circuit?
Thank you very much!
Analog Circuit Design :: 26.06.2007 09:44 :: ken_cn :: Replies: 3 :: Views: 578
For read operation, we need a precharge circuit to charge the bit lines. I know the precharge circuit for two bit lines.
How the precharge circuit for single bit line would look like???
Analog IC Design and Layout :: 10.04.2010 09:07 :: raman_87 :: Replies: 1 :: Views: 548
I have a problem with my spice codes. When I add the precharge circuit, the error appears.
I have this problem only with finfet model. With other types, it works.
.option accurate=1 method=gear delmax=30p
.OPTIONS ABSTOL=1p VNTOL=1u
Analog IC Design and Layout :: 04.12.2010 07:19 :: rosaeidi :: Replies: 6 :: Views: 1232
I just designed this small circuit (reusing some components already in the flyback circuit). This charges the Vdd capacitor with 2 mA until it reaches 10 V.
If the auxiliary winding is providing power to Vdd it should reach 14 V --> precharge circuit off. I chosed a PNP transistor that should withstand the peak power during (...)
Power Electronics :: 23.08.2013 09:05 :: emontllo :: Replies: 2 :: Views: 167
most on-chip buses / interconnects are of static type buses, as opposed to dynamic logic type ones that uses a precharge and evaluation periods.
what i want to know is, are there any bus implemented using dynamic logic? and what is the purpose? i know dynamic logic will save space, and it can speed up a logic circuit. but does this also apply fo
ASIC Design Methodologies and Tools (Digital) :: 21.08.2006 15:24 :: irfansyah :: Replies: 0 :: Views: 327
post the clock waveform and input waveforms... the problem is due to the timing difference between the input waveforms only... the precharge cycle is generally used to avoid problem due to difference in the arrival of the input signals...
Analog IC Design and Layout :: 12.12.2007 16:06 :: A.Anand Srinivasan :: Replies: 5 :: Views: 778
Yea, its a switched mode charger with fast charge of 1 amp (precharge and maintenance charge at 250mA).
The transistors I'm using are straight from the specified part in the schematic in the datasheet and aren't getting exceedingly hot anymore.
I fixed some wiring issues so it matches the schematic now and I have LED indicating state but the
Hobby Circuits and Small Projects Problems :: 25.05.2008 01:51 :: R2c2 :: Replies: 5 :: Views: 1519
I got it.
Another precharge ckt works after the 100mV voltage difference is generated, because the circuit is large I did not notice that at first.
ASIC Design Methodologies and Tools (Digital) :: 05.09.2008 05:12 :: iamxo :: Replies: 3 :: Views: 610
I`m very new to HDLs, so please bare with me.
I want to design a dynamic decoder (precharge & evaluate).
The way I would do it in my analog designs is with a prechrge PMOS and discharge NMOS devices.
I was wondring if the same can be done with verilog.
I want to write behavioral code and synthesize a transistor level implementation.
ASIC Design Methodologies and Tools (Digital) :: 16.09.2010 11:56 :: eladla :: Replies: 1 :: Views: 384
Charge sharing is SI issue in dynamic logic design. There two phases in a dynamic logic precharge and evaluate. The charge stored on the output node during the precharge phae will be redistributed over o/p node and mos transistor in the discharge path. This causes a drop in output voltage and this cannot be recovered due to the dynamic
ASIC Design Methodologies and Tools (Digital) :: 12.02.2011 23:09 :: phoenixpavan :: Replies: 5 :: Views: 1286
To calculate the offset of a comparator with a reset (precharge - track, what ever) I strobe the output to get only the evaluated data.
For example, this is the output/input of track-and-latch comparator. If I were to check when the output crosses zero, I would get wrong results. So I strobe the output to get only the data I want. (the gray outp
Analog IC Design and Layout :: 08.05.2011 06:19 :: lamoun :: Replies: 12 :: Views: 1027
At least in operation, the bootstrap capacitor should be charged during diode conduction time. But I agree, that an auxilary circuit to precharge the bootstrap capacitor can be required. I assume, that activating the low side switch without the HS would be sufficient in most cases.
Power Electronics :: 24.06.2011 16:25 :: FvM :: Replies: 15 :: Views: 1306
The rule is to connect the body to at most the lower of drain/source voltages, ie at least 3VDD-Vth or below.
There is no rule to state that the body must be tied to either source or drain. It can be any other suitable node.
But your application seems to be a charge pump with your NMOS being the precharge diode. In such cases, you tie the body to
Analog IC Design and Layout :: 25.05.2012 14:41 :: checkmate :: Replies: 6 :: Views: 460
The circuit has not starpoint, in so far you can say that the voltage starts from zero.
To start from mid supply, you have to disable all transistors at startup and would precharge the filter.
Electromagnetic Design and Simulation :: 14.05.2013 08:07 :: FvM :: Replies: 6 :: Views: 261
I have a question about write operation of 6T sram
I know for sram read:
phy2 : precharge both bitlines high
phy1 : Then turn on wordline, One of the two bitlines will be pulled down by the cell
for sram write, my question is that during phy2, does the bitline and bitline_bar need to be precharged? I got this question from a tutori
Analog Circuit Design :: 27.08.2013 19:26 :: onion2014 :: Replies: 0 :: Views: 185