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Problems Logic Gates

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4 Threads found on edaboard.com: Problems Logic Gates
I am having some problems simulating IC schematics with there any other software like hspice to simulate IC circuits.
Hi all, How the timing parameters - set up and hold time of a flip flop can be met, by using simple logic gates. Please try to explain with some example and diagram. Thanks
Imagine a combinatorial cloud, with n inputs and m outputs, the combinatorial logic inside the cloud can be any combination of logic gates. If some of the outputs are fedback to some of the n-inputs, we have a combinational loop. This causes problems in timing analysis.
Thanks