246 Threads found on edaboard.com: Process Parameters
Scattering parameters once a TRL calibration is performed are referred to the Zc of the micro-strip line.
Determining with measurement Zc (that is not an outcome of the calibration process) is a problem ( myabe a next question to ask about).
However from the theory we know that Zc is in general complex.
Let say nearly real, but with a small imag
RF, Microwave, Antennas and Optics :: 02-07-2017 12:19 :: aleberto :: Replies: 0 :: Views: 2
The technology file contains process specific parameters such as layer thicknesses and the sheet resistance of the various layers, isn't it.
So should I have a technology file to make schematic simulation?
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-03-2016 05:58 :: Bakr.hesham :: Replies: 3 :: Views: 456
please share the parameters for 90 nm cmos process
drain current,small signal parameter and intrinsic gate capacitance parameters for 90 nm cmos process (T=300k)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-20-2016 18:03 :: email@example.com :: Replies: 1 :: Views: 415
Dear All ;
I 'm using sentaurus workbench as attached GUI in simulating multigate mosfet , and I need to add to parameters (number of fins and supply voltage ) as input parameter to the user to sweep on them I added them but can't add the command lines corresponding to those parameter in the sentaurus process input command file , I don't know in
Electromagnetic Design and Simulation :: 04-01-2016 11:42 :: EngAmira :: Replies: 0 :: Views: 481
typically the Avt and Beta mismatch parameters are given in the process design specification.
They should also be included in the bsim models, or some additional statistical file.
Analog Circuit Design :: 03-07-2016 12:40 :: buffallo :: Replies: 2 :: Views: 465
Info: I am using cadence IC6.1.6 and I have access to process Design Kits from a commercial foundry (PDKs)
My aim is to have the ability to manipulate the model equations and parameters for the bipolar vbic model (or other models if possible) but for the specific process that I use from the fabrication foundry (the foundry supplies (...)
Software Problems, Hints and Reviews :: 03-06-2016 04:02 :: abdoabd :: Replies: 0 :: Views: 520
Mismatch parameters are process dependent, so you can find them in additional Monte Carlo simulation files if your process provider (foundry, fab) provides them, see e.g. this tutorial, pp. 10 ff.: 123178.
process size dependent Avt values for estimations you can find i
Analog Circuit Design :: 11-14-2015 22:44 :: erikl :: Replies: 1 :: Views: 482
From a sensitivity analysis following a process only monte carlo analysis, I have a variance contribution report showing that the main contributions to the noise figure of a Low-noise amplifier are due to the parameters xbpos, xncjcu and xndren. I am using the IBM process BiCMOS8HP and ADEXL (Spectre RF). Any one who knows where to (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-08-2015 17:32 :: abimana :: Replies: 1 :: Views: 499
I'd suggest to study any of these analog circuit design textbooks. Binkley's book (No. 8, at the bottom) shows most of these parameters (and a lot more) for a 0.5?m process (pp. 42 ff).
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-08-2015 13:49 :: erikl :: Replies: 1 :: Views: 481
If you start with non-zero initial parameters, the iterative process won't arrive at all zero in one step. By watching the parameters and error square sum, you get an idea what goes wrong.
To know reasonable parameters, you can perform the fit with a spread sheet calculator, e.g. the Excel solver.
Microcontrollers :: 09-01-2015 08:01 :: FvM :: Replies: 4 :: Views: 441
I am new to the IC design domain...Where can I find the parameters of the 90nm technology process...???
Thanks and regards..
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-22-2015 13:57 :: rahul91 :: Replies: 1 :: Views: 667
The model file must match the process technology, i.e. you can use any advanced model file from PTM for the 45nm process.
Analog Circuit Design :: 08-07-2015 18:32 :: erikl :: Replies: 3 :: Views: 492
I'm beginner in automatics and could use your advice.
So, I'm designing a PID regulator for oven and right now I'm trying to tune the Kp, Ki and Kd parameters. The oven has nice step response that gets easily approximated by the PT1 system with the dead time delay.
Robotics and Automation Forum :: 07-31-2015 15:16 :: Pero2912 :: Replies: 2 :: Views: 1064
process corner, voltage, temperature, number of tracks (i.e. cell height), threshold voltage, channel length, whether specific cells are available (E.g. UPF support).
ASIC Design Methodologies and Tools (Digital) :: 07-14-2015 10:43 :: jbeniston :: Replies: 6 :: Views: 461
I think this foundry kit is just prepared for MC mismatch parameters, which will be provided after corresponding silicon evaluation and measurements.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-12-2015 14:59 :: erikl :: Replies: 7 :: Views: 1136
what parameters should i use to design my trans conductance amplifier in 180 nm process?
As a designer, you should know what are the parameters needed to design an amplifier. It normally starts with your specifications (gain,bandwidth etc.) . From that you will be able to configure out what you should do.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-16-2015 09:57 :: deepsetan :: Replies: 5 :: Views: 771
Run a Monte Carlo analysis - if your transistor models include mismatch and/or process variance parameters - and display the delay measurement statistics ordered in your control file.
Analog Circuit Design :: 03-13-2015 12:40 :: erikl :: Replies: 1 :: Views: 398
I am trying to find the parameters of a surface mounted PM synchronous motor using the application note AN4680 (PMSM Electrical parameters Measurement) and had some queries regarding it.
The Ld and Lq inductance measurement process is mentioned as follows
Power Electronics :: 02-16-2015 19:59 :: Umit45 :: Replies: 0 :: Views: 473
I would like to know if the TSMC 90nm transistor models from T-N90-CM-SP-004-K1/T-N90-CM-SP-013-K1 process Desgin Kit consist reliability parameters for Cadence Reliability Simulator.
Thank you for reactions.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-08-2015 17:38 :: kovibb :: Replies: 2 :: Views: 732
I'm using siliconsmart for library characterization, the model I'm using is BSIMCMG and PTM.
BSIMCMG describes the mathematical model of finfet in verilog-A. PTM lists process parameters in their model files.
When I was trying to import the spice netlists, I got the following error messages on every netlist:
ASIC Design Methodologies and Tools (Digital) :: 01-25-2015 21:55 :: yyffe :: Replies: 0 :: Views: 866
There is no minimum/maximum W/L specification, you can make it whatever you want. The only restriction is that W and L has their minimum lengths. Both should be specified in the PDK of your process and in few occasions in the model with parameters wmin and lmin.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-06-2015 17:12 :: csolis_GT :: Replies: 2 :: Views: 492
Maybe You exceess the maximum dimensions? If your process has halo implants, the maximum length of RF fets is limited (240nm for example).
On cadence forum is thread about this warning for mimcap, exceeding maximum width.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-05-2015 13:03 :: Dominik Przyborowski :: Replies: 5 :: Views: 1003
If you want to see 10dBm output power while the input is driven with -20dBm, the Gp must be 30dB.
Changing the model parameters in a large signal model of a transistor is not solution because model has been extracted for that transistor and it must be constant during design process.
What is your intention by changing model parameters ?? It (...)
RF, Microwave, Antennas and Optics :: 12-21-2014 16:12 :: BigBoss :: Replies: 1 :: Views: 468
I have OTA schematic with nmos sizing is 50um/10um(w/l) and pmos sizing is 10um/10um(w/l) .this schematic is implemented in 0.35um technology. i have to implement the same schematic in 90 nm . i want to know how calculate w/l ratio for 90nm technology.
If you know the process parameters ( e.g. beta,K ) you can sca
Analog Circuit Design :: 12-15-2014 17:32 :: BigBoss :: Replies: 2 :: Views: 558
Without knowing any of your parameters
bulk or epi process
type of circuit
power consumption of circuit
guard ring spacing
guard ring width
... I'd advice: max. contact spacing < 5*contact_size .
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-24-2014 13:57 :: erikl :: Replies: 3 :: Views: 981
Using a 'hardware' mathematical calculation processor is faster than using maths software .
You load the maths processor with the calculation parameters and start the calculation process, when the result is available, the maths processor will create an interrupt to the main (...)
Digital Signal Processing :: 11-12-2014 09:09 :: esp1 :: Replies: 4 :: Views: 758
I am designing a DCXO block which clock is 26 Meg. But, using crystal model R/L/C parameters showed in picture, I can't get accurate 26Meg value by formula
Here is the process of calculation, I select a set of R/L/C parameters
1.From calucation, error of frequency is about 337ppm. it is too larger for our design
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-27-2014 03:55 :: kkt51 :: Replies: 2 :: Views: 458
it depends on a number of parameters in particular how fast the serial data is arriving and the speed of the host system.
1. As the serial data arrives the SerialPort event handler can put it into a buffer (ring buffer, double buffer, ??)
2. a BackgroundWorker can process the data a pass it to a Chart component
if the data is arriving too fa
PC Programming and Interfacing :: 08-28-2014 05:29 :: horace1 :: Replies: 17 :: Views: 3592
... I need an approximate estimation of this mismatch to calculate the unit capacitance value.
Mismatch parameters depend on process size. If you can't get them from your foundry, try these approximate values from this thread.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-02-2014 12:32 :: erikl :: Replies: 1 :: Views: 471
I'm just about to design a "connector evaluation card" to correlate some model-based s-parameters for a connector pair we're going to use for ~8Gb/s transmission (so I'll want data that's good to maybe 20GHz...the extent of my N5230A). What I want to have at the end of the process are s-parameter data for the mated connector pair only,
RF, Microwave, Antennas and Optics :: 07-01-2014 15:50 :: OrangeTwin :: Replies: 0 :: Views: 366
Of course you can analyse/measure all these parameters with this tool - if you have the appropriate (standard) library for a special technological process.
Analog Circuit Design :: 06-27-2014 20:03 :: erikl :: Replies: 2 :: Views: 442
I have the following circuit which was designed in AMI0.5 um process which needs to be converted to TSMC 0.35um process for simulation on cadence. Can somebody please tell me how to calculate the transistor sizes in order to have a correct operation?
parameters: Vin=3.7V, Vout=1.8V, load current=300mA, switching frequency=1MHz (...)
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-23-2014 12:42 :: tabascorez :: Replies: 6 :: Views: 848
I need process parameters to get the following:
sigma_vth = (q* tox / eox ) * sqrt (Na*Wd / (3*L*W)) ---
tox is oxide thickness
Na is effective channel doping
Wd is the depletion region width
Now, I have 90 nm spice parameters, but I do not know which parameters represent these values. Specifically
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-10-2014 05:00 :: naeemmaroof :: Replies: 2 :: Views: 705
I am trying to write a python process code for 40nm double gate soi n- channel mosfet and have got stuck with some parameters which are :
vertical and lateral characteristic length of source/drain doping, Rmax and Rmin of source/drain doping, offset length i.e source/drain implant measured from poly edge, well doping concentration, Rmax an
Software Problems, Hints and Reviews :: 03-04-2014 17:51 :: mini11 :: Replies: 0 :: Views: 491
You have to specify first the type of the meter you are using, and also some parameters regarding the process itself.
Mechanical Engineering and Design :: 02-28-2014 22:41 :: eehero :: Replies: 1 :: Views: 2023
Has anyone encountered this error before? I can provide more information as needed. Apologies if unclear, I'm new to this.
PML Setup: PML Material parameters are out of sync with the problem setup and need to be recalculated using the PML Setup Wizard.
Adaptive solution setup, process hf3d error: Failure in source
Electromagnetic Design and Simulation :: 01-22-2014 22:07 :: fbodruck :: Replies: 0 :: Views: 503
I have an ICT Setup for Hardware Testing.
Can anybody suggest me what System parameters/process parameters we need to focus for Maintainence of the ICT Setup/ Fixture?
PCB Routing Schematic Layout software and Simulation :: 12-22-2013 13:20 :: hrerocker :: Replies: 1 :: Views: 401
This is definitely not a PI controller transfer function which has a simple and well-known shape. May be it's the transfer function of the control process and the said parameters are describing the result of controller tuning.
Elementary Electronic Questions :: 12-18-2013 17:38 :: FvM :: Replies: 11 :: Views: 2042
I am trying to simulate an analog circuit in hspice linux. I am using the parameters of IBM 0.13um CMRFSF process.
The Hspice not run due some VA compilation problem.
In the .lis file the following mensage is shown:
*pvaE* Please invoke hspice script instead of binary.
**error** call to epvaHDLinit failed.
**error** Failed to read ver
Software Problems, Hints and Reviews :: 10-17-2013 17:59 :: lucas_severo :: Replies: 1 :: Views: 1760
I am writing a macro (structure/global) to automatically build up my planar antenna. Using the parameters I can easily and fast change the geometry by using the history update function.
To further improve the design process I want that macro to add a post-processing macro (under the shift-P window).
Unfortunately the history (...)
Electromagnetic Design and Simulation :: 08-22-2013 16:43 :: rootrich :: Replies: 0 :: Views: 744
Extrapolating from a different model file (different foundry and different process size) I'd guess the following:
The parameters to be calculated (all starting with the letter d) from only a few secondary parameters (a1prf, a1nrf, a1rf_18, a2rf_18) are not parameters for the calculation of vth itself, bu
Analog Circuit Design :: 08-09-2013 22:13 :: erikl :: Replies: 10 :: Views: 1255
Hello! I added MOUNT-PAD-ROUND3.0 from standard library named "holes", but where is the hole? I mean, i can see hole in the pad, but where it parameters that would be using fo drilling, i can see only center, without diameter. For me it is not obvious, how PCB shop will process my board. Should i do something with it or it is okay?
PCB Routing Schematic Layout software and Simulation :: 07-14-2013 19:56 :: Terminator3 :: Replies: 0 :: Views: 643
I guess you are talking about pre-estimated rather than controlled impedances. Controlled impedance involves test structures that are measured after production of a sample board and adjustment of PCB process parameters to meet the specified impedance. The procedure is respectively costly.
Pre-estimated impedance means that trace widths are calcu
PCB Routing Schematic Layout software and Simulation :: 06-11-2013 17:01 :: FvM :: Replies: 4 :: Views: 2415
Perhaps these Predictive Technology Models (PTM) may help you: click Nano-CMOS, then change to your process size. Here - if need be - you can still adapt some parameters, then click Submit. Now you can download NMOS worst-case, typical, and/or best-case model parameters. Same procedure for
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-22-2013 13:25 :: erikl :: Replies: 6 :: Views: 1040
... will you plz tell me where is LD & WD in my file.
Your file doesn't contain these parameters. May be they're hidden somewhere in a general process file. Try and search for them!
... if i'll use value given by ur file is their any problem in calculation?
Don't think so.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-09-2013 20:14 :: erikl :: Replies: 3 :: Views: 1236
I am running monte carlo simulations and wanted to know if there is a way to save all the process parameters values during each iteration.
To be more clear, say I run 10000 samples varying vth, tox & u, I want to save the values of these 3 parameters during every single sample out of 10000
Analog Circuit Design :: 04-30-2013 15:09 :: satishgra :: Replies: 0 :: Views: 607
Is there a reason you can't generate it in simulink? It may help you visualize the process before coding it in matlab.
Digital communication :: 04-16-2013 08:22 :: newtonoid :: Replies: 5 :: Views: 2559
I have a VHDL code for a system that implements clock recovery. Right now, we are using an FPGA and want to replace it by a microcontroller. The code includes various processes. A process in VHDL is like a function but consists of a sensitivity list that contains parameters which decide when the process is executed. eg. (...)
Microcontrollers :: 04-01-2013 23:25 :: krutarth :: Replies: 0 :: Views: 365
Threshold Voltage: VT (or VTH0 in the AMI model; dvthn considers the deviation of statistical process spread)
Mobility: U0 [cm2 (a fitted parameter from extraction, recognizable by the many decimal figures). Use it if you don't find better sources.
lambda is a (to be) SPICE-calculated parameter, which considers a lot o
Analog Circuit Design :: 04-01-2013 17:41 :: erikl :: Replies: 1 :: Views: 2534
I got a circuit netlist including TX and RX blocks supposedly located on different dice. It'd be helpful to run transient simulation with separate process corners for the subcircuits, say SS for TX and FF for RX.
The problem is, all the devices point to a same library which includes a bunch of parameters and macro-models. Therefore it'll be ver
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-15-2013 03:12 :: cise :: Replies: 0 :: Views: 648