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7 Threads found on edaboard.com: Ptat Feedback
Usually, please some one correct me if I am wrong, there are two stable states for this kind of circuits. Depending on the initial conditions the circuit could go to a state where the current is zero, so for this reason some sort of start up circuitry is needed. There can be a third stable state, if you close the
Hi palmeiras, here are some new outcomes from my side: 1) When you wrote: “the resistor leading to a reduction in VGS2=VGS1”. Do you mean VGS2 minus VGS1, right? Because VGS1 is always different from VGS2, never equal. Sorry, this was a typo: Of course it must be Vgs1=Vgs2+Ids2*Rs=Vgo2 (referred to ground). A last thing:
Could anyone explain where's the positive and negative feedback in the attached ptat current ref? Thanks a bunch!
Can anybody help me? how to connect the "+ -" input of the opa to form negative feedback in the ptat circuit?
i generated a reference voltage Vcm (0.9V) from the output of ptat,but how to use it to reset the opamp output vout+ and vout- in reset phase of sc-opamp? i tried many times,but it doesn't work well. how to drive a resistive laod(such as output of opamp)? Vcm is generated by resistor divider and opamp (through feedback),the value is exact in so
benchen: you are right. The ptat current which consists of BandGap that can be used to bias the erro amplifier. I think the sequence is : ptat is ready, then erro amplifier is working normally after biases is ready by feedback. Maybe, the response speed is not so fast. But, generally, it is enough. There is not any problem. (...)
the question is : 1. do the pmos worked in the saturate? 2. why did the Iptat not to change when i changed the M (the number of pnp)from 8 to 16 ? thank you first


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