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11 Threads found on edaboard.com: Ptat Startup
You could start with just what "didn't work" means. A result you didn't like, or failure to produce a result at all? bandgap / ptat loops without explicit startup mechanisms, can easily converge in one testbench and fail in another, because when they start up they're doing so on "numerical noise" which depends on the circuit matrix and algorithm
hi all, i got PATA current from Razavi at chapter there is no more detailed start-up for this circuit. whether the circuit needn't start-up circuit? if start-up circuit must have, can anyone recommend or what document i can r
Hi palmeiras, here are some new outcomes from my side: 1) When you wrote: “the resistor leading to a reduction in VGS2=VGS1”. Do you mean VGS2 minus VGS1, right? Because VGS1 is always different from VGS2, never equal. Sorry, this was a typo: Of course it must be Vgs1=Vgs2+Ids2*Rs=Vgo2 (referred to ground). A last thing:
I have used junction capacitors as startup circuits in bipolar ptat & bandgap designs and they work fine provided you ensure there is a discharge path for the capacitor. I cannot remember the exact mechanism in the designs I did but there was a distinct, predictable discharge path when the power was removed (possibly through one of the wells being
A ptat current reference circuit is based on the concept of adding (subtracting) vbe voltages. Typically you would use two vbe voltages with different areas and a resistor closing the loop to put the ptat voltage across it. Such a circuit has two stable Operating Points, one of them is with every voltage equal to zero, the other one is the desired
Hi For 1.5V supply I would not use the classical bandgap approach The classical approach will show some serious problems in the low-temp/slow corners, especially during startup ... Look out for some papers about low voltage bandgaps. The basic idea there is, that you add a ptat and an iptat current. THis current is injected into a (...)
Simulate the supply ramping with a transient simulation. Use either a positive and a negative offset on your error amplifier. If only one polarity works you get the issue. startup in CMOS bandgap set the operating point at a value where the ptat generate enough voltage to overcome offsets.
Transient is the only way to do startup sims. You should ramp Vdd very slowly (1 second for 0-3.3v for example) and watch to make sure your circuit starts. Cold is usually worse if your circuit uses ptat currents since they are smaller at cold. Slower ramps are always worst case, because some circuits get "knocked into startup" by (...)
That is true! The ptat loop which generate a voltage difference close to zero at the target operating point is dominating the speed. If the regulator output is driving the bandgap voltage and get its input from the ptat voltage difference output it could be described as a frequency transfer function. There is depending on current density a paras
Where is charging device for A or B node? self-bias circuit, ptat current mirror, op-amp
The main circuit is the ptat core. It is enclosed into a regulation loop which try to equalize the currents I1 and I2. The resulting current Iptat=I1=I2 is the ptat current. The equations for the ptat circuit is I1*R+VT*ln(I1/(a*IS))=VT*ln(I2/IS), "a" emitter area ratio the solution for I1=I2 is (...)