11 Threads found on edaboard.com: Pull Up Pull Down Network
I would think that the static and dynamic are more related to digital side of things. The transitor level implementation of the D-FF can be of pull-Up/pull down network, E-TSPC, or TSPC which for the E-TSPC and TSPC are dynamic.
Just my thoughts.
RF, Microwave, Antennas and Optics :: 12.05.2006 23:33 :: wchu01 :: Replies: 1 :: Views: 802
Depending on whether the MOSFET is NMOS or PMOS. NMOS is used for pull down network. PMOS is used for pull up network. So, gate is from 7407, Power to Drain and fan to Source, the other terminal from fan will be connected to Ground.
Gate = The control of inversion layer. (...)
Electronic Elementary Questions :: 28.09.2010 00:04 :: john blue :: Replies: 5 :: Views: 919
connect it to a transistor and use a pull down network :)
Electronic Elementary Questions :: 16.12.2010 04:04 :: john blue :: Replies: 5 :: Views: 858
I'm doing a project using atmel8951. The pin5 0f port3 goes low even after pulling it up. The adjacent pins have no problem. I checked the network array resistor , it works fine. But on connecting it on the pcb, its pin connected to pin5 of port3 goes down
Is it due to the damage of the pin5 of port3?
Microcontrollers :: 08.02.2012 03:08 :: avirajose :: Replies: 4 :: Views: 246
SIM900 support the reset function, when the MCU find the module is in an abnormal state, SIM900 can be restarted by pulling the RESET pin to ground for a typical 50uS. Reset is a noise sensitivity pin, it should be kept away from the high speed signal line (eg. clock) when layout. This pin is internal pull up to 2.8V through (...)
Digital communication :: 01.03.2012 06:07 :: akvii :: Replies: 2 :: Views: 3344
It's a systematic design procedure...
You should check on stick diagram first. In Euler path we are conceren on the pull-up and pull down current network.
The important notation is the Vdd, input node( a,b, etc ), Output(usually denoted F) and Vss. The path should start with Vdd (...)
Analog IC Design and Layout :: 20.09.2005 07:38 :: Syukri :: Replies: 5 :: Views: 5006
S and LS gates are similar, so see page 12 of the ON Semiconductor LS TTL Data book:
I changed the text's transistor numbers to match your diagram:
Referring to Figure 1, the base of the pull-down output transistor Q6 is returned to ground through Q3 and a pair of resistors instea
Professional Hardware and Electronics Design :: 21.11.2005 02:13 :: echo47 :: Replies: 3 :: Views: 1380
ya it is correct because in cmos the pull up network is of ptype and pull down network is of n type
and for proper functioning we r tied the vdd to the source of the ptype and gnd to the source of n type
and taking o/p at drain of both n type and ptype which is tied (...)
ASIC Design Methodologies and Tools (Digital) :: 09.01.2007 08:27 :: rakesh1234 :: Replies: 7 :: Views: 782
Static power disipation is the power dissipated when the inputs are not changing...
In CMos we use complementary devices for the pull up and pull down network...
So when either is on the other is off... so naturally there is no direct path between Vdd and Gnd... Only path exists (...)
ASIC Design Methodologies and Tools (Digital) :: 21.04.2008 16:36 :: lordsathish :: Replies: 1 :: Views: 747
Considering the Nand4 gate:
1) The pull up time will be data dependent, i.e. you have to see how many PMOS are ON at a time. Worst case will be 0111 and best will be 0000
2) For pull down time, due to velocity saturation, the effective resistance of the Four series NMOS will be reduced, so you will not (...)
ASIC Design Methodologies and Tools (Digital) :: 02.04.2009 07:57 :: animeshjn :: Replies: 10 :: Views: 2725
Hello I am new to this forum although I have used this site for some time.
I got stuck with the following task and need some help.
I have to draw a transistor diagram of a CMOS gate with the following logical
F (a, b, c) = (a * b + a * c + b * c) '
The gate must be made up of only One pull-up and a (...)
Electronic Elementary Questions :: 16.09.2011 17:45 :: mr_l :: Replies: 2 :: Views: 542