1000 Threads found on edaboard.com: Pull Up Pull Down Network
If you have true Tri-state logic (H+L+Z) ie in bus transceivers were both pull-up or pull-down could be used to prevent floating inputs, pull-up is the prefered solution because of noise margin in TTL compatible circuitry is larger in H state than in L (that's one of the (...)
Professional Hardware and Electronics Design :: 01-20-2003 14:55 :: turttle :: Replies: 11 :: Views: 4412
can any one help me in selecting a pull up/pull down resistor value
Electronic Elementary Questions :: 12-19-2006 09:26 :: prasannabalaji :: Replies: 8 :: Views: 1418
Hi,who can tell me why & when use pull up & pull down resistor?
One good point missed out (I think) is that a pull UP resistor is used to pull the voltage to the supply (usually +5 VDC) and a pull (...)
Electronic Elementary Questions :: 05-16-2008 03:06 :: dunn :: Replies: 7 :: Views: 1425
most of sensors and digital ICs have open collector configuration and hence their output voltage doesnt reach the supply... in those cases a pull up resistor is needed which is nothing but a resistor to the supply... this supplies current to the output from the supply effectively reducing the load offered to the output pin...
Analog Circuit Design :: 07-09-2008 16:21 :: A.Anand Srinivasan :: Replies: 2 :: Views: 598
pull up or pull down RB0 is not the real problem.
answer first to this question :
what is the source of the signal you apply
on RB0 pin ?
a passive component, as,a,relay reed contact ?
or the ouput of a active component
ie output of a 7406 ttl driver
you have to considere booth decide if (...)
Microcontrollers :: 10-06-2013 04:05 :: paulfjujo :: Replies: 8 :: Views: 482
Another question,usually,what's the internal pull-up resistor value can be called weak pull-up?
ASIC Design Methodologies and Tools (Digital) :: 07-25-2004 07:53 :: zcq :: Replies: 11 :: Views: 4813
What is the typical value for a pull up or pull down resistor?
IL be using this in Microcontroller GPIOs.
Hobby Circuits and Small Projects Problems :: 08-10-2005 20:51 :: ece4afe :: Replies: 3 :: Views: 2392
Hi all: I download a data of download cable from Altera, I don't find that the
10-pin need connect to pull up resistance and pull down resistance, but somebody tell me that if CPLD has no pull up resistance and (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-11-2005 21:59 :: wjx197733 :: Replies: 0 :: Views: 785
Plz clarify my doubt
which is better pull up or pull down
Analog Circuit Design :: 04-25-2007 05:54 :: saurav_sdpl :: Replies: 4 :: Views: 1764
See for a good explanation for both pull up and pull down:
Hobby Circuits and Small Projects Problems :: 09-22-2007 15:24 :: plusminus :: Replies: 1 :: Views: 1487
pull up by nmos and pull down by pmos works??
Electronic Elementary Questions :: 09-02-2008 15:07 :: elexian :: Replies: 3 :: Views: 2246
A pull-up device when energized will pull the ouput to supply(i.e "1") and a pull-down will pull the output to ground (i.e. "0").
Usually PMOS is used for pull-up since it can provide GOOD "1" (HIGH) i.e (...)
Analog IC Design and Layout :: 04-22-2009 05:50 :: prakash_nb :: Replies: 1 :: Views: 3481
I am looking at one IO buffer design from other Sr person, he used all N devices for both pull up and pull down, please refer to the schematic of attachment.
Everyone says N pull up will reduce swing from VCC to VCC-vth, can anyone explain why he designed (...)
Analog Circuit Design :: 12-03-2010 20:29 :: euchee :: Replies: 1 :: Views: 547
Check IC datasheet. It has reference application circuit that shows if this pin should be pulled high or low, and the pull resistor values.
Usually 10k resistor is used for 5V devices, and 4k7 for 3.3V and 2.5V devices.
In this way, you do not need to calculate any value.
ASIC Design Methodologies and Tools (Digital) :: 07-03-2011 12:56 :: SkyHigh :: Replies: 6 :: Views: 2721
Is it possible to use internal pull up or pull down resistors and make them appear (or dissapear) only when a certain logic condition is satisfied ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-24-2012 19:14 :: shaiko :: Replies: 3 :: Views: 694
pull up and pull down resistors is same as pull up and pull down transistors in CMOS. pMOS as pull up and nMOS as pull down.
ASIC Design Methodologies and Tools (Digital) :: 08-06-2012 00:11 :: maulin sheth :: Replies: 9 :: Views: 1069
Hello everyone, I need your help! Thank you in advance.
Does anyone know the approximate value for the pull up PMOS, the pull down NMOS driver, and access NMOS transistor for 40nm or 32nm sram cell? I just need a approximate value for reference.
We want to do a hspice simulation for a sram cell (...)
ASIC Design Methodologies and Tools (Digital) :: 08-29-2012 13:00 :: phuang :: Replies: 1 :: Views: 779
pull-up and pull-down resistor is a common mechanism used in basic electronic circuits. pull-up means connection of a line or chip, with supply voltage though a resistor with a value of few kOhms. This kind of connection results in maintaining high state, when the external (...)
Show DIY :: 12-15-2012 12:24 :: Vermes :: Replies: 1 :: Views: 1396
What is drive current for a PAD and how to decide drive current for I/O PAD while doing characterization.Also how to calculate the pull-up and pull-down resistance for I/O pad cells.
Analog IC Design and Layout :: 03-31-2013 01:25 :: dileep4111 :: Replies: 7 :: Views: 716
I am doing library characterization for bidirectional pull-up(PDU02DGZ from tsmc) and pull-down(PDD02DGZ from tsmc) cells.Help me how to simulate for pulling resistance.
Analog IC Design and Layout :: 04-17-2013 09:30 :: dileep4111 :: Replies: 1 :: Views: 304
Hi Mentor ,
I want to know about pull Up and pull down Resistor with Applications.
Thanks in Advance
Electronic Elementary Questions :: 03-29-2014 07:22 :: DigitalWork :: Replies: 4 :: Views: 510
i'm working with non-series-parallel arrangements, something like this:
as you can see, the euler paths in pull-up and pull-down are differents. for example, in pull-up we have "abcde" and in (...)
ASIC Design Methodologies and Tools (Digital) :: 09-04-2014 03:41 :: nrb1981 :: Replies: 1 :: Views: 121
No, a weak pull-down is a large resistance (or equivalent, i.e. it might be an active device on a chip), as high a resistance as possible which overrides any leakage currents to guarantee a valid logic 0 voltage. Smaller values would waste power when driven high, higher values would not guarantee a logic 0.
Analog Circuit Design :: 08-06-2004 04:31 :: barny451 :: Replies: 7 :: Views: 11224
Test pin pull-down is required
Microcontrollers :: 02-10-2005 03:45 :: niks :: Replies: 3 :: Views: 659
use constraint editor of xilinx ise to add pullup for io signals
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-16-2006 06:05 :: kib :: Replies: 6 :: Views: 9155
For pull ups, look at the leakage current of the pin.
For example, the MCLR pin of a pic micro is typically 5uA. Too high a pull up value will result in a voltage drop which might make the micro reset with a little noise on the line. The highest recommended value in this case is 33K.
Electronic Elementary Questions :: 08-19-2006 16:36 :: btbass :: Replies: 15 :: Views: 6352
The pull-up resistor only acts as a "weak" pull-up source.
So when slave drives low, the net will be pulled-down to '0'.
You can also refer to the open-drain circuit.
ASIC Design Methodologies and Tools (Digital) :: 11-30-2006 09:10 :: joe2moon :: Replies: 6 :: Views: 1268
pull ups depend values depend on the technology used ,Bipolar or cmos .but also the FAN OUT ..which means how many inputs that signal feeds .The more inputs connected to that signal the lower the resistor the higher the current needed to sustain the logical level
PCB Routing Schematic Layout software and Simulation :: 01-29-2007 14:44 :: eltonjohn :: Replies: 5 :: Views: 1301
If you know the value of the capacitive load on the output, you can calculate the maximum allowable resistance of pullup resistor by solving the equation.
Vo = Vin(1-exp(-t/RC)) for R, where
Vin is the minimum steady-state "1" output.
t is the maximum allowable rise time fro the output to reach Vo.
Vo is the minimum acceptabl
Electronic Elementary Questions :: 07-03-2007 09:54 :: Kral :: Replies: 3 :: Views: 4900
it depends on the resistor or active network you use for pull up.... what r u planning on.... active network or passive network....
Analog Circuit Design :: 08-13-2007 07:51 :: A.Anand Srinivasan :: Replies: 5 :: Views: 754
I'm not sure whether this is an analog or digital question. I know that for an I2C line, you have to pull up SDA and SCL. What other lines do you have to pull up? Someone told me that you have to pull up lines that come from open drains. In general, what are guidelines for (...)
Analog Circuit Design :: 10-23-2007 12:41 :: jbs87 :: Replies: 3 :: Views: 506
I made a simple program on PIC, in which as long as I press the push button the LED would glow and as I remove my finger from push button it would stop glowing.I choose R0(Pin) for input and B0(Pin) for output.
Microcontrollers :: 01-12-2008 00:51 :: umery2k75 :: Replies: 1 :: Views: 3708
In PIC18F4550, only PORTB has internal weak pull-ups, the other ports don't.
Hope this helps.
Microcontrollers :: 10-28-2010 10:19 :: Tahmid :: Replies: 8 :: Views: 2172
There is no way to use that pull down resistors when the pins are used, these can only be enabled for unused pin.
You can use an external resistor for the pins (inputs i suppose), a 10k resistor would be fine.
---------- Post added at 10:12 ---------- Previous post was at 09:57 ----------
Embedded Systems and Real-Time OS :: 03-03-2011 03:12 :: alexan_e :: Replies: 1 :: Views: 1296
1) im using the circuit below and when im connecting pull-up or pull down resistor the system not working ! , i know that PORTB in PIC18F4550 has internal resistors but even when i connect resistors to PORTD system in not working as it should be.
"Not working" is in fact a vague information. I understand, (...)
Microcontrollers :: 05-16-2011 10:00 :: FvM :: Replies: 7 :: Views: 2285
I'm reverse engineering NMOS chips from the early eighties (just for fun and historical reasons, eh).
In a NOR gate with many inputs (part of a PLA) I found a pull-up circuit as shown below. What is the reason for T215? A friend guessed that it is working like a bootstrap circuit, to lift and drop the gate voltage of T216 whenever the source vol
Analog IC Design and Layout :: 10-31-2012 06:12 :: skoe :: Replies: 0 :: Views: 317
I wonder if @lter@ family has internal pull-up, just like CoolRunner?
Professional Hardware and Electronics Design :: 06-13-2002 05:15 :: ltg :: Replies: 1 :: Views: 642
:D some ICs require their output pins to be connected with a pull-up resistor. i wonder what this is for. another Q, what does open drains mean? 8O
pull up resistors are used for open collector or open drain outputs. Usually, a logic gate output have two switching elements (either bipolar or mos), one which produce "1" l
Electronic Elementary Questions :: 08-25-2004 05:20 :: pisoiu :: Replies: 8 :: Views: 2840
Nothing will happend.
PIC has his internal pull up resistors (they can be switched ON/OFF by software), so in case when pull ups are switched off everything is same as in 8051 case. If they are switched on and you connect additional extern pull you will just boost (...)
Microcontrollers :: 12-14-2004 03:04 :: mrcube_ns :: Replies: 5 :: Views: 1288
For me I think 10k pull up is enough, soemtimes I use 1k.
Microcontrollers :: 12-31-2004 02:12 :: glenjoy :: Replies: 11 :: Views: 14901
I found there are several values of pull-up resistor, for example 1k, 3.3k, 4.7k. Is the value of resistor proportional to the VCC? Or it related to other parameters, such as current?
Professional Hardware and Electronics Design :: 12-31-2004 22:43 :: davyzhu :: Replies: 2 :: Views: 1388
This discussion assumes 5 V Vcc.
TTL output levels must only drive 2.0 volts or greater for a logic high level. In addition, many TTL drivers source less current than they sink, meaning that while they may be rated for 4 mA drive for logic high, they might be rated at 12 mA for a logic low. As the output voltage increases, the drive current dr
Microcontrollers :: 01-19-2005 17:42 :: knavekid :: Replies: 2 :: Views: 4279
pull up resistor shifts output level of circuit toward Vcc ( supply voltage).
If NPN transistor's emiter is connected to GND, base to previous stage ( drive circuit), and collector is open, you shoud connect pull resistor between Vcc and collector. In that way when transistor is "open" ( current flows trough collector (...)
Electronic Elementary Questions :: 03-10-2005 08:39 :: Moss :: Replies: 10 :: Views: 9671
The pullups can be (and should be) set only for pins programmed as inputs! So the corresponding bit of the direction register must be 0. To 1 you should set the bit in the PORT register. For example to set the pullup on the PA0:
DDRA &= 0xFE; // Clear the bit 0
PORTA |= 0x01; // Set the bit 0
DDRA.0 = 0; (...)
Microcontrollers :: 05-31-2005 07:08 :: vdaniel :: Replies: 1 :: Views: 1873
This question has been asked a lot of time here.
See for example this old post try a seach
Replace * by t
Microcontrollers :: 07-29-2005 09:18 :: papyaki :: Replies: 4 :: Views: 721
Hi I wanted to created a top-level block that contains two 8-bit tristate buffers ,one is connected to the input of a register and the other is connected to the output ...I got this warning :
WARNING:Xst:2042 - Unit zreg: 8 internal tristates are replaced by logic (pull-up yes): into1<0>, into1<1>, into1<2>, into1<3>, into1<4>, into1<5>, into1<6
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-20-2005 18:47 :: cmos babe :: Replies: 3 :: Views: 3152
I don't think it is possible to disable the weak pullups on this micro. It is basically an 80C32, where the pullups are always on, to allow the I/O pins to function as both inputs and outputs, simply by clearing the port latch; there is no data direction register.
Is it really that important to have the (...)
Professional Hardware and Electronics Design :: 09-08-2005 12:52 :: VVV :: Replies: 4 :: Views: 1844
Is it always better to use a pull up resistor on the CS active low input of an IC?
Does it make a difference if the CS input is open drain/collector or not?
Microcontrollers :: 11-15-2005 12:09 :: alexz :: Replies: 2 :: Views: 516
To our Smart Card ic product, when set pull up resistance to 100KΩ, it will reset, can not work. what cause this iusse?
ASIC Design Methodologies and Tools (Digital) :: 12-27-2005 20:12 :: wucaifeng :: Replies: 7 :: Views: 816
I face some problems in designing a full CMOS SRAM cell:
1. The choose of W/L ratio
The W/L of the back-to-back inverters should be the same? I saw this in somewhere. I was confuse by that because in a latch, the forward inverter should be stronger than the feedback inverter...
The Wordline transistor should have smaller W/L com
ASIC Design Methodologies and Tools (Digital) :: 02-11-2006 22:04 :: weng :: Replies: 0 :: Views: 956