25 Threads found on edaboard.com: Pwm Vhdl
Does anyone have a vhdl implementation of a symmetrical pwm generation? or a link?
PC Programming and Interfacing :: 24.01.2003 13:25 :: Sonic :: Replies: 1 :: Views: 2176
I'm trying to implement (in vhdl) a simple 3-bit counter that is loaded asynchronously. The CPU writes to an 8-bit register, in which 3 of those bits are the ones that are loaded into the counter. These 3-bits determine the duty cycle for the pwm output that is gated on the TC of the counter.
Has anyone had any experience designing loadable c
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.06.2003 12:18 :: tjendon74 :: Replies: 0 :: Views: 2166
Hi! I don't have a background on vhdl/FPGA until last month when i started to self-study because there is a design contest in our school. Part of the contest is designing a pwm Encoder having 8 bits of input from an ADPCM Decoder and the pwm Encoder is fed with a PCM. The output of the pwm Encoder is also 8 bit. I (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.09.2005 12:10 :: PWM_encoder :: Replies: 0 :: Views: 1500
HI people. I have a code that count pulses of clock, and put the exit high or low (like a pwm, but user enters the number os pulses on high and the number of pulses on low). I have available a Altera 3064, and i need also divide clock per 8, before counting. After compilation and synthesis, the code are using (with Quartus 6.0) 68 macrocells, and
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.06.2006 07:53 :: btminzon :: Replies: 3 :: Views: 1081
From ur post what I guess is you need code for pwm to drive a DC motor.
If I am right you can get vhdl code for pwm from net. Checkout this!
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.10.2006 02:58 :: nand_gates :: Replies: 3 :: Views: 4680
It 's quite easy...
You built a free running counter. The bit size of the counter depends on the desired pwm command resolution. If you want a 8 bit command, then you have to build a 8 bit counter.
The counter 's clock is derived from your system 's clock.
Then you (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.04.2007 03:43 :: fguihot :: Replies: 1 :: Views: 1454
OK well i wanted to test something like the following using SPICE simulation.
I have some vhdl which is just a pwm generator. I would like to add this vhdl in a A/D circuit in PSPICE and test it with some different value resistors and capacitors for a low-pass filter for the output... Basically to create a 1-bit DAC. But i have no idea (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.08.2007 23:15 :: Lord Banshee :: Replies: 4 :: Views: 6545
I'm currently in the process of developing a control scheme for a custom power device using FPGA. The control scheme processes the error voltage through a PI controller whose output (PI output) is used to phase modulate the sinusoidal waveform (50 Hz). The phase modulated waveform is then compared against a triangular carrier wave to generate
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.04.2008 03:26 :: rjai_pradha :: Replies: 0 :: Views: 1033
how to implement vhdl code for pwm with frequency 1kHz and duty cycle of 20%
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.08.2008 10:55 :: gvsm :: Replies: 1 :: Views: 11668
*only exact solution will get the reward.
URGENT SOLUTION NEEDED.
Problem: i want to count number of pulses of a DC motor operated at +5v. the clock used in controller was 50MHz. The Design consist of PID (16-bit output,8-bit input and feedback) +pwm.the #of pulses[
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.06.2009 02:05 :: koolslash :: Replies: 1 :: Views: 1169
I just wondering wht's the way to sample the pwm signal in vhdl so that to design an integrator with pwm signal as input.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.02.2010 10:43 :: KSR24 :: Replies: 2 :: Views: 1791
am doing project in three phase pwm rectifier for harmonic reduction.can any one send me the vhdl code for three phase pwm generation using sinusoidal pwm technique.pwm rectifier consists of 6 MOSFET switchs.the conduction of each switch is 120 degree and interval between 2 switchs is 60 degrees.the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.04.2010 02:32 :: divya06 :: Replies: 1 :: Views: 1751
If you meen "seeing" in hardware, you'll need a digital-to-analog conversion means. For low data rates, a pwm modulated pin with a low-pass can do. But involves additional logic. Some DevKits are equipped with DAC hardware, I think.
Digital Signal Processing :: 28.07.2011 03:15 :: FvM :: Replies: 19 :: Views: 1863
lvhdl code for generation of pam,ppm & pwm waveforms using xilinx software....
plz do reply......its urgent
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.09.2011 02:01 :: winnysam :: Replies: 5 :: Views: 1133
It could be that pwm_out becomes bigger than 255 and thus fall out of the range of 8 bit.
But like TrickyDicky wrote, the line indication is line 1347. You should have a look at that line.
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.12.2011 12:55 :: lucbra :: Replies: 15 :: Views: 466
to make things easier, you could start by eliminating the std_logic_vectors for the counters and replacing them with integer, natural or unsigned.
Write a counter, let it run from 0 to max_countervalue, set the dout signal, when the counter reaches the desired value, reset your dout signal (port).
If you translate this piece of text to vhdl/v
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.03.2012 09:16 :: lucbra :: Replies: 8 :: Views: 919
I am trying to connect a servo motor to my Basys2 using the con3 Pmod sold by Digilent. I have been attempting to use two different methods for this and am unable to cause my servo to move with the pwm Signal they generate. I believe this has something to do with the constraints file I write. I have tried assigning the the servo's connection pin o
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.03.2013 01:32 :: Wolfgang94 :: Replies: 9 :: Views: 415
i guess that is possible once u use square waves instead of sines. u can obtains pwm... I have done that once..
u need timer circuits to do that.... in case your objectives can be met in that case it was so.
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.01.2006 13:21 :: eda_freak :: Replies: 6 :: Views: 1973
Using a plain MC34063 controller would be much simpler solution, but if you must use FPGA, then I'd recommend the PicoBlaze controller from Xilinx.
It is free, compact and easy to use, has got assembler and even a C-compiler for free.
You can fit many of them in a single FPGA ( depending on the size of your FPGA of course ).
This IP is also v
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.10.2006 06:17 :: yego :: Replies: 5 :: Views: 1007
this isn't strictly a DSP question but DSP is definitely an option. What I have is a 3 semester project for uni. I chose to implement an ABS and traction control system in a 1/5th scale remote control car ( for pictures).
My original idea was to use an FPGA, Spartan 3E. I have only ever written vhdl and never
Digital Signal Processing :: 16.02.2007 09:37 :: mookins :: Replies: 0 :: Views: 561
pls help, i m doing my final year project.. which is a (8bit) vhdl model of three phase pwm. i have written vhdl code for the pwm. in the embedded design, i need to write a c-program to generate 3 phase sine waves to the port 1 of the TSK51a microprocessor that will communicate with the vhdl model. (also (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.02.2011 19:31 :: ls3ar :: Replies: 0 :: Views: 407
yes..i know vhdl. some of it.
state machine that I had build for a car
a red signal in modelsim where it supposed to be a pwm enable and a pwm signal
what you mean by car? red signal in modelsim? pwm?
i dont get it..
if is not related to the thread title, then can you post another thread for it?
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.04.2011 02:09 :: zel :: Replies: 5 :: Views: 509
u just need to find/write the pwm modulator
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.05.2011 21:51 :: yadog :: Replies: 3 :: Views: 761
All of three seconds of random googling :
Synthesisable Sine Wave Generator
That approach uses a lookup table.
---------- Post added at 03:44 ---------- Previous post was at
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.09.2011 21:44 :: mrflibble :: Replies: 3 :: Views: 1551
browse site for other useful info. but attached is quicker (4MB)
General vhdl and specific to H bridge sin pwm
You need to define your own State Table for Quadrature H bridge drive and pwm on one leg or two.
Microcontrollers :: 02.05.2012 17:13 :: SunnySkyguy :: Replies: 16 :: Views: 1225