1000 Threads found on edaboard.com: Pwm Vhdl
Does anyone have a vhdl implementation of a symmetrical pwm generation? or a link?
PC Programming and Interfacing :: 01-24-2003 13:25 :: Sonic :: Replies: 1 :: Views: 2305
Hi! I don't have a background on vhdl/FPGA until last month when i started to self-study because there is a design contest in our school. Part of the contest is designing a pwm Encoder having 8 bits of input from an ADPCM Decoder and the pwm Encoder is fed with a PCM. The output of the pwm Encoder is also 8 bit. I (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-23-2005 12:10 :: PWM_encoder :: Replies: 0 :: Views: 1706
There are some points, that have to be considered before writing pwm code (respectively trying to copy some existing code):
- the modulation scheme can be natural, regular symmetrical or regular asymmetrical sampling
- pwm modulation input can be either relative (+/- 1 range) or absolute (requested output voltage). In the latter case, a bus v
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-10-2008 11:30 :: FvM :: Replies: 1 :: Views: 12235
I just wondering wht's the way to sample the pwm signal in vhdl so that to design an integrator with pwm signal as input.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-03-2010 10:43 :: KSR24 :: Replies: 2 :: Views: 1960
am doing project in three phase pwm rectifier for harmonic reduction.can any one send me the vhdl code for three phase pwm generation using sinusoidal pwm technique.pwm rectifier consists of 6 MOSFET switchs.the conduction of each switch is 120 degree and interval between 2 switchs is 60 degrees.the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-20-2010 02:32 :: divya06 :: Replies: 1 :: Views: 1915
lvhdl code for generation of pam,ppm & pwm waveforms using xilinx software....
plz do reply......its urgent
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-25-2011 02:01 :: winnysam :: Replies: 5 :: Views: 1417
..hi guys..others project is time code generator on fpga and generated time code ....now have to do pwm....here is the code i wrote but not getting code i used /100 counter as actual serial data and /10 to compare it and change duty cycle.....i.e each serial data pluse time=10 times /10 counter output pulse width..given code has some un
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-23-2012 04:34 :: Zampradeep :: Replies: 8 :: Views: 1160
I'm trying to control a servomotor HS-645MG with the Altera FPGA DE0 using vhdl. According to my limited knowledge (and according to other programmers) these are the code for frequency dividing and pwm:
entity clk64kHz is
clk : in STD_LOGI
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-11-2014 02:48 :: Gilgamesh90 :: Replies: 2 :: Views: 243
I'm trying to implement (in vhdl) a simple 3-bit counter that is loaded asynchronously. The CPU writes to an 8-bit register, in which 3 of those bits are the ones that are loaded into the counter. These 3-bits determine the duty cycle for the pwm output that is gated on the TC of the counter.
Has anyone had any experience designing loadable c
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-26-2003 12:18 :: tjendon74 :: Replies: 0 :: Views: 2365
HI people. I have a code that count pulses of clock, and put the exit high or low (like a pwm, but user enters the number os pulses on high and the number of pulses on low). I have available a Altera 3064, and i need also divide clock per 8, before counting. After compilation and synthesis, the code are using (with Quartus 6.0) 68 macrocells, and
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-22-2006 07:53 :: btminzon :: Replies: 3 :: Views: 1309
From ur post what I guess is you need code for pwm to drive a DC motor.
If I am right you can get vhdl code for pwm from net. Checkout this!
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-05-2006 02:58 :: nand_gates :: Replies: 3 :: Views: 5021
It 's quite easy...
You built a free running counter. The bit size of the counter depends on the desired pwm command resolution. If you want a 8 bit command, then you have to build a 8 bit counter.
The counter 's clock is derived from your system 's clock.
Then you (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-04-2007 03:43 :: fguihot :: Replies: 1 :: Views: 1592
I have some vhdl which is just a pwm generator. I would like to add this vhdl in a A/D circuit in PSPICE and test it with some different value resistors and capacitors for a low-pass filter for the output... Basically to create a 1-bit DAC. But i have no idea how to do this at all.
Okay sorry to burst your bubble but Pspice does
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-06-2007 22:56 :: jhallows :: Replies: 4 :: Views: 7025
I'm currently in the process of developing a control scheme for a custom power device using FPGA. The control scheme processes the error voltage through a PI controller whose output (PI output) is used to phase modulate the sinusoidal waveform (50 Hz). The phase modulated waveform is then compared against a triangular carrier wave to generate
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-08-2008 03:26 :: rjai_pradha :: Replies: 0 :: Views: 1195
*only exact solution will get the reward.
URGENT SOLUTION NEEDED.
Problem: i want to count number of pulses of a DC motor operated at +5v. the clock used in controller was 50MHz. The Design consist of PID (16-bit output,8-bit input and feedback) +pwm.the #of pulses[
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-14-2009 02:05 :: koolslash :: Replies: 1 :: Views: 1257
If you meen "seeing" in hardware, you'll need a digital-to-analog conversion means. For low data rates, a pwm modulated pin with a low-pass can do. But involves additional logic. Some DevKits are equipped with DAC hardware, I think.
Digital Signal Processing :: 07-28-2011 03:15 :: FvM :: Replies: 19 :: Views: 2246
It could be that pwm_out becomes bigger than 255 and thus fall out of the range of 8 bit.
But like TrickyDicky wrote, the line indication is line 1347. You should have a look at that line.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-29-2011 12:55 :: lucbra :: Replies: 15 :: Views: 669
I recently switched from vhdl to Verilog to more utilize my background in programming in C++. I was given a project in which i need to implement pwm on a FPGA. I've been trying my best to do my research and look at examples of pwm that are floating around the internet. I written some code that I believe does what I would like, (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-30-2013 12:26 :: loki3118 :: Replies: 3 :: Views: 393
1. Complete vhdl Project
2. As of now im using Single Phase. only one H-Bridge with 4 switches.
3. Generating the pulses from comparing values of sine samples(lookup table) to triangular samples(up/down counter)
4. Im able to generate sine pwm and want to update my design for closed loop design.
5. What is a matrix converter?
6. Are there any
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-17-2014 03:25 :: codetrickster :: Replies: 3 :: Views: 350
i need a vhdl code for pwm generation for boost converter..i want to generate a pwm by comparing a output of pi controller with triangular wave(counter)
plz help me in this..m complete new to vhdl/.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-28-2014 01:34 :: vini p :: Replies: 0 :: Views: 216
I am trying to control two Futaba S3003 servo motor with a basys2 board. I understand that the servo works of pulse width modulation and have done the required calculations to create the correct pulse widths.
I have written the implementation constraints to output on the the JA and JB terminals. I have tested the system with an oscilloscope/mul
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-23-2014 17:26 :: NOTSam :: Replies: 1 :: Views: 394
i want to do in OrCAD PSPICE and want to generate a 30 MHz sawtooth for that without use of VPULSE.
like integrating a square wave.
Why don't you do exactly this: integrating a square wave (using behavioral SPICE models). I don't see where vhdl comes into play.
You can model complete power electronic control circuits, e.g. pwm,
Power Electronics :: 08-14-2014 06:44 :: FvM :: Replies: 19 :: Views: 423
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments....
For FPGA design, what I have used synthesis tools(only to synthesis vhdl code): Synplicity Synplify > Synopsys FPGA Compiler II > Mentor Leonardo Exemplar
It is only my personal opinion...
Professional Hardware and Electronics Design :: 07-13-2001 17:19 :: :: Replies: 7 :: Views: 3656
If you want an audio interactive tutor to learn Verilog or vhdl.. I did upload it for someone who did ask me... ES PERAN Verilog & vhdl.
If you are interested let me know
Professional Hardware and Electronics Design :: 08-06-2001 13:01 :: henrik2000 :: Replies: 5 :: Views: 9985
Hello everybody !!
I serach for a "pwm-Circuit" for controlling a "Buck/Boost-Converter" !!
Does anybody have a circuit !!
Please don't reply unless you have useful information to add on this post.
Any other replies are always welcome via PM.
Professional Hardware and Electronics Design :: 08-27-2001 05:35 :: Vauxdvihl :: Replies: 6 :: Views: 1866
On 2001-08-31 17:26, ahgu wrote:
I did some research:
pwm usually have 10bit resolution(1024) levels. 20Khz x 1k=20Mhz. if you goto 12bit resolution, you need 80Mhz clock.
But for DAC, 16bits is readily available. But it is a external component. Any uController that has 12bits DAC?
I need to do location position, My encoder has 512
Professional Hardware and Electronics Design :: 09-01-2001 17:49 :: Speedy :: Replies: 5 :: Views: 2503
pwm != position control, unless you are using some control logic between the pwm signal and the motor.
positioning accuracy will depend on your encoders which provide position/velocity feedback.
Professional Hardware and Electronics Design :: 08-31-2001 12:35 :: pissant :: Replies: 3 :: Views: 1671
I'm looking for a simple pwm low voltage (6/12V 50W) lamp controller, using PIC 16F84/F628 or 12C509 and a power MOSFET.
It should provide "soft start" and regulate the lamp voltage from a battery V greater or equal the nominal Vlamp.
Does anyone has already it or I have start this design from scratch ?
Professional Hardware and Electronics Design :: 09-15-2001 02:22 :: picman2 :: Replies: 9 :: Views: 10558
I am a student from Harbin China. Now I am building a behavioral model of a Direct Sequence Spread Spectrum Communication system using vhdl-AMS. So i want to know where can I find some example similar to that or something that may give help to me.
Can you give me some advices. Thank you!
[ This Message was edited by: flybear on
Professional Hardware and Electronics Design :: 10-29-2001 04:17 :: flybear :: Replies: 0 :: Views: 1532
vhdl QUICK Reference Guide
Ready for onboard prints
Uploaded file: vhdlref.pdf
Microcontrollers :: 02-21-2002 06:04 :: jimjim2k :: Replies: 2 :: Views: 3143
where to get test bench with vhdl for SDH chip?
Microcontrollers :: 02-22-2002 00:49 :: coolsniper :: Replies: 10 :: Views: 2325
The vhdl Golden Reference Guide
A 136 pps ebook.
Uploaded file: vhdl-golden-reference.pdf
Please don't reply unless you have useful information to add on this post. Thanks !
(No Me-too's, no Thanks-you's, etc ... use
Microcontrollers :: 02-24-2002 06:48 :: jimjim2k :: Replies: 3 :: Views: 7776
Here is the vhdl code for 8051 MC.
Uploaded file: 8051 in vhdl.zip
Microcontrollers :: 02-24-2002 06:59 :: jimjim2k :: Replies: 8 :: Views: 7812
LEON is a synthesisable vhdl model of a 32-bit SPARC* compatible processor, developed by the European Space Agency (ESA) for future space missions. To promote the SPARC architecture and enable development of system-on-a-chip (SOC) devices using SPARC cores, ESA is making the full source code freely available under the GNU LGPL license.
Microcontrollers :: 02-25-2002 09:00 :: jimjim2k :: Replies: 5 :: Views: 3632
vhdl Language reference manual. latest edition.
Please don't reply unless you have useful information to add on this post.
Any other replies are always welcome via PM.
[ This Message was edited by: KARLZ on
Microcontrollers :: 03-01-2002 15:09 :: KARLZ :: Replies: 3 :: Views: 2377
Online vhdl Testbench Generator
1. TestBench Tool
3. -> t
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-02-2002 08:40 :: jimjim2k :: Replies: 6 :: Views: 6673
These materials are made available for ECE 4170: Introduction to HDLs with Applications to Digital Design taught during the Spring 2000 Semester at Georgia Tech.
This text focuses on presenting the basic features of the vhdl language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by fami
Microcontrollers :: 03-02-2002 09:09 :: jimjim2k :: Replies: 9 :: Views: 3329
Anyone interested in a single entity vhdl testbench generator, try this. Code is free to do with as you wish. If you add significant enhancements, please send me a new copy too. You will need to have Tcl/Tk installed on you system to use this.
Uploaded file: tb_gen.tcl
Microcontrollers :: 03-04-2002 20:12 :: mexico_mike :: Replies: 2 :: Views: 3771
Would you please upload IEEE Standards
for verilog and vhdl to this place.
1. If you have uploaded files in some other boards, please leave a URL pointer only.
2. Please rename the files before uploading by the a definitive words to distingush files from each other. It seems that the forum replaces every newer file with
Microcontrollers :: 03-05-2002 02:40 :: jimjim2k :: Replies: 0 :: Views: 1628
Which most prefer or popular? vhdl or Verilog?
ASIC Design Methodologies and Tools (Digital) :: 03-09-2002 12:13 :: cadb0y :: Replies: 113 :: Views: 15477
Anyone has a DSP core in vhdl or Verilog? Prefer TI but anyone will do.
Microcontrollers :: 03-14-2002 11:16 :: ASIC :: Replies: 14 :: Views: 5367
Would anyone share the RS232 vhdl code ?
If you have RS232 test program , please share.
Thanks a lot.
Other Design :: 03-30-2002 04:47 :: cssheu :: Replies: 11 :: Views: 13147
Please suggest good books in this thread for vhdl/Verilog ASIC design
ASIC Design Methodologies and Tools (Digital) :: 04-04-2002 05:12 :: antipattern :: Replies: 7 :: Views: 1984
anyone can send me the reference of phase shift pwm application
Professional Hardware and Electronics Design :: 04-26-2002 07:05 :: alphi :: Replies: 3 :: Views: 1536
Tutorials for vhdl and Verilog.
HDL Synthesis for FPGAs: Design Guide (PDF 2MB)
SystemC -- Technical Papers
Cypress: Programmable Logic: vhdl Page
Cypress: Design Resources : Technical Articles
Logic Synthesis with vhdl System Synthesis
vhdl SYNTHESIS TUTORIAL
vhdl Coding Style manual (...)
Microcontrollers :: 05-09-2002 06:32 :: jimjim2k :: Replies: 5 :: Views: 3348
signal rd,dr : std_logic;
ad_bus,ram_bus : inout;
process(rd) ---- right.
if (rd='0' and dr='1') then
process(rd) ---- error.
if (rd='0') then
if dr='1' then
ASIC Design Methodologies and Tools (Digital) :: 05-19-2002 10:17 :: 75 sinfocia :: Replies: 9 :: Views: 1182
This object of this course is to introduce the student to more of the vhdl modeling language than what has been covered in previous courses.
1. -> t
Microcontrollers :: 06-09-2002 08:29 :: jimjim2k :: Replies: 0 :: Views: 1457
1. -> t
Microcontrollers :: 07-11-2002 03:09 :: jimjim2k :: Replies: 0 :: Views: 1465
1. -> t
Microcontrollers :: 07-11-2002 04:11 :: jimjim2k :: Replies: 0 :: Views: 1422
is there any software which convert matlab code to vhdl?
how can i get it?
PC Programming and Interfacing :: 07-13-2002 04:04 :: baa110 :: Replies: 32 :: Views: 15181