25 Threads found on edaboard.com: Pwm Vhdl
Does anyone have a vhdl implementation of a symmetrical pwm generation? or a link?
PC Programming and Interfacing :: 24.01.2003 13:25 :: Sonic :: Replies: 1 :: Views: 2264
I'm trying to implement (in vhdl) a simple 3-bit counter that is loaded asynchronously. The CPU writes to an 8-bit register, in which 3 of those bits are the ones that are loaded into the counter. These 3-bits determine the duty cycle for the pwm output that is gated on the TC of the counter.
Has anyone had any experience designing loadable c
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.06.2003 12:18 :: tjendon74 :: Replies: 0 :: Views: 2302
Hi! I don't have a background on vhdl/FPGA until last month when i started to self-study because there is a design contest in our school. Part of the contest is designing a pwm Encoder having 8 bits of input from an ADPCM Decoder and the pwm Encoder is fed with a PCM. The output of the pwm Encoder is also 8 bit. I (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.09.2005 12:10 :: PWM_encoder :: Replies: 0 :: Views: 1665
HI people. I have a code that count pulses of clock, and put the exit high or low (like a pwm, but user enters the number os pulses on high and the number of pulses on low). I have available a Altera 3064, and i need also divide clock per 8, before counting. After compilation and synthesis, the code are using (with Quartus 6.0) 68 macrocells, and
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.06.2006 07:53 :: btminzon :: Replies: 3 :: Views: 1225
From ur post what I guess is you need code for pwm to drive a DC motor.
If I am right you can get vhdl code for pwm from net. Checkout this!
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.10.2006 02:58 :: nand_gates :: Replies: 3 :: Views: 4892
It 's quite easy...
You built a free running counter. The bit size of the counter depends on the desired pwm command resolution. If you want a 8 bit command, then you have to build a 8 bit counter.
The counter 's clock is derived from your system 's clock.
Then you (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.04.2007 03:43 :: fguihot :: Replies: 1 :: Views: 1541
I have some vhdl which is just a pwm generator. I would like to add this vhdl in a A/D circuit in PSPICE and test it with some different value resistors and capacitors for a low-pass filter for the output... Basically to create a 1-bit DAC. But i have no idea how to do this at all.
Okay sorry to burst your bubble but Pspice does
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.08.2007 22:56 :: jhallows :: Replies: 4 :: Views: 6860
I'm currently in the process of developing a control scheme for a custom power device using FPGA. The control scheme processes the error voltage through a PI controller whose output (PI output) is used to phase modulate the sinusoidal waveform (50 Hz). The phase modulated waveform is then compared against a triangular carrier wave to generate
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.04.2008 03:26 :: rjai_pradha :: Replies: 0 :: Views: 1144
how to implement vhdl code for pwm with frequency 1kHz and duty cycle of 20%
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.08.2008 10:55 :: gvsm :: Replies: 1 :: Views: 12032
*only exact solution will get the reward.
URGENT SOLUTION NEEDED.
Problem: i want to count number of pulses of a DC motor operated at +5v. the clock used in controller was 50MHz. The Design consist of PID (16-bit output,8-bit input and feedback) +pwm.the #of pulses[
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.06.2009 02:05 :: koolslash :: Replies: 1 :: Views: 1224
I just wondering wht's the way to sample the pwm signal in vhdl so that to design an integrator with pwm signal as input.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.02.2010 10:43 :: KSR24 :: Replies: 2 :: Views: 1900
am doing project in three phase pwm rectifier for harmonic reduction.can any one send me the vhdl code for three phase pwm generation using sinusoidal pwm technique.pwm rectifier consists of 6 MOSFET switchs.the conduction of each switch is 120 degree and interval between 2 switchs is 60 degrees.the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.04.2010 02:32 :: divya06 :: Replies: 1 :: Views: 1861
If you meen "seeing" in hardware, you'll need a digital-to-analog conversion means. For low data rates, a pwm modulated pin with a low-pass can do. But involves additional logic. Some DevKits are equipped with DAC hardware, I think.
Digital Signal Processing :: 28.07.2011 03:15 :: FvM :: Replies: 19 :: Views: 2134
lvhdl code for generation of pam,ppm & pwm waveforms using xilinx software....
plz do reply......its urgent
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.09.2011 02:01 :: winnysam :: Replies: 5 :: Views: 1319
I write a simple code for changing the velocity of dc motor.
the code check the velocity and change the pwm value.
but the compilation of the program is not successful.I get an error massege and don't know the meaning.
please your answer.
here is the code and the wrong massage :
the code :
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.12.2011 08:55 :: shaolomc32 :: Replies: 15 :: Views: 606
to make things easier, you could start by eliminating the std_logic_vectors for the counters and replacing them with integer, natural or unsigned.
Write a counter, let it run from 0 to max_countervalue, set the dout signal, when the counter reaches the desired value, reset your dout signal (port).
If you translate this piece of text to vhdl/v
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.03.2012 09:16 :: lucbra :: Replies: 8 :: Views: 1096
Have you connected an O-scope to the pin you are intending to use for your pwm signal. I would think your issue is more than likely your signal and not just identifying a pin in the constraint file.
My suggestion would be to set up a counter from (0 to Period) where period is the value (which depends on you clock rate) that equates to 20 ms. Next
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.03.2013 21:25 :: Mwnuk :: Replies: 9 :: Views: 554
i guess that is possible once u use square waves instead of sines. u can obtains pwm... I have done that once..
u need timer circuits to do that.... in case your objectives can be met in that case it was so.
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.01.2006 13:21 :: eda_freak :: Replies: 6 :: Views: 2096
Using a plain MC34063 controller would be much simpler solution, but if you must use FPGA, then I'd recommend the PicoBlaze controller from Xilinx.
It is free, compact and easy to use, has got assembler and even a C-compiler for free.
You can fit many of them in a single FPGA ( depending on the size of your FPGA of course ).
This IP is also v
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.10.2006 06:17 :: yego :: Replies: 5 :: Views: 1068
this isn't strictly a DSP question but DSP is definitely an option. What I have is a 3 semester project for uni. I chose to implement an ABS and traction control system in a 1/5th scale remote control car ( for pictures).
My original idea was to use an FPGA, Spartan 3E. I have only ever written vhdl and never
Digital Signal Processing :: 16.02.2007 09:37 :: mookins :: Replies: 0 :: Views: 614
pls help, i m doing my final year project.. which is a (8bit) vhdl model of three phase pwm. i have written vhdl code for the pwm. in the embedded design, i need to write a c-program to generate 3 phase sine waves to the port 1 of the TSK51a microprocessor that will communicate with the vhdl model. (also (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.02.2011 19:31 :: ls3ar :: Replies: 0 :: Views: 466
It wasn't clear to my a month ago too (; but it's all right I solved it.
Do you know vhdl ... I am having a problem with a state machine that I had build for a car
a red signal in modelsim where it supposed to be a pwm enable and a pwm signal
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.04.2011 01:17 :: showsellar :: Replies: 5 :: Views: 560
u just need to find/write the pwm modulator
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.05.2011 21:51 :: yadog :: Replies: 3 :: Views: 819
All of three seconds of random googling :
Synthesisable Sine Wave Generator
That approach uses a lookup table.
---------- Post added at 03:44 ---------- Previous post was at
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.09.2011 21:44 :: mrflibble :: Replies: 3 :: Views: 1748
browse site for other useful info. but attached is quicker (4MB)
General vhdl and specific to H bridge sin pwm
You need to define your own State Table for Quadrature H bridge drive and pwm on one leg or two.
Microcontrollers :: 02.05.2012 17:13 :: SunnySkyguy :: Replies: 16 :: Views: 1507