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18 Threads found on Questa Sim
hi , i know that modelsim is used for simulating vhdl codes , but i dont know waht is questa sim and what does it do and how it works ? can any body help me ? thanks in advanced omid sharifi
Hi all ! I'm new to questa sim 10.1b but i'm use to Active-HDL and I want to know two thing First is there a way to define a macro inside a file I know that with Aldec->Active-HDL we can use the function : +define+ but i'm not able to find the equivalent with questa Second is there a way to set many variable into a
I know VCS has two states mode, does questasim have similar feature? The x in gate sim is very big headache. Is there a way to resolve x in questa sim? I am not using SDF back annotated sim. Thanks.
Hi After comillation ,simulation when i have given add wave option i am getting error like "objects not found in tb" in questa sim 6.2 j . tb (which is test bench module name).please give the solution
Hi, Is there any evaluation version software that can support systemverilog? I have heard that questasim is one such tool which supports systemverilog. Is it available freely? Plz let me know about this. Thanks
i have written a simple "and" in vhdl , the functional simulation in modelsim is okay , but when i synthesize it in ise with xst and i make the post synthesis simulation model , when i want to simulate it in modelsim or questa sim , it says that some (...)
To my knowledge questasim is released for the Verification purpose only by Mentor Graphics in support from Cadence. But Modelsim is from Metor Graphics only
Hi, I am using questa sim. While checking assertion, It is showing pass in the waveform, but its showing fail in log file. Assertion logic is right and signals is also behaving right.
Good idea is always to start with simulations. Once you are sure that there are no compilation errors, and your design is performing as expected, then move on to synthesis. Industry follows the similar flow : Design --> simulation --> Synthesis --> Backend flow Modelsim is from Mentor. Latest Modelsim (...)
i made one transaction class... class jk_trans; // randomization function write // display function i write endclass i made driver Generator Receiver scoreboard envirnment package.... all class are interact with one another i made driver class first.. class jk_driver; jk_trans data2duv; mailbox#(jk_trans) drv2sb; mail
There are many tools and each company uses different tool set. But, if you are interested in FPGA design, it will be the best to start from vendor provided design package because it contains all required tools to design FPGA. For example, Xilinx ISE, Altera Quartus-II and Actel Libero contain synthesizer, PAR, simulation tools in their packages. T
What is Multi-thread Ranking (VM) in latest questa sim 10.2 (beta).
module blocking(a,b,c); output reg a,b; input c; initial begin $monitor (",monitor=",a,$time); a<= #5 1'b0; a<= #10 1'b1; $strobe ("strobe=",a,$time); end endmodule The output I'm getting is run # ,monitor=x 0 # strobe=x 0 # ,monitor=0
Are there any free tools that support SystemVerilog? I'm looking into CAD tools and design methods at work (luckily starting with pretty much a blank slate), and at least for verification SystemVerilog seems to do just about everything I'm looking for (constrained random, assertions, etc). I could get an eval copy of questa or Aldec, but since
I have actually done functional coverage for verilog desing using system verilog. Ncverilog supports system verilog. The same thing I want to do for my vhdl design. I have gone through ncvhdl docs and found that system verilog constructs are not supported. Do I have to use mixed languages simulation for this purpose? I just want
i'm also looking for a simulator for system verilog. i'm a student and can't afford to buy a full version of Models sim with questa in it. i would really appreciate if anyone could point me in the right direction. for that matter does anybody know if there are free system verilog simulators out there? i need it so i could (...)
Hi My code has the following ifdef `ifdef simFILE `include `simFILE `endif While compiling I give vlog +define+simFILE="file1.sim" -f file_list.f When I give this way file1.sim is actually not included. Whereas it gets included only when I explicitly define as: `define simFILE (...)
Check the questa User Manual for suggestion for dealing with zero delay loops. You may have to set breakpoints and step through some of your code to find the loop.