12 Threads found on edaboard.com: Questa Sim
Is there way in system Verilog to compare line by line two files(its not know whether file will have strings or digit so no %s, %d )
Can I call $system in SV to do diff in questa sim or Is there any best way to do it like tcl command etc ?
ASIC Design Methodologies and Tools (Digital) :: 10-06-2014 23:52 :: GSB :: Replies: 3 :: Views: 315
Please revert back if the PA experts who can comment on the Power Aware GLS with the questa sim.
There are some difference like the way questa taking the Hard Macros as different optimisation and the visibilty to the design is removed while elaborating. If anything critical, known are shared will be helpful.
ASIC Design Methodologies and Tools (Digital) :: 03-26-2014 13:30 :: paulki :: Replies: 0 :: Views: 238
What is Multi-thread Ranking (VM) in latest questa sim 10.2 (beta).
ASIC Design Methodologies and Tools (Digital) :: 12-31-2012 05:46 :: jaybshah :: Replies: 0 :: Views: 299
Hi all !
I'm new to questa sim 10.1b but i'm use to Active-HDL and I want to know two thing
First is there a way to define a macro inside a file
I know that with Aldec->Active-HDL we can use the function : +define+ but i'm not able to find the equivalent with questa
Second is there a way to set many variable into a
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-25-2012 16:43 :: FboDigit :: Replies: 1 :: Views: 599
Good idea is always to start with simulations. Once you are sure that there are no compilation errors, and your design is performing as expected, then move on to synthesis.
Industry follows the similar flow : Design --> simulation --> Synthesis --> Backend flow
Modelsim is from Mentor. Latest Modelsim (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-24-2011 01:36 :: dtn_me :: Replies: 5 :: Views: 605
I am using questa sim.
While checking assertion, It is showing pass in the waveform, but its showing fail in log file.
Assertion logic is right and signals is also behaving right.
please send me code
ASIC Design Methodologies and Tools (Digital) :: 05-05-2011 02:14 :: akee_sa :: Replies: 3 :: Views: 474
Can I know what is the differnce between questa sim & modelsim?
Thanks in advance,
ASIC Design Methodologies and Tools (Digital) :: 12-02-2010 07:02 :: ramesh441 :: Replies: 6 :: Views: 9049
i'm also looking for a simulator for system verilog. i'm a student and can't afford to buy a full version of Models sim with questa in it. i would really appreciate if anyone could point me in the right direction. for that matter does anybody know if there are free system verilog simulators out there? i need it so i could (...)
Software Links :: 07-03-2010 07:24 :: cvc :: Replies: 5 :: Views: 708
questasim is advance version to support the simulation of SystemVerilog. support to the assertions and coverage varies in both versions.
visit the Mentorgraphics website
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-29-2009 05:25 :: gck :: Replies: 3 :: Views: 7936
Is there any evaluation version software that can support systemverilog? I have heard that questasim is one such tool which supports systemverilog. Is it available freely? Plz let me know about this.
Software Requests :: 07-19-2008 04:33 :: pratibha m d :: Replies: 3 :: Views: 424
After comillation ,simulation when i have given add wave option i am getting error like "objects not found in tb" in questa sim 6.2 j . tb (which is test bench module name).please give the solution
ASIC Design Methodologies and Tools (Digital) :: 07-10-2008 09:42 :: praneethkpt :: Replies: 1 :: Views: 520
Are there any free tools that support SystemVerilog? I'm looking into CAD tools and design methods at work (luckily starting with pretty much a blank slate), and at least for verification SystemVerilog seems to do just about everything I'm looking for (constrained random, assertions, etc).
I could get an eval copy of questa or Aldec, but since
ASIC Design Methodologies and Tools (Digital) :: 09-28-2006 15:57 :: Mike_D :: Replies: 2 :: Views: 1264