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questasim is advance version to support the simulation of SystemVerilog. support to the assertions and coverage varies in both versions. visit the Mentorgraphics website
Hi, Please revert back if the PA experts who can comment on the Power Aware GLS with the questa sim. There are some difference like the way questa taking the Hard Macros as different optimisation and the visibilty to the design is removed while elaborating. If anything critical, known are shared will be helpful. -paulki
Hi, Is there way in system Verilog to compare line by line two files(its not know whether file will have strings or digit so no %s, %d ) Can I call $system in SV to do diff in questa sim or Is there any best way to do it like tcl command etc ? Thanks, GSB
Hi all ! I'm new to questa sim 10.1b but i'm use to Active-HDL and I want to know two thing First is there a way to define a macro inside a file I know that with Aldec->Active-HDL we can use the function : +define+ but i'm not able to find the equivalent with questa Second is there a way to set many variable into a
I know VCS has two states mode, does questasim have similar feature? The x in gate sim is very big headache. Is there a way to resolve x in questa sim? I am not using SDF back annotated sim. Thanks.
Hi After comillation ,simulation when i have given add wave option i am getting error like "objects not found in tb" in questa sim 6.2 j . tb (which is test bench module name).please give the solution
Hi, Is there any evaluation version software that can support systemverilog? I have heard that questasim is one such tool which supports systemverilog. Is it available freely? Plz let me know about this. Thanks
i have written a simple "and" in vhdl , the functional simulation in modelsim is okay , but when i synthesize it in ise with xst and i make the post synthesis simulation model , when i want to simulate it in modelsim or questa sim , it says that some (...)
Can I know what is the differnce between questa sim & modelsim? Thanks in advance, RamesH
Hi, I am using questa sim. While checking assertion, It is showing pass in the waveform, but its showing fail in log file. Assertion logic is right and signals is also behaving right. please send me code
Good idea is always to start with simulations. Once you are sure that there are no compilation errors, and your design is performing as expected, then move on to synthesis. Industry follows the similar flow : Design --> simulation --> Synthesis --> Backend flow Modelsim is from Mentor. Latest Modelsim (...)
i made one transaction class... class jk_trans; // randomization function write // display function i write endclass i made driver Generator Receiver scoreboard envirnment package.... all class are interact with one another i made driver class first.. class jk_driver; jk_trans data2duv; mailbox#(jk_trans) drv2sb; mail
There are many tools and each company uses different tool set. But, if you are interested in FPGA design, it will be the best to start from vendor provided design package because it contains all required tools to design FPGA. For example, Xilinx ISE, Altera Quartus-II and Actel Libero contain synthesizer, PAR, simulation tools in their packages. T
What is Multi-thread Ranking (VM) in latest questa sim 10.2 (beta).
module blocking(a,b,c); output reg a,b; input c; initial begin $monitor (",monitor=",a,$time); a<= #5 1'b0; a<= #10 1'b1; $strobe ("strobe=",a,$time); end endmodule The output I'm getting is run # ,monitor=x 0 # strobe=x 0 # ,monitor=0
DR. sim, i have more nice SmartCard Programs. Loking for special one ? post me ! Uploaded file: Dr.
hi, i am just a jackaroo, and i need the help of all of you. where can i download NC-sim for linux and its license? when i ftp the, i don't know the detailed path . pls tell me ! Thanks a lot !
The output of synplify is .vm. How to perform simulation with .vm files? I just change .vm into .v,and perform sim in modelsim.Neither using testbench nor macro files(.do) can I give stimulus to input ports,such as clk, so the results are either 0 or x. BTW, modelsim didn't generate any error message during (...)
how to start Coverage Analysis tool in NC-sim? i can't find it .
Hi, How to do post-sim in modelsim with quartusII? step by step ! Who can tell me ? thanks fr help!
Hi, Can I use modelS/Im to simulate edif files . i am using Active H/D/l for edif simulation. After FPGA synthesis (output netlist is in edif format )how can simulate it with model/sim. If I cant. Is there any other way to verify synthesisd output with modelsim tnx
hi, Which is a better choice and why? I have used both I feel activehdl is more easy to use . Anyway I would like to know your comments tnx
hi, Who can help me? Used Modelsim to create a library for post-sim but occurred error,when I created a library to Compile apex20ke_components.vhd and apex20ke_atoms.vhd .error message: Error:Failed to access library'apex20ke'at"apex20ke" Error:apex20ke_Component.vhd:Library apex20ke not Found. but I Compiled apex20ke_ato
Is there any STANDARD about sim card of GSM mobile?And about its architecture? I want to design a sim card Reader that could connect to compter,read the card information about the telephone books,SMS's ,etc. Edit the information by computer then write it to the sim card. Any one could help me? Or give some information or documents (...)
Hi, Can someone tell me what's the difference between the two types of simulation?? as i know, after synthesis and post layout, i can get the timing report and back annotation sdf file, and the gate level netlist. Should i use the sdf file to simulate using Modelsim/Nc-sim in RTL level?? i can get more accurate (...)
What is Incisive ? It is included in Cadence LDV. What is defference form NC-sim ? Anybody knows that ?
IC digital sim e.g 7400
how to compile xilinx simulation lib use nc-sim?ISE5.2 lib tool doesn't support windowsNT version nc-sim.
Hi, I using NCsim v3.4 Linux How can I insert parameter in my verilog core ( example : CLKPERIOD = 40 instead of 20 ) in elaborate process just like in vhdl core I can insert generic with the aid as option : ncelab (...) -generic CLKPERIOD=>40 .... Regards Elektor
Hi Guys Instead of using a eerom in a dip socket to change data I was thinking of the possibility of using a sim card instead. Anyone got any experience of this. I need at least 64kBYTE memory. I have never seen any company who sells sim cards. Do you know of any company selling "blank" sim cards? Are they difficult to interface to? MrEd
I am using C@dance LDV5.0. When I tried to reinoke NC-sim simulator, it shows: A fatal error has ocurred during reinvoke, please check your simulator log file for the errors and start simVision again. Did anyone encounter this? how to solve this problem? thanks
How to create the cds.lib and hdl.var file before executing the NC-sim simulator?
Could someone tell me how to sim colippts active negative R ? I use colippts circuit , one MOS and 2 extrnal cap . I try put current source between Gate and Drain , but sim result real part is -3k , it's seems not correct. so if you have this paper or sim method ,please help me ... 3Q3Q 8O 8O 8O 8O
Hi All. I want to working with sim card based sequrity system. where i can write identify code, i am work with bascom. please help me . about blank sim card, reader & writer with AT89C##. thanks :2gunfire:
hi ,all When I used the Micron mt48lc4m32b sim model in my SDRAM Controller,a surprise issue occured. That is when I execute write command(single write or burst write) to external SDRAM, when the actual burst length is smaller than the burst length set by sdram model mode register,and there are some idle operation between t
i'm drawing the sim card holder (part no. is Molex 91236, 6pins) PCB component libs, but there's no pins assignment, where can i get them? please help me. thank you
How to copy sim card of a mobile phone?(a copier circuit)
How can i know the standard of a sim card from it's shap and where i can find books about such standard and sim card pin assignment .. :?
helo dears any one guide me or post me the softwere and how to convert the cdma mobile(sim card type) to gsm mobile thanking you
Hi, I found that i can perform post-simulation by setting up the config view or just simply insert the extracted view to the simulation envirment. Am I doing the same thing? What is the different? Dragonwell
Hi, Can anyone tell me what is the CAM "satallite" sim Card interface protocol usually? I want to know if it is I2C or ISP or what
HI!!! As I am carrying out nc-sim run the simulator, I have met the following problem. I have two file adder.v(gatelevel file) & adder.sdf. I increase " $sdf _ annotate ("adder.sdf" , uut)" in testbench too. Can anyone tell me the meaning? ? ##################################################### nclaunch> ncelab -work wor
I want to clone my cellular phones sim card. but i havent got any idea. do you have any idea or documents to do this?
I simulate my design by using NC-sim 5.3. I found a strange phenomenon when I saw the related simulation waveform. There is a bug occured. The below is my testbench code: always @(lnbuf_m0_ADDR) begin lnbuf_m0_ADDR_d = #3 {1'b0, lnbuf_m0_ADDR}; end When the lnbuf_m0_ADDR countes from 8'hFF to 8'h00, the number of (...)
if any one knows about any PCMCIA card or any related device in which the sim can be inserted to run internet on laptop through GPRS network. regards, usman
Dear all : somebody know how to sim eye diagram in cadence ? I try a lot of time , the waveform is not same to book. so if someone know to to sim please tell me . thanks .
Does anybody know how the variables in a VHDL code can be seen in the waveforms when NC-sim or Modelsim is used? I can only see the signals. Thanks.
I'm running some VHDL simulation with NC-sim and I encountered the following error. As I'm pretty new to using NC-sim for VHDL, can anyone tell me what's the error message actually mean and how to resolve it. ncsim: 05.30-s005: (c) Copyright 1995-2004 Cadence Design Systems, Inc. ncsim: *F,TOOMNS: more (...)
Hello, Anyone know about the difference between microchip icd2 and simulator (mplab sim)? I found that microchip icd2 has a lot of limitation in debugging and needs actual device. On the other hand, mplab simulator does not need actual device. So, what are the advantages of icd2? Thanks, ako
Dear all, Could anyone teach me how could I set the parameteric simulation in background? I just know how could I sim in background by using runsimulation script. Thanks wccheng