1000 Threads found on edaboard.com: Random Sequence Generator Code
4-1. random-Bit Noise generator??.??????????.?. 32
4-1-1. Uniform-Distributed random-Bit generator??.?.. 33
4-1-2. Normal-Distributed random-Bit generator????. 34
4-1-3. Pseudo-random random-Bit generator?????? 35
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-10-2007 00:24 :: IanP :: Replies: 2 :: Views: 1729
can any one send a system VERILOG code for random sequence generator
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-06-2011 02:53 :: solanke :: Replies: 0 :: Views: 328
Most of lfsr approach can't generate psuedo random sequence with
Doesn anyone know how to generate psuedo random sequence with zero number?
ASIC Design Methodologies and Tools (Digital) :: 02-13-2005 23:51 :: corgan :: Replies: 17 :: Views: 1760
Binary sequence generator
I went to generate a sequence of bits
Here length is 600*8 bits (this is fixed not random sequence)
I will code this in vhdl
Can some help me :cry:
Digital Signal Processing :: 02-15-2006 03:08 :: n38 :: Replies: 1 :: Views: 2210
why not use sc or sv to generate random sequence?
ASIC Design Methodologies and Tools (Digital) :: 11-26-2009 20:47 :: ljxpjpjljx :: Replies: 3 :: Views: 3403
I have code for Linear feedback shift register. It is not a random number generator in the strict sense. But must be useful in some cases.Download it from opencore.org:
LFSR-random number generator :: Overview :: OpenCores
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-20-2010 09:57 :: vipinlal :: Replies: 3 :: Views: 2267
I have a problem with the random number generator function with MPLAB c programming.
We use rand() to generate 2 numbers, but the 1st number is generated randomly in odd sequence and the other number is generated randomly in even sequence. The number is from 0-7. This is our (...)
Microcontrollers :: 06-21-2012 03:54 :: gordon the light :: Replies: 4 :: Views: 505
I need a "truely random" bit generator ic. It must not be "pseudo random"
I search over the internet but can only find a MCU from Atmel.
If it is possible to be implemented on a single chip, why there is no single ic dedicated for this operation.
Tundra semiconductor has a truely RBG module which occupies too much space on (...)
Professional Hardware and Electronics Design :: 10-02-2003 12:21 :: electro :: Replies: 7 :: Views: 4002
There is a lot of implementation to generate pseudorandom numbers implementin a cellular automata. I want to help you but i donot remmeber how to make it.
Microcontrollers :: 10-05-2004 12:34 :: seinfield :: Replies: 6 :: Views: 7311
Xilinx app note 052, "Efficient Shift Registers, LFSR Counters, and Long Pseudo-random sequence generators"
Xilinx app note 210, "Linear Feedback Shift Registers in Virtex Devices"
Electronic Elementary Questions :: 10-10-2004 08:00 :: echo47 :: Replies: 4 :: Views: 2455
Have a look at
Efficient Shift Registers, LFSR Counters, and Long Pseudo- random sequence generators
XAPP 052 July 7,1996 (Version 1.1) Application Note by Peter Alfke
ASIC Design Methodologies and Tools (Digital) :: 02-13-2005 07:20 :: vomit :: Replies: 8 :: Views: 2771
I guess you CAN'T! All that you can do with logic gives you more or less PSEUDO-random sequences.
True random sequence can be generated using the help of noise generator. There is an application note on the web (can't recall the magazine nor the name of the article right now, sorry) that uses Zener diode (...)
ASIC Design Methodologies and Tools (Digital) :: 05-23-2005 17:26 :: rfmw :: Replies: 5 :: Views: 3857
Pseudorandom Binary generator is nothig but a shift register which will output the sequence of 1s and 0s. This sequence (called a PN sequence) has a random nature ; that is it does not repeat itself. (Well it repeats itself but after a very very long time so that it can be considered as (...)
Digital communication :: 01-13-2006 04:33 :: sachinlan :: Replies: 2 :: Views: 1641
i have made an address sequence generator in verilog. the following part gives the error
always @ (negedge init or negedge rst)
first = 14'b00_0000_0000_0000;
last = 14'b00_0000_0000_0000;
addr = 14'b00_0000_0000_0000;
count = 13'b0_0000_0000_0000;
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-20-2006 00:42 :: samcheetah :: Replies: 2 :: Views: 2330
Now I have to test the design, I need a random packet generator, can anyone help me about the code of this kind of random packet generator?
ASIC Design Methodologies and Tools (Digital) :: 06-16-2006 04:17 :: test_out :: Replies: 2 :: Views: 1177
HI friends ,
I need information about pseudo random number generator to implement it in hardware.
Thanks and Regards,
Look for LFSR techniques, fairly well known approach to do this. Do a google and you can even find HDL code on the net.
ASIC Design Methodologies and Tools (Digital) :: 12-05-2006 04:11 :: aji_vlsi :: Replies: 7 :: Views: 1115
I am trying to do pn sequence generator to remove the spur for phase dithering in Matlab simulink.
I can generate the specific system noise level by using pn sequence simulink model. But this does not reduce the spur due to phase dithering and this system noise level is quite high.
Q1) how to adjust the parameter of pn (...)
Digital communication :: 01-10-2007 00:39 :: alex2007 :: Replies: 7 :: Views: 7525
The random mechanism is pseu-random. If you are interest in the sequence of the instruction, you can research on the pseu-random mechanism.
ASIC Design Methodologies and Tools (Digital) :: 06-19-2007 21:11 :: hawk_chenbo :: Replies: 5 :: Views: 1006
In one of my application which use avr-libc, there is also have this problem. Every first time, rand() will generate the same value. But next, the value is different.
And I see the code:
static unsigned long next = 1;
Microcontrollers :: 01-19-2010 20:12 :: unaided :: Replies: 2 :: Views: 1128
The error message:
"VHDL Unsupported Feature error at : cannot synthesize non-constant real objects or values"
points out what exactly the problem is with the code.
Objects of type Real - floating point numbers cannot be mapped to hardware and therefore are not supported.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-27-2010 03:00 :: bigdogguru :: Replies: 2 :: Views: 2126
suppose i wanna generate random data from 0 to 3 (ie, qpsk data) in matlab simulink
unsing random integer generator.
output should be vector form like
how can i do this using simulink and how to set parameters for that .
thanks in advance.
Digital Signal Processing :: 07-22-2011 03:50 :: zunayeed :: Replies: 3 :: Views: 1700
If you rand() generator gives random numbers in 16 bits, and you need numbers ranging from 0 to 2047 (i.e. 11 bits) you can call rand() function and take the 11 least significant bits of the value it returns.
This does not give a cycle of 2048 values, but longer (with pseudo-random repetitions). Is it really important that all (...)
Digital communication :: 08-29-2011 14:05 :: zorro :: Replies: 6 :: Views: 563
if you r talking abt PRBS(Pseudo random Binary sequence) generator, u should specify how many bits or the length . If u want n- bit PRBS generator ,then it can give u 2^n-1 binary sequences.
For PRBS FPGAsRus PRBS which are usually implemented using an LFSR(linear Feedback Shift register) i.e shift regi
ASIC Design Methodologies and Tools (Digital) :: 12-13-2011 07:34 :: antaryami.mt.er09 :: Replies: 4 :: Views: 2289
Possibly, but the number may be cyclic because the timer will update at a regular rate and will always have the same start value. In other words, you may get something which looks random but gives the same pattern sequence after each processor reset. If you are finding a truly random sequence I would suspect it is because (...)
Microcontrollers :: 08-02-2012 01:36 :: betwixt :: Replies: 1 :: Views: 414
verilog testbench tutorial section at
There are lot of examples demonstrating the behaviour of $random().
PC Programming and Interfacing :: 02-18-2009 07:09 :: www.testbench.in :: Replies: 6 :: Views: 13437
I have Hardware random Number generator (HRNG) Through Serial COM Port (RS232),if i plug it in the COM and restart the PC,Windows XP idintifies it as a mouse and the mouse pointer moves randomly in the screen disply(Note:This problem dosn't appear in windows 98&windows 2000),also when i remove the HRNG from the COM and restart again the (...)
Software Problems, Hints and Reviews :: 10-08-2003 13:52 :: JIF :: Replies: 14 :: Views: 3166
I am trying to design high speed USB HRNG(Hardware random Number generator), i have a source of random number generator which supply 9600 pbs,and i want to use multi-source of this random generator to satisfy the speed of the USB,so can any body help me on this"i mean the (...)
Professional Hardware and Electronics Design :: 10-26-2003 05:47 :: JIF :: Replies: 3 :: Views: 2060
if you are refering to a software solution then you can use matlab to produce random numbers. In particular the function rand.
Digital Signal Processing :: 02-26-2004 07:03 :: etherios :: Replies: 4 :: Views: 1438
there are some cellular automatas that generates pseudo-random numbers.
Analog Circuit Design :: 11-14-2004 19:44 :: seinfield :: Replies: 8 :: Views: 1316
I see project about true hardware random number generator using PSoC microcontroller and Markov network.
Mathematics and Physics :: 11-16-2004 10:18 :: dacadc :: Replies: 5 :: Views: 2139
You might try "lfsr random generator" in google.
I am using LFSR random genartors with good success but as you already wrote a "good" seed value is not so easy to find.
hope this helps
Software Problems, Hints and Reviews :: 11-03-2005 00:23 :: C-Man :: Replies: 5 :: Views: 1011
Where can I find good information how to create a pseudo random noise generator in VHDL.
Use IEEE.MATH_REAL package and UNIFORM function. See:
I believe recent simulators support it as built-in now.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-02-2006 05:10 :: aji_vlsi :: Replies: 6 :: Views: 6312
I need the following paper provided by IEEE;
"sequence generator identification from noisy observations using three way recursions"
Digital communication :: 11-22-2006 02:40 :: mstalebi :: Replies: 0 :: Views: 621
Guys , Can any of u help me regarding this VARIABLE LENGTH UNIFORM random number generator. I have to implement this in verilog.
ASIC Design Methodologies and Tools (Digital) :: 01-13-2007 23:44 :: subramanyam :: Replies: 0 :: Views: 645
In which lang ? If u want for simulation & using verilog u can use $random etc function. Similar function r available in SV & SC etc (Can't be used in RTL)
ASIC Design Methodologies and Tools (Digital) :: 06-07-2007 02:01 :: abhikohli :: Replies: 3 :: Views: 1155
How can I design and implement a serial random bit generator in gate or circuit level.
ASIC Design Methodologies and Tools (Digital) :: 12-14-2007 05:04 :: nassim_el85 :: Replies: 1 :: Views: 659
MODIFY A 3-BIT LINEAR sequence generator TO OUTPUT 4 STATES?
Electronic Elementary Questions :: 03-09-2008 08:50 :: graciousparul :: Replies: 0 :: Views: 432
generally, you can design a random (or pseudo random) sequence generator. you can vary the length of shift register to achieve better results. then add it to your modulator to make your signal busy enough.
Analog IC Design and Layout :: 04-01-2008 02:06 :: amir81 :: Replies: 6 :: Views: 840
If you want truly random noise. Force current backwards on a BJT transistior base-emitter junction. Then AC couple to an amplifier and include filters to get the frequency range you want.
Analog Circuit Design :: 06-13-2008 13:06 :: flatulent :: Replies: 3 :: Views: 737
I want to design 128 bit RAM based Pseudo random Number generator in FPGA (as in XAPP052)?
Can somebody help me with its implementation in VHDL?
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-24-2009 05:01 :: mufarish :: Replies: 0 :: Views: 932
Use the following blocks.
1) Insert Uniform random Number and change the minimum and maximum to 25 and 30.
2) Connect the Rounding Function and change function to round.
You are done!
Digital Signal Processing :: 12-15-2009 02:04 :: MHanif :: Replies: 2 :: Views: 3356
I am trying to design a PN sequence generator circuit with Cadence software. LFSR and Xor gate work properly, but PN sequence does not work and simulation result just shows some glitches, Could you please someone help me?
Electronic Elementary Questions :: 01-19-2011 19:50 :: NARINA :: Replies: 4 :: Views: 786
Is it the same as the white noise which means the power is equally divided in the whole frequency range?
If so, how does it come? Any reference is preferred.
Now I've built a pseudo-random sequence using linear feedback shift register(LFSR), and I'd like to check its power spectral, is it possible to make it out using Cadence and how?
Analog Circuit Design :: 12-17-2011 06:07 :: bsaqycx :: Replies: 0 :: Views: 270
For a car-fob, when a certain code have been accepted by receiver is it automatically blocked against reuse. Else had it not been a working rolling code system.
A common rolling code system is KeeLoq which have a 32 bit random sequence generator. When a key fob is paired in a such system, (...)
RF, Microwave, Antennas and Optics :: 12-26-2013 04:56 :: E Kafeman :: Replies: 4 :: Views: 1064
It's not the language, it's the methodoloy. If you like a random sequence generator, specman is definitely the best choice. Wanna save money? Try , CVE is great!
ASIC Design Methodologies and Tools (Digital) :: 03-12-2004 06:28 :: farmerwang :: Replies: 14 :: Views: 1729
Signal source is a (pseudo-)random sequence generator.
Oscilloscope must have external trigger input, use sequence generator clock as trigger signal.
To measure, hook up oscilloscope to end of transmission media (receiver side).
To implement a sequence generator in (...)
PCB Routing Schematic Layout software and Simulation :: 08-08-2009 07:17 :: alenze :: Replies: 1 :: Views: 2674
Clydesdale. I think you killed it !
It's a small IC, probably a random sequence generator to make the LED flicker in an unpredictable way. The IC would have been glued to the board, had wires bonded from it to pads nearby then had the blob of epoxy dropped on it to protect it.
If you want to resurrect it you will have to make a (...)
Hobby Circuits and Small Projects Problems :: 09-11-2009 04:21 :: betwixt :: Replies: 3 :: Views: 1409
Anyone has the code or info for the random number generator and the random number verifier. I've to design for the transceiver, which transmiter has 8-bit PRBS and the receiver has PRBS verification.
Any infomation is highly appreciated.
Thank you in advance.
ASIC Design Methodologies and Tools (Digital) :: 01-15-2004 21:02 :: always@smart :: Replies: 17 :: Views: 26694
Whether the seed are initialised to a particular number or left uninitialised, for both cases, same sequence of random number are generated
I think this is not true for a LFSR generator. probably you could not load your LFSR correctly or mot simulating enough time.
I need random seed values after each cycle of
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-13-2013 09:47 :: Port Map :: Replies: 8 :: Views: 614
Does anybody know where to get a Matlab file that generates very close to independent random samples? If you look at the higher order statistics of rand or randn, they are not as independent as I would like them to be. Any suggestions?
inorder for u to generate random numbers, u could use the PN sequence generator,
Digital Signal Processing :: 03-08-2005 14:59 :: cedance :: Replies: 12 :: Views: 2693