82 Threads found on edaboard.com: Readline Vhdl
Hi Shiva:
Thanks for the reply. Here is the code I used for reading values from file into an array. This process is similar to an example from Designer's guide to vhdl (By Peter Ashenden). I'm not sure as to where the problem is.Please help me out with this.
process
type Y_array is array (1 to 2,1 to 2) of integer;
vari
ASIC Design Methodologies and Tools (Digital) :: 21.05.2004 10:06 :: vomit :: Replies: 7 :: Views: 2612
the read function will read values from the same line. There is another version of the function that will tell you if a read has been done sucessfully. It will ignore whitespace, so there is no need for you to read the whitespace between values. You also dont need a temporary integer to store the read values.
architecture Behavioral of fil2
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.06.2011 10:13 :: TrickyDicky :: Replies: 29 :: Views: 2048
When you use vhdl Code... Write TAG Code--- it's more readable
library ieee,std;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity tb is
end tb;
architecture beh_tb of tb is
component dff
port ( d : in bit;
q : out bit;
clk : in bit;
rst : i
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.05.2005 10:20 :: OvErFlO :: Replies: 5 :: Views: 1156
Hello,
I'm trying to read some stimulus form a file, but an error always occur, would you like to help me to solve it, thanks.
Source code:
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity FILE_READ is
generic (
stim_file: string := "sim.dat"
);
port(
CLK
ASIC Design Methodologies and Tools (Digital) :: 13.03.2006 04:46 :: bigdog :: Replies: 2 :: Views: 3179
I use modelsim in vhdl design. I want to call data from fetalint.txt. my code is
use std.textio.all;
file infile: text is in "fetalint.txt";
variable ip1: integer range -4096 to 4095;
variable buf: line;
process
begin
while not(endfile(infile)) loop
readline(infile,buf);
read(buf,ip1);
W_data<=ip1;
wait until falling_edge(W_clock
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.04.2006 17:27 :: coo848 :: Replies: 1 :: Views: 538
hello
I am writing a vhdl program for reading text files and i run it in modelsim but it gives me the following error
** Error: (vsim-7) Failed to open vhdl file "hds_projects/my_project2/my_project2_lib/hdl/file_io.txt" in rb mode.
# No such file or directory. (errno = ENOENT)
why???
plz help
i attached the vhdl code (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.05.2006 15:58 :: emmos :: Replies: 9 :: Views: 9233
hii,
I am doing a project on memory controller in which i am trying to implement a design using fifos and FSMs . this design acts as an interface between the fast peripherals sending burst of data , and a slow memory.
i have implemented the design in vhdl. whenever the external device request read into memory, my des
ASIC Design Methodologies and Tools (Digital) :: 16.08.2006 16:13 :: mpatel :: Replies: 6 :: Views: 1396
Textio is d keyword.. :)
TEXTIO is a package of vhdl functions that read and write text make the package visible:
use std.textio.all;
Data Types:
text - a file of character strings
line - one string from a text file
Example Declarations
file Prog: text is in "file_name"; --text file "file_name"
variable L: line
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.01.2007 17:51 :: tut :: Replies: 3 :: Views: 7324
Hi Everyone, currently i'm doing a final year project. I'm having a problem on the output signal. My It2 doesnt seems to haf clk, it's just gif an output of 0(decimal) all the way. Not like Xr2 or Xi2. The following is my Main program and test bench.
The filter is generated from GEN Core. It's a DA FIR 32 tap filter. I dont know where went wrong.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.07.2007 09:35 :: YenYu :: Replies: 0 :: Views: 484
in vhdl every thing is in binary, you cannot have a data type which can store hex. so when you will read from a file using something like
variable l1 : line;
variable var1 : std_logic_vector(7 downto 0);
.
.
readline(f1,l1); --read a line from a file f1 which contains hex words example FE
hread(var1,l1); -- read into var1, a hex val
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.11.2007 23:05 :: avimit :: Replies: 13 :: Views: 12323
sure!!
i assume that you want to use this for a testbench or some simulation purpose only.
add the textio package from synopsis into your project directory from the path i told you before. compile it .
to understand how to use these hread, hwrite etc procedure in your code you can simply open the package file and understand its input and output
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.04.2008 12:40 :: kvingle :: Replies: 6 :: Views: 7449
You may want to see how it is done on LEON project.
file TCF : text is in fname;
begin
if FIRST then
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.01.2009 17:07 :: pini_1 :: Replies: 2 :: Views: 6979
i think u have missed the "readline" function before read function...
Check the below link
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.07.2009 07:56 :: shanmugaveld :: Replies: 4 :: Views: 4260
the code is below.when i simulation,read file fail.why?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
library std;
use std.textio.ALL;
entity rom is
Port ( read : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (15 downto 0);
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.08.2009 15:23 :: honeyleabe :: Replies: 0 :: Views: 981
Hi,
-- extra packages:
library std;
use std.textio.all;
use ieee.std_logic_textio.all;
-- file declaration (vhdl 93 syntax) in architecture:
file fin : text open read_mode is "c:/temp/input_file.txt";
-- read file contents somewhere in process:
process....
variable inp_line : line;
begin
---
while not endfile (fin) loop
readline(
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.01.2010 08:53 :: devas :: Replies: 7 :: Views: 2875
HI all
Is the below code snippet for file reading is fine. I am not able to open this file, so please correct the code. I am newbie to vhdl.
procedure PrepareInput is
VARIABLE inLine : LINE;
VARIABLE dataRead : REAL;
VARIABLE index : integer:= 0;
file file_in : text open read_mode is "lena_64_64.txt";
ASIC Design Methodologies and Tools (Digital) :: 13.02.2010 14:29 :: raghava :: Replies: 0 :: Views: 376
HI all,
This is the testbench on which I am working. It consists of text (Image pixel data) file reading and writing. I am facing problem in doing so. Can anybody could correct my test bench where file reading and writing is taking place.
I am newbie to vhdl and I am facing problem here. Please help me in this regard.
*******************
ASIC Design Methodologies and Tools (Digital) :: 13.02.2010 14:50 :: raghava :: Replies: 4 :: Views: 2084
HI all,
I am facing problems with file reading in vhdl. I am newbie to vhdl.
I am expecting answers.
Here is the code and error message I have got.
***********************
procedure PrepareInput is
variable inLIne: line;
variable int_text : integer:= 0;
variable index : integer:= 0;
--file file_in : text open read_
ASIC Design Methodologies and Tools (Digital) :: 17.02.2010 14:18 :: raghava :: Replies: 6 :: Views: 1630
Hi all,
How to read a 24 bit bmp file in vhdl. This is the code I have written.
Here also exit when endfile is needed na????
***********************
procedure bmp_read is
variable inline: line;
variable b:character;
variable g:character;
variable r:character;
variable end_of_line:boolean;
type char_file is file of char
ASIC Design Methodologies and Tools (Digital) :: 18.02.2010 09:48 :: raghava :: Replies: 4 :: Views: 1846
I see you have an image of a table tennis bat/ball..
to read in the image, try the following code that I used to find out exactly what your image was (which I then wrote into a bitmap file):
type img_array_t is array(natural range <>, natural range <>) of natural;
signal img_array : img_array_t(0 to X_SIZE-1, 0 to Y_SIZE-1);
.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.07.2010 10:17 :: TrickyDicky :: Replies: 25 :: Views: 4267
in the below i have this runtime error :
no digits found in abstract literal
textio procedure READ(INTEGER): can not get value from "?" (? shows some unkhon character)
and then equal to the 16*16 times generate this error:
textio procedure READ(INTEGER) :parameter L designate an empty string
what does it mean?
for i in 0 to 15
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.07.2010 08:29 :: MOOMOO_KAMP81 :: Replies: 17 :: Views: 1913
Hi Haneet,
Something like:
library ieee;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
architecture xxxx of yyyy is
file fin : text open read_mode is "";
process(zzzz)
variable rdline : line
variable hex : std_logic_vector(3 downto 0);
begin
while not endfile(fin) loop
readline(fin, rdli
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.08.2010 08:56 :: devas :: Replies: 6 :: Views: 1631
HI all,
I am facing problems with reading binary files in vhdl. I want to make a ROM with the size 512*8bit. Firstly, initialing the ROM and then reading data.
Here is the code and error message I have got. I am expecting answers.
***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.11.2010 07:56 :: lijing8898 :: Replies: 3 :: Views: 2363
hai
i want to read the pixel values of two images and perform correlation between the pixels using vhdl.
firstly i got the pixel values of the images and stored the values in two text files. now i want to read values from the text files, perform cross correlation and want to write results to another text file.
can
Electronic Elementary Questions :: 22.02.2011 17:17 :: manoranjan sb :: Replies: 0 :: Views: 654
Thank you all for the replies,
A code example is:
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT m_est15x
PORT(
in : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
ms : OUT std_logic_vector(13 downto 0)
);
END COMPONENT;
co:process
if ms'ev
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.03.2011 20:26 :: Angelonut :: Replies: 10 :: Views: 738
its a text file..
---------- Post added at 11:43 ---------- Previous post was at 11:42 ----------
it is a text file stored in notepad
---------- Post added at 11:45 ---------- Previous post was at 11:43 ----------
the main program is ..
library ieee;
use ieee.s
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.04.2011 08:15 :: chat :: Replies: 10 :: Views: 718
hello all, i have with me a spartan 3 starter board that has 4 LEDs and 4 capacitive touch pads that can be interfaced with. i have an upcoming project that would use the spartan 3A FPGA and i figured this starter board would be a good place for me to start as i have no experience with FPGAs and vhdl programming.
i intended to program the FPGA
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.04.2011 05:52 :: ptjw :: Replies: 12 :: Views: 2125
Hello, I am trying to read a single line from a text file and then output it to another text file.
Here is my current code:
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use Ieee.std_logic_unsigned.all;
use std.textio.all;
entity tb_project is
end tb_project;
architecture tb_project_arc
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.04.2011 08:27 :: VHDLStarter :: Replies: 15 :: Views: 1851
while not endfile(loaddata) loop
readline(loaddata,adline);
read(adline,advalue);
end loop;
If there is more than one data line in your file, it's ignored except for the last one that's stored in advalue. So the observed behaviour is pretty understandable.
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.04.2011 13:19 :: FvM :: Replies: 3 :: Views: 1193
Does Xilinx XST support vhdl textio library for synthesized code? Most likely not.
P.S.: If it's for a simulation test bench, the sequence would be
for i in ar'range loop
readline(f, inline);
read(inline, ar(i));
end loop;
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.06.2011 20:13 :: FvM :: Replies: 13 :: Views: 1627
hi i want to know how many characters does a readline command reads.
is it full one line or is there any limitation for it.?????????
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.06.2011 18:48 :: chitra ranganath :: Replies: 2 :: Views: 387
there is no way to do this easily in vhdl. vhdl is not set up to do File io nicely other than text.
What file are you trying to read? For every file you can use the ENDFILE() function to see if you have reached the end of a file:
eg.
while not ENDFILE(my_file) loop
readline(file, inline);
...etc
end loop;
You could use this lo
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.06.2011 16:33 :: TrickyDicky :: Replies: 2 :: Views: 675
Hello! i want to read input from a file, and i have written a testbench which is correct for reading positive integer numbers.
But when i read negative numbers it gives me error message so its either problem of my reading input or of my vhdl programme.
What i want is when reading a negative number "tranform" it in the following form: msb is the
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.12.2011 13:04 :: ghostridergr :: Replies: 15 :: Views: 585
A few days ago I had the exact same problem. I also used my code in a process:
txt_inp:process(CLK, write_en)
begin
if rising_edge(CLK) then
if write_en <= '1' then
while not((endfile(Datafile))) loop
readline(Datafile, L);
Read(L, mem_data);
TXTRAM(i) <= mem_data;
i <= i +1;
end loop;
end if;
end if;
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.12.2011 10:06 :: 153rd :: Replies: 8 :: Views: 1455
Hi all;
I found a memory code,but I think it is not synthesis because it use file command. Is it the code below is synthesis? If not, how to make it synthesis? Thank you
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity Memory is
generic
(
WIDTH
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.02.2012 15:42 :: fanwel :: Replies: 10 :: Views: 917
hi
I want to read bmp files in vhdl. I need only data values,so I skip header by reading each character in the header. but there is a problem that we may encounter with a NL(new line) character. when it exist I must use readline to get new line. I do this and it works but problem is when I use it, it takes time for each character(for 8bbp,1078 ch
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.03.2012 14:42 :: alvearal :: Replies: 6 :: Views: 517
Well this is my testbech code:
library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.my_package.all;
entity tb_landmark is
generic
(N :integer := 8;
NA:integer:=3);
port (
rst: in std_logic;
vin: in std_logic
);
end tb_landmark;
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.03.2012 13:39 :: ghostridergr :: Replies: 2 :: Views: 398
Hello,
I'm trying to read some stimulus from a file. The format is the following:
signal1 signal2 signal3 ...
101 0 11001011
111 1 00001001
....
Each line is a "cycle" of the FSM wich I want to test.
Here is my code:
library IEEE;
library modelsim_lib;
use IEEE.std_logic_1164.all
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.04.2012 13:45 :: Fackelmann :: Replies: 6 :: Views: 459
I have a RAM code here in vhdl where I have to convert to Verilog.
vhdl seems very complicated on its grammar and I am new to this field.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE STD.TEXTIO.ALL;
USE IEEE.std_logic_TEXTIO.ALL;
ENTITY std_logic_ram IS
PORT (address : IN std_logic_ve
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.05.2012 05:52 :: sukyen :: Replies: 2 :: Views: 212
Here's an example that reads a single stimulus vector (representing an analog waveform) line by line. You can easily extend it to read additional values and possibly write output data to a second file.
Process
file IN_DAT : text open read_mode is "scope.txt";
variable LI: line;
variable MV: integer;
Begin
while not
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.07.2012 17:10 :: FvM :: Replies: 15 :: Views: 503
Hi all
I wrote a vhdl code for file read. Its for getting array of integers from the check whether this program working properly ,Ineed to write a testbench.Please help t write testbench for this code. I am using xilinx 10.1 version.I generated atestbench in this , but couldn't work out.
library ieee;
use ieee.std_logic_
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.08.2012 07:36 :: ammassk :: Replies: 1 :: Views: 265
Hi!
I want to read two integer values from a .txt file named "entry.txt", which is located in the project folder, with all of the .vhd files.
-- ...
variable inline : line;
file inputFile : text open read_mode is "entry.txt";
variable mynum: integer;
variable stdmynum: std_logic_vector (N-1 downto 0);
-- ...
readline(inputF
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.09.2012 10:37 :: vtomic85 :: Replies: 1 :: Views: 313
The example i got on net is as follows please have a look on it and guide me to solve this problem:-
vhdl CODE:-
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ADDER is
port(VALUE_1 : in std_logic_vector(7 downto 0);
VALUE_2 : in std_logic_vector(7 downto 0);
OVERFLOW : out
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.10.2012 09:08 :: avnish5mishra :: Replies: 7 :: Views: 215
Well for a testbench, you're not using the correct package, you should be using textio - it already has a file type, Text, declared for you and assosiated read/write and readline/writeline procedures. There are numerous tutorials around the web, so use google.
For actually doing it in an FPGA, why would you do that? you would need a file handler s
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.01.2013 16:15 :: TrickyDicky :: Replies: 7 :: Views: 189
I managed to get a code for initialising my generated values to the addresses in the LUT but I get the following errors:
-syntax error near for
-i is not declared
-synax error near loop
-unit behavioural ignored due to previous errors
I tried to resolve these errors but had no luck so far, I don't know if I am doing something wrong. Can anyone pl
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.02.2013 23:39 :: bachoo786 :: Replies: 18 :: Views: 451
is the 3rd signal data?
I ran the code, changed Data from buffer to out and inserted the piece of code that you gave me converting std_logic inputs to unsigned and I get errors. Here's the code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity main is
port(
Addr: in std_logic_vector (0 to 15);
Clk: in std_logic;
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.02.2013 14:26 :: bachoo786 :: Replies: 85 :: Views: 1471
Use the textio package:
use std.textio.all;
It allows you to read text files. The important procedures you need to know are
readline/writeline : read/write a line of text from a text file into a line type.
read/write(l, x) : where l is the line, and x is the signal/variable you want to read/write a value to.
Here is a quick demo:
[syntax=vhdl
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.04.2013 10:24 :: TrickyDicky :: Replies: 6 :: Views: 152
Dear Tricky Dicky,
I am having unexpected error while trying to open with the string variable's name rather string itself.
Please see the simplest code first then the error.
Note that this same program when run with the name "data0.txt" itself runs perfectly fine, when I change to either variable or string post the below error
Finished ci
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.04.2013 10:51 :: syedshan :: Replies: 22 :: Views: 289
I tried with this code......
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use std.textio.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity image_read is
--port(
--typ
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.04.2013 18:42 :: aara :: Replies: 11 :: Views: 258
use ieee.std_logic_textio.all;
use std.textio.all;
file master_file : TEXT is in "E:\??\??\??";
begin
process
variable Lbuf : Line;
readline(master_file, Lbuf);
...
ASIC Design Methodologies and Tools (Digital) :: 18.06.2004 06:37 :: roger :: Replies: 4 :: Views: 1148