1000 Threads found on edaboard.com: Readline Vhdl
Thanks for the reply. Here is the code I used for reading values from file into an array. This process is similar to an example from Designer's guide to vhdl (By Peter Ashenden). I'm not sure as to where the problem is.Please help me out with this.
type Y_array is array (1 to 2,1 to 2) of integer;
ASIC Design Methodologies and Tools (Digital) :: 05-21-2004 04:06 :: vomit :: Replies: 7 :: Views: 3989
I use modelsim in vhdl design. I want to call data from fetalint.txt. my code is
file infile: text is in "fetalint.txt";
variable ip1: integer range -4096 to 4095;
variable buf: line;
while not(endfile(infile)) loop
wait until falling_edge(W_clock
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-01-2006 10:27 :: coo848 :: Replies: 1 :: Views: 710
Textio is d keyword.. :)
TEXTIO is a package of vhdl functions that read and write text make the package visible:
text - a file of character strings
line - one string from a text file
file Prog: text is in "file_name"; --text file "file_name"
variable L: line
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-19-2007 11:51 :: tut :: Replies: 3 :: Views: 8070
in vhdl every thing is in binary, you cannot have a data type which can store hex. so when you will read from a file using something like
variable l1 : line;
variable var1 : std_logic_vector(7 downto 0);
readline(f1,l1); --read a line from a file f1 which contains hex words example FE
hread(var1,l1); -- read into var1, a hex val
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-29-2007 17:05 :: avimit :: Replies: 13 :: Views: 14331
i assume that you want to use this for a testbench or some simulation purpose only.
add the textio package from synopsis into your project directory from the path i told you before. compile it .
to understand how to use these hread, hwrite etc procedure in your code you can simply open the package file and understand its input and output
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-05-2008 06:40 :: kvingle :: Replies: 6 :: Views: 9141
-- extra packages:
-- file declaration (vhdl 93 syntax) in architecture:
file fin : text open read_mode is "c:/temp/input_file.txt";
-- read file contents somewhere in process:
variable inp_line : line;
while not endfile (fin) loop
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-12-2010 02:53 :: devas :: Replies: 7 :: Views: 3713
Is the below code snippet for file reading is fine. I am not able to open this file, so please correct the code. I am newbie to vhdl.
procedure PrepareInput is
VARIABLE inLine : LINE;
VARIABLE dataRead : REAL;
VARIABLE index : integer:= 0;
file file_in : text open read_mode is "lena_64_64.txt";
ASIC Design Methodologies and Tools (Digital) :: 02-13-2010 08:29 :: raghava :: Replies: 0 :: Views: 599
I am facing problems with file reading in vhdl. I am newbie to vhdl.
I am expecting answers.
Here is the code and error message I have got.
procedure PrepareInput is
variable inLIne: line;
variable int_text : integer:= 0;
variable index : integer:= 0;
--file file_in : text open read_
ASIC Design Methodologies and Tools (Digital) :: 02-17-2010 08:18 :: raghava :: Replies: 6 :: Views: 2332
How to read a 24 bit bmp file in vhdl. This is the code I have written.
Here also exit when endfile is needed na????
procedure bmp_read is
variable inline: line;
type char_file is file of char
ASIC Design Methodologies and Tools (Digital) :: 02-18-2010 03:48 :: raghava :: Replies: 4 :: Views: 3108
architecture xxxx of yyyy is
file fin : text open read_mode is "";
variable rdline : line
variable hex : std_logic_vector(3 downto 0);
while not endfile(fin) loop
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-05-2010 02:56 :: devas :: Replies: 6 :: Views: 3466
I've only been using vhdl for a few months now, and i'm currently working on a RAM module in which the contents of the memory are initially loaded from a file. The module has 5 address lines, 8-birectional data lines, an active low enable, and a read/write select input.
At the moment, i've got to a stage were some sort of value seems to b
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-30-2011 06:19 :: MRLL :: Replies: 3 :: Views: 1800
Ill assume each value is stored on a seperate line:
type some_array_t is array(integer range <>) of integer;
signal ar : some_array_t(0 to 99); --could be a varaible
--inside a process
file f : text open read_mode is "my_file.txt";
variable inline : line;
for i in ar'range loop
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-03-2011 09:08 :: TrickyDicky :: Replies: 13 :: Views: 2740
hi i want to know how many characters does a readline command reads.
is it full one line or is there any limitation for it.?????????
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-06-2011 12:48 :: chitra ranganath :: Replies: 2 :: Views: 578
there is no way to do this easily in vhdl. vhdl is not set up to do File io nicely other than text.
What file are you trying to read? For every file you can use the ENDFILE() function to see if you have reached the end of a file:
while not ENDFILE(my_file) loop
You could use this lo
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-17-2011 10:33 :: TrickyDicky :: Replies: 2 :: Views: 1153
Here's an example that reads a single stimulus vector (representing an analog waveform) line by line. You can easily extend it to read additional values and possibly write output data to a second file.
file IN_DAT : text open read_mode is "scope.txt";
variable LI: line;
variable MV: integer;
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-30-2012 11:10 :: FvM :: Replies: 15 :: Views: 1167
I want to read two integer values from a .txt file named "entry.txt", which is located in the project folder, with all of the .vhd files.
variable inline : line;
file inputFile : text open read_mode is "entry.txt";
variable mynum: integer;
variable stdmynum: std_logic_vector (N-1 downto 0);
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-22-2012 04:37 :: vtomic85 :: Replies: 1 :: Views: 900
the readline(file, line) procedure reads an entire line from a text file. You then use read(dest, line) to extract elements from that line.
- - - Updated - - -
Or, to make our lives a little easier, post the code that doesnt work and ask some good questions.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-02-2014 04:00 :: TrickyDicky :: Replies: 12 :: Views: 341
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments....
For FPGA design, what I have used synthesis tools(only to synthesis vhdl code): Synplicity Synplify > Synopsys FPGA Compiler II > Mentor Leonardo Exemplar
It is only my personal opinion...
Professional Hardware and Electronics Design :: 07-13-2001 17:19 :: :: Replies: 7 :: Views: 3658
If you want an audio interactive tutor to learn Verilog or vhdl.. I did upload it for someone who did ask me... ES PERAN Verilog & vhdl.
If you are interested let me know
Professional Hardware and Electronics Design :: 08-06-2001 13:01 :: henrik2000 :: Replies: 5 :: Views: 9988
I am a student from Harbin China. Now I am building a behavioral model of a Direct Sequence Spread Spectrum Communication system using vhdl-AMS. So i want to know where can I find some example similar to that or something that may give help to me.
Can you give me some advices. Thank you!
[ This Message was edited by: flybear on
Professional Hardware and Electronics Design :: 10-29-2001 04:17 :: flybear :: Replies: 0 :: Views: 1532
vhdl QUICK Reference Guide
Ready for onboard prints
Uploaded file: vhdlref.pdf
Microcontrollers :: 02-21-2002 06:04 :: jimjim2k :: Replies: 2 :: Views: 3149
where to get test bench with vhdl for SDH chip?
Microcontrollers :: 02-22-2002 00:49 :: coolsniper :: Replies: 10 :: Views: 2327
The vhdl Golden Reference Guide
A 136 pps ebook.
Uploaded file: vhdl-golden-reference.pdf
Please don't reply unless you have useful information to add on this post. Thanks !
(No Me-too's, no Thanks-you's, etc ... use
Microcontrollers :: 02-24-2002 06:48 :: jimjim2k :: Replies: 3 :: Views: 7777
Here is the vhdl code for 8051 MC.
Uploaded file: 8051 in vhdl.zip
Microcontrollers :: 02-24-2002 06:59 :: jimjim2k :: Replies: 8 :: Views: 7815
LEON is a synthesisable vhdl model of a 32-bit SPARC* compatible processor, developed by the European Space Agency (ESA) for future space missions. To promote the SPARC architecture and enable development of system-on-a-chip (SOC) devices using SPARC cores, ESA is making the full source code freely available under the GNU LGPL license.
Microcontrollers :: 02-25-2002 09:00 :: jimjim2k :: Replies: 5 :: Views: 3634
vhdl Language reference manual. latest edition.
Please don't reply unless you have useful information to add on this post.
Any other replies are always welcome via PM.
[ This Message was edited by: KARLZ on
Microcontrollers :: 03-01-2002 15:09 :: KARLZ :: Replies: 3 :: Views: 2379
Online vhdl Testbench Generator
1. TestBench Tool
3. -> t
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-02-2002 08:40 :: jimjim2k :: Replies: 6 :: Views: 6676
These materials are made available for ECE 4170: Introduction to HDLs with Applications to Digital Design taught during the Spring 2000 Semester at Georgia Tech.
This text focuses on presenting the basic features of the vhdl language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by fami
Microcontrollers :: 03-02-2002 09:09 :: jimjim2k :: Replies: 9 :: Views: 3329
Anyone interested in a single entity vhdl testbench generator, try this. Code is free to do with as you wish. If you add significant enhancements, please send me a new copy too. You will need to have Tcl/Tk installed on you system to use this.
Uploaded file: tb_gen.tcl
Microcontrollers :: 03-04-2002 20:12 :: mexico_mike :: Replies: 2 :: Views: 3773
Would you please upload IEEE Standards
for verilog and vhdl to this place.
1. If you have uploaded files in some other boards, please leave a URL pointer only.
2. Please rename the files before uploading by the a definitive words to distingush files from each other. It seems that the forum replaces every newer file with
Microcontrollers :: 03-05-2002 02:40 :: jimjim2k :: Replies: 0 :: Views: 1631
Which most prefer or popular? vhdl or Verilog?
ASIC Design Methodologies and Tools (Digital) :: 03-09-2002 12:13 :: cadb0y :: Replies: 113 :: Views: 15477
Anyone has a DSP core in vhdl or Verilog? Prefer TI but anyone will do.
Microcontrollers :: 03-14-2002 11:16 :: ASIC :: Replies: 14 :: Views: 5367
Would anyone share the RS232 vhdl code ?
If you have RS232 test program , please share.
Thanks a lot.
Other Design :: 03-30-2002 04:47 :: cssheu :: Replies: 11 :: Views: 13148
Please suggest good books in this thread for vhdl/Verilog ASIC design
ASIC Design Methodologies and Tools (Digital) :: 04-04-2002 05:12 :: antipattern :: Replies: 7 :: Views: 1985
Tutorials for vhdl and Verilog.
HDL Synthesis for FPGAs: Design Guide (PDF 2MB)
SystemC -- Technical Papers
Cypress: Programmable Logic: vhdl Page
Cypress: Design Resources : Technical Articles
Logic Synthesis with vhdl System Synthesis
vhdl SYNTHESIS TUTORIAL
vhdl Coding Style manual (...)
Microcontrollers :: 05-09-2002 06:32 :: jimjim2k :: Replies: 5 :: Views: 3348
signal rd,dr : std_logic;
ad_bus,ram_bus : inout;
process(rd) ---- right.
if (rd='0' and dr='1') then
process(rd) ---- error.
if (rd='0') then
if dr='1' then
ASIC Design Methodologies and Tools (Digital) :: 05-19-2002 10:17 :: 75 sinfocia :: Replies: 9 :: Views: 1182
This object of this course is to introduce the student to more of the vhdl modeling language than what has been covered in previous courses.
1. -> t
Microcontrollers :: 06-09-2002 08:29 :: jimjim2k :: Replies: 0 :: Views: 1457
1. -> t
Microcontrollers :: 07-11-2002 03:09 :: jimjim2k :: Replies: 0 :: Views: 1465
1. -> t
Microcontrollers :: 07-11-2002 04:11 :: jimjim2k :: Replies: 0 :: Views: 1422
is there any software which convert matlab code to vhdl?
how can i get it?
PC Programming and Interfacing :: 07-13-2002 04:04 :: baa110 :: Replies: 32 :: Views: 15190
I am seeking cache controller vhdl example,
I hope some good guy can give me hint or
tell me where I can find it.
It is better a standalone module, simple.
Microcontrollers :: 07-17-2002 14:24 :: john5888 :: Replies: 6 :: Views: 3791
here is a link to comp.lang.vhdl newsgroup about the
necessary of the sensitivity list. very interesting.
PC Programming and Interfacing :: 10-03-2002 09:38 :: kobik :: Replies: 0 :: Views: 1704
Can any body help me if you have vhdl code for BFSK or even clear flowchart
PC Programming and Interfacing :: 12-08-2002 03:06 :: Vonn :: Replies: 0 :: Views: 1526
Is it possible that Vera work with NC-verilog/vhdl ?
ASIC Design Methodologies and Tools (Digital) :: 12-12-2002 09:47 :: DeepIC :: Replies: 7 :: Views: 2656
I need tha vhdl of the PCI LogiCORE interface from Xilinx.. could you help me???
Tnx a lot
PC Programming and Interfacing :: 12-14-2002 09:55 :: Leron :: Replies: 2 :: Views: 1433
Check for updates and fine resources especially on: Microprocessors/MCUs
1. -> t
Microcontrollers :: 12-15-2002 04:25 :: jimjim2k :: Replies: 0 :: Views: 1292
1. -> t
Microcontrollers :: 12-15-2002 07:05 :: jimjim2k :: Replies: 0 :: Views: 1295
Here is the pdf explains the efficient coding style in the vrilog hdl
ASIC Design Methodologies and Tools (Digital) :: 12-18-2002 04:08 :: hynix :: Replies: 4 :: Views: 2687
I am a newbie when it comes to making a clone of an old 16 bit uP
in vhdl. I know there are a lot of gurus around here so here
is my question.
I am looking for a feedback or hindsight on what to expect
when undertaking such a project. Are there any good books written
which might help me in tackling this kind of problem?
I know that
Other Design :: 12-19-2002 06:02 :: LLCD :: Replies: 5 :: Views: 2351
I was thinking of designing a 32 bit alu with vhdl.. I have coded with functionalites add,sub,and,or,etc....(no multiplication and divsion)..
My doubt is i just wrote
when 001-> c<- a and b;
is it this much easy to design an alu.. or I am doing something wrong ..
also How would
ASIC Design Methodologies and Tools (Digital) :: 12-22-2002 07:09 :: eda_wiz :: Replies: 6 :: Views: 4553