1000 Threads found on edaboard.com: Reduce
NO you are driving a DC motor at less than 10% of it's rated voltage so there is little back EMF to reduce the current.
It is like driving a car from a stop light in 5th gear
Elementary Electronic Questions :: 11-04-2016 03:16 :: SunnySkyguy :: Replies: 14 :: Views: 678
Changing RTL is always the easiest option.
Have you got register merging turned off? Than can help reduce the register fan outs.
All false paths and multi cycle paths specified?
Finally you can try overconstraining a single path using a set max delay, but this can often make it harder to route adjacent nets and is a rather tedious job.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-02-2016 07:35 :: TrickyDicky :: Replies: 2 :: Views: 353
Wanted to ask "How to choose voltage rating of SMD ceramic capacitors"?
It depends. AC or DC voltage load, low or high permittivity dielectricum. For the latter, you may reduce the voltage to 50 % of the rated voltage due to the capacitance drop versus applied voltage.
- - - Updated - - -
By reading manuf
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-30-2016 17:24 :: FvM :: Replies: 3 :: Views: 654
Assuming it's not, in fact, the B terminal?
Give us a picture, or something.
Could be a field plate to control the nasty low quality
oxide at the base surface, in which case tying to the
emitter (or most positive potential) could stiffen up the
surface concentration and reduce the injection of
"doomed" carriers (destined to recombine at that
Analog Circuit Design :: 10-29-2016 17:06 :: dick_freebird :: Replies: 3 :: Views: 469
The shown topology can be expected to generate even harmonics due to the asymmetrical current mirror RF input. Should try a standard Gilbert topology with a differential RF input. Or reduce the RF input level.
Analog Circuit Design :: 10-26-2016 05:01 :: FvM :: Replies: 3 :: Views: 465
You just need to reduce the current for a given W/L to enter subthreshold.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-26-2016 13:52 :: deba_fire :: Replies: 4 :: Views: 473
Don't use thermal spokes for RF PCB (L1 ground pad).
I don't see an actual CPWG structure, rather a micro-strip with distant ground via fence, impedance is mostly that of the pure micro-strip. You could however taper the center line and reduce the ground separation towards the end.
Or leave everything as is and put some series inductance for
RF, Microwave, Antennas and Optics :: 10-13-2016 18:02 :: FvM :: Replies: 3 :: Views: 382
2GBps would likely require at a minimum 16-bit transfers using a parallel bus @ 125 MHz, I would probably go to 32-bit just to reduce that clock rate down to 62.5 MHz SDR or stay with 16-bit DDR. It might be better to use a transceiver based solution a single 2.5Gbps SERDES link would suffice. Your budget seems low, as most of the boards Xilinx and
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-12-2016 19:04 :: ads-ee :: Replies: 2 :: Views: 383
is it possible to drive EEPROM or some other chips like accelerometer and ... VCC directly through MCU IO ?!!
i'm thinking of it in order to reduce components count (not using on/off transistor for VCC of each chip) and also reducing power consumption in those chips less than even power down modes by cutting off VCC.
the max current co
Microcontrollers :: 10-12-2016 15:38 :: hm_fa_da :: Replies: 2 :: Views: 422
Your hand is probably radiating ambient 50/60 Hz mains hum. Our bodies pick it up like an antenna, from all around in the room. A sensitive input pin (or mosfet gate, or transistor bias pin) easily responds to it, if the pin is unconnected and allowed to 'float'.
What value is your pullup resistor? You may need to reduce its value. 4k or 5k is rea
Microcontrollers :: 10-12-2016 15:20 :: BradtheRad :: Replies: 2 :: Views: 401
Subharmonic oscillation cannot happen at small signal. It is a large signal phenomenon which appears in peak current mode, mainly when the duty-cycle is greater than 50%.
Definitely this is not our case.
Just reduce the number of turns of the inductor and you will get the right fundamental frequency.
RF, Microwave, Antennas and Optics :: 10-07-2016 06:23 :: vfone :: Replies: 22 :: Views: 1358
I am trying to synthesize AES encryption algorithm in vivado which was uploaded on open cores as shown in the link below
When I synthesize it, i get the following errors
IO Placement failed due to overutilization. This design contains 258 I/O po
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-06-2016 08:49 :: Sunayana Chakradhar :: Replies: 8 :: Views: 661
i found a graphical LCD driver chip, NT7538 i.e. ( other LCD controllers have same mode too)
in the datasheet, about "standby mode" is written:
Stops the operation of the duty LCD displays system and turns on only the static drive system to reduce current consumption to the minimum level required for st
Professional Hardware and Electronics Design :: 10-06-2016 08:53 :: hm_fa_da :: Replies: 2 :: Views: 454
Your attachment does not work so we do not know the function of the circuit.
The AD8610A low noise opamp has a typical open loop gain of 250 at 100kHz. Is it needed to reduce 100kHz distortion? It costs 2.8 times more than an OPA134 audio opamp that also has low noise and has an open loop gain of 100 at 100kHz where its distortion will be about 0.
Analog Circuit Design :: 10-04-2016 21:38 :: Audioguru :: Replies: 9 :: Views: 640
What about you reduce delay times by a factor of 1:50 for example? The above routine is doing absolutely nothing for 1.4 seconds (even w/o accounting debounce time), and writing in 6 memory locations in perhaps no more than a hundred millisecond. The whole funcion at all is masking the read of the Button() exectution for a long period.
Microcontrollers :: 09-28-2016 17:13 :: andre_teprom :: Replies: 13 :: Views: 564
i want to simulate 2 layer pcb and calculate s parameters. this 2 layer pcb have complex structure . in cst micro wave studio with frequency domain solver its have too long time for simulating and not appropriate . can any one help me to reduce thats needed time for simulation ?
RF, Microwave, Antennas and Optics :: 09-28-2016 12:06 :: amir_rch :: Replies: 0 :: Views: 392
Realistically you're never going to see hold violations for that situation where the source and destination flip-flip (and therefore clock) are the same. Hold time violations would be far more common for inputs coming from a different (and therefore potentially skewed) synchronous clock (an async clock may of course create hold violations but won't
ASIC Design Methodologies and Tools (Digital) :: 09-20-2016 03:05 :: asdf44 :: Replies: 10 :: Views: 715
I was looking for an optimized way to synth and implement multiple runs in parallel if possible ?
The design is huge with 90% utilization, so it takes 5 hours to synthesize and 11 hours to implement.
What are the ways to reduce these run times ( I cannot modify the rtl codes, I know there are combinatorial loops )
Also How can I
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-15-2016 07:27 :: UltraGreen :: Replies: 11 :: Views: 394
The aim is to prevent the battery going over 14.4V, and to prevent 'gassing' (bubbling electrolyte). Battery voltage is elevated during a charge. Afterward it takes several hours to settle down to its resting voltage, 12.8 V.
A taper charge is optimum. Start to reduce charge rate when battery reads 13.5V. reduce steadily until final voltage is 14.
Microcontrollers :: 09-12-2016 15:40 :: BradtheRad :: Replies: 2 :: Views: 583
First stage output/second stage input node is high impedance, too.
Diode connected? I don't see a diode connected MOSFET. The compensation network will of course reduce the OTA output impedance, as well as the input impedance of the second stage.
Analog Circuit Design :: 09-11-2016 17:57 :: FvM :: Replies: 2 :: Views: 418
You can do these to reduce the simulation time...
a) Minimum no of passes
b) Uncheck the save fields
c) In Frequency sweep step size should not be very small
d) Frequency sweep range to be kept as required range
Electromagnetic Design and Simulation :: 09-06-2016 16:47 :: sree479 :: Replies: 6 :: Views: 763
You did not mention so far for what kind of application all the 6 motors will be used, but if there is the need of real time geometric calculations to be done by the uC ( eg not synchronized steps, but interspersed at non-integer rates ), the use of delays will ruin the operation - or at the best case, will dramatically reduce the maximum speed of
Microcontrollers :: 09-06-2016 16:35 :: andre_teprom :: Replies: 11 :: Views: 518
In normal operation, there's no need for a series resistor. To calculate a resistor that protects the opto triac under all conditions, including load short, apply ohms law. R = 250V/0.07A = 3600 ohm.
Unfortunately, the series resistor would reduce the load voltage in normal operation to 70% (assuming a resistive load) and must be rated w
Power Electronics :: 09-06-2016 07:29 :: FvM :: Replies: 6 :: Views: 331
MNA-MAT, a MATLAB based analog circuit simulation tool, uses Modified Nodal Analysis to reduce a SPICE netlist to a system of equations which yield voltage at and current through specific points in the network. Monte Carlo analysis adds further functionality by evaluating possible uncertainties in real-world working conditions.
Business, Promotions, Advertising :: 09-02-2016 14:15 :: nik1106 :: Replies: 0 :: Views: 663
Hi. I want to regulate a 45VDC unregulated power supply down to 300mA at ~12V. I was going to use a LM7812 until another member pointed out they have a max Vin of 35V. My plan was to use the circuit shown on the
Elementary Electronic Questions :: 09-01-2016 07:02 :: JohnJohn20 :: Replies: 7 :: Views: 549
Due to skin effect of 0.6 um, most of the current flows on the edge, so will it be a good idea to assume sheet metal to reduce simulation time drastically? I've simulated several single-patch antennas and I didn't see a big change but if I try to simulate full-sized antenna with thick metal, ADS creates over 100,000 elements and my computer literal
Electromagnetic Design and Simulation :: 09-01-2016 18:43 :: usx :: Replies: 1 :: Views: 329
Two or more frames to animate means that your simulation time is very small or the probe setting you are using has very big step. This may be the reason you can check this by increasing the simulation time or if you are using any probe then reduce the time step.
I never got this error with HFSS but I am optimistic that by making one or both mention
Electromagnetic Design and Simulation :: 08-31-2016 07:14 :: nomigoraya :: Replies: 11 :: Views: 618
I am trying to simulate an OpAmp comparator circuit. Simulation is taking long time to simulate because of small step size. How can i run simulation faster? How can i reduce step size for faster simulation? I already tried option in transient analysis for TIME STEP PARAMETERS but it is not working. Plz Suggest some solution.
ASIC Design Methodologies and Tools (Digital) :: 08-26-2016 06:52 :: akt007 :: Replies: 3 :: Views: 438
In my design, I am having some congestion after post route stage. What are the different methods I can use to reduce the congestion without going back to the previous stages?
ASIC Design Methodologies and Tools (Digital) :: 08-17-2016 10:41 :: biju4u90 :: Replies: 2 :: Views: 371
Hi. I have a 12V PSU which I want to reduce to 4V 2A PSU. I have used a NPN power transistor (BD137) plus a 270Ω resistor and a 5V zener to make a regulator which gives me a 4.4V output which is still too high.
Is it a good idea for me to just put a silicon rectifier of some sort in series with the regulator output to give me a further 0.6V
Power Electronics :: 08-15-2016 06:56 :: JohnJohn20 :: Replies: 7 :: Views: 331
Are you sure these motors are actual synchronous motors and not plain ordinary induction motors ?
Usually synchronous motors are only fitted to things that must run at a very constant fixed speed, such as clocks and timers.
Fans and compressors never use synchronous motors.
The problem with slowing single phase induction motors is that they nev
Show your DIY :: 08-14-2016 21:31 :: Warpspeed :: Replies: 13 :: Views: 2188
You would have to route the source clock from the pad to the center of the chip, and that is not desirable.
Think about the net delay.
If you can place your design near the PLL and that would reduce clock net delay significantly.
Whereas if your PLL is somewhere at the center of the chip, and say you place your logic also at the
ASIC Design Methodologies and Tools (Digital) :: 08-12-2016 08:17 :: dpaul :: Replies: 3 :: Views: 392
Using EET I derived the following symbolic expression
C1*C2*C3*R1* (R2 //R3//RL)
I know that the expression reduces to this
C1*C2*C3*R1*R2 (RL //R3)
I don't know where to begin to reduce my expression to get the final answer. Can anyone help me? Are they identities to apply? Please point me to any reference material t
Elementary Electronic Questions :: 08-05-2016 13:15 :: Souljah44 :: Replies: 1 :: Views: 290
Triacs, including the small opto-triac inside the MOC3020 can turn on if the voltage across then rises suddenly, this makes them prone to triggering when interference spikes arrive along the AC lines. The 0.05uF capacitor and 470 Ohm resistor are there to limit the rise time of any voltage step or voltage pulse to prevent that happening.
Power Electronics :: 08-03-2016 21:47 :: betwixt :: Replies: 8 :: Views: 1188
In order to improve our prototype, quick-turn, small-medium size manufacturing lead time, and also help to reduce our company's manufacturing cost, a more than 4,000,000 RMB cost of laser direct imaging (LDI) equipment has been introduced recent successfully, and it's under in-house operating right now.
When this LDI passed our trial period suc
Business, Promotions, Advertising :: 08-03-2016 06:59 :: darrenyang20085 :: Replies: 0 :: Views: 43
I don't understand the problem.
It's a high side current sensor using differential Hall sensors to reduce stray magnetic effects with a single supply for unipolar DC current using a ratiometric supply reference added to the output to avoid the converted signal inside being near ground.
It is digitally compensated for linearity and tempco.
Analog Circuit Design :: 07-29-2016 23:09 :: SunnySkyguy :: Replies: 27 :: Views: 1459
Can you make a 50mV current shunt and scope current symmetry? especially harmonic content.
Saturation will reduce inductance, increase di/dt for the same voltage and be asymmetrical if there is remenance.
50mV/20A=2.5mΩ, a short pc. of wire calibrated.
using shielded twisted pair of magnet wire on the neutral side to a diff Amp with a
Power Electronics :: 07-28-2016 21:09 :: SunnySkyguy :: Replies: 8 :: Views: 471
Without switching regulator:
* reduce input voltage
* reduce current consumption
I see no other way.
Noise of switchin regulators:
In a handheld measurement device I have a step down switcher...
50mm away on the same PCB I have a 16 bit ADC running with 10kSamples/s and an anlog bandwidth of about 3kHz.
The input signals i
Analog Circuit Design :: 07-26-2016 10:09 :: KlausST :: Replies: 6 :: Views: 329
For 1kV with fan cooling and dust accumulation creepage or leakage discharges with high voltage can reduce from 3kv/mm on a surface to 300V/mm or worse. Therefore for longevity they prefer air gaps between HVAC and LVDC using air slotted gaps.
But you have HVDC which requires more care.
HOw much of the board will have 1kV distributed around it?
Power Electronics :: 07-23-2016 20:51 :: SunnySkyguy :: Replies: 2 :: Views: 274
A 40khz squarewave has harmonics at 80kHz, 120kHz, 160kHz and many higher multiples. An RC lowpass filter can be made with one series resistor then a capacitor to ground and it can reduce the harmonics a little but the filtered waveform will not yet be a sinewave unless many RC filters like that are used, but then since the circuit has nothing acti
Elementary Electronic Questions :: 07-22-2016 03:51 :: Audioguru :: Replies: 7 :: Views: 564
Basically, increasing the capacitor value reduces the output DC voltage ripple.
But than input AC current (rms and peak) and current through DC capacitors increases. To reduce this inductor is use.
From simulation point of view there is no difference whether I put same value inductor on AC or DC side (equal rms curren
Power Electronics :: 07-21-2016 09:25 :: mike buba :: Replies: 10 :: Views: 805
I tried to synthesize a 64-bit adder. It's pure combinational. When I set the virtual clk to 1GHz. The timing report is
clock vclk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
output external delay -0.10 0.90
data required time
ASIC Design Methodologies and Tools (Digital) :: 07-19-2016 15:44 :: ammmmlol :: Replies: 9 :: Views: 1187
hi, thank you.
i used 10uf just to see max current can flow. all of the graph looks like that 130682
i am trying to reduce rise time to increase current from 3A to 3,5A (values are just sample). it needs 100 ns to rise from 3 to 3,5A, i am trying to make it between 10-20 ns.
Analog Circuit Design :: 07-12-2016 14:43 :: deniz88 :: Replies: 7 :: Views: 418
HFSS is notorious for needing lot's of computer resources. In some cases you may be able to reduce the detail in your model. Usually that is not the case. Symmetry planes may help a bit but you probably want a bigger computer. RAM is your friend. So are more cores.
Electromagnetic Design and Simulation :: 07-11-2016 22:19 :: Azulykit :: Replies: 4 :: Views: 578
I have a nrf24L01 module acting as a transmitter and multiple other nRF's acting as receivers. And every receiver has to receive data from Tx. How can synchronization be done between 1 Tx and multiple Rx's so as to reduce Nrf's power consumption.
Any help is much appreciated.
RF, Microwave, Antennas and Optics :: 06-27-2016 08:02 :: Raman_Sharma :: Replies: 1 :: Views: 364
To get max power out of the device, you will have to excite it with an AC wave of 140V peak to peak (see post #2) at 40kHz. The output power has not been specified. It may be wise to reduce the max voltage by about 20% to leave some headroom. That will reduce the output power but that will depend on the nature of the coupling.
RF, Microwave, Antennas and Optics :: 07-08-2016 17:51 :: c_mitra :: Replies: 2 :: Views: 299
Most likely you have a large common mode noise interfering with a differential current source, sense.
Try a large CM balun or ferrite sleeve or twin coupled choke to the twisted pair to raise CM impedance and thus CMRR but keep DM impedance relatively low compared to Zc(f)
If that fails, reduce area of loop with a smaller gap . water has a diele
Hobby Circuits and Small Projects Problems :: 07-08-2016 02:35 :: SunnySkyguy :: Replies: 3 :: Views: 373
I do not have much knowledge regarding RF PCB design so my queries would be very basic:sad:
I have a 433MHz RF module on PCB, its RFM69W by HOPERF. PCB that I am using is a 1.6mm 4 layer board. PCB stack up is TOP signal layer, ground plane, power plane, Bottom Signal layer.
I plan to have an 50 ohm SMA connector on PCB to connect whip antenna.
Electromagnetic Design and Simulation :: 07-04-2016 07:08 :: raghavani :: Replies: 5 :: Views: 519
If you have any explanation, Could you please provide me?
scan chain length is proportional to the number of flops in your design. the number of test vectors is proportional to how complex the logic between flops is. compression can reduce the number of test vectors, but it will not alter the design. so th
ASIC Design Methodologies and Tools (Digital) :: 07-04-2016 15:54 :: ThisIsNotSam :: Replies: 4 :: Views: 585
Almost any electret microphone will work up to around 50kHz. Knowles make a number that are characterised beyond the normal 10kHz. Just put a high pass filter after it to reduce lower frequency audio. An amplifier may be needed as well. You can then process the signal however you like.
Look up bat detectors to get plenty of ideas of what you could
Microcontrollers :: 07-01-2016 10:47 :: G4BCH :: Replies: 2 :: Views: 1721