1000 Threads found on edaboard.com: Reduce
NO you are driving a DC motor at less than 10% of it's rated voltage so there is little back EMF to reduce the current.
It is like driving a car from a stop light in 5th gear
Elementary Electronic Questions :: 11-04-2016 03:16 :: SunnySkyguy :: Replies: 14 :: Views: 920
Changing RTL is always the easiest option.
Have you got register merging turned off? Than can help reduce the register fan outs.
All false paths and multi cycle paths specified?
Finally you can try overconstraining a single path using a set max delay, but this can often make it harder to route adjacent nets and is a rather tedious job.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-02-2016 07:35 :: TrickyDicky :: Replies: 2 :: Views: 454
Wanted to ask "How to choose voltage rating of SMD ceramic capacitors"?
It depends. AC or DC voltage load, low or high permittivity dielectricum. For the latter, you may reduce the voltage to 50 % of the rated voltage due to the capacitance drop versus applied voltage.
- - - Updated - - -
By reading manuf
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-30-2016 17:24 :: FvM :: Replies: 3 :: Views: 980
Assuming it's not, in fact, the B terminal?
Give us a picture, or something.
Could be a field plate to control the nasty low quality
oxide at the base surface, in which case tying to the
emitter (or most positive potential) could stiffen up the
surface concentration and reduce the injection of
"doomed" carriers (destined to recombine at that
Analog Circuit Design :: 10-29-2016 17:06 :: dick_freebird :: Replies: 3 :: Views: 567
The shown topology can be expected to generate even harmonics due to the asymmetrical current mirror RF input. Should try a standard Gilbert topology with a differential RF input. Or reduce the RF input level.
Analog Circuit Design :: 10-26-2016 05:01 :: FvM :: Replies: 3 :: Views: 602
You just need to reduce the current for a given W/L to enter subthreshold.
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-26-2016 13:52 :: deba_fire :: Replies: 4 :: Views: 621
Don't use thermal spokes for RF PCB (L1 ground pad).
I don't see an actual CPWG structure, rather a micro-strip with distant ground via fence, impedance is mostly that of the pure micro-strip. You could however taper the center line and reduce the ground separation towards the end.
Or leave everything as is and put some series inductance for
RF, Microwave, Antennas and Optics :: 10-13-2016 18:02 :: FvM :: Replies: 3 :: Views: 449
2GBps would likely require at a minimum 16-bit transfers using a parallel bus @ 125 MHz, I would probably go to 32-bit just to reduce that clock rate down to 62.5 MHz SDR or stay with 16-bit DDR. It might be better to use a transceiver based solution a single 2.5Gbps SERDES link would suffice. Your budget seems low, as most of the boards Xilinx and
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-12-2016 19:04 :: ads-ee :: Replies: 2 :: Views: 467
is it possible to drive EEPROM or some other chips like accelerometer and ... VCC directly through MCU IO ?!!
i'm thinking of it in order to reduce components count (not using on/off transistor for VCC of each chip) and also reducing power consumption in those chips less than even power down modes by cutting off VCC.
the max current co
Microcontrollers :: 10-12-2016 15:38 :: hm_fa_da :: Replies: 2 :: Views: 544
Your hand is probably radiating ambient 50/60 Hz mains hum. Our bodies pick it up like an antenna, from all around in the room. A sensitive input pin (or mosfet gate, or transistor bias pin) easily responds to it, if the pin is unconnected and allowed to 'float'.
What value is your pullup resistor? You may need to reduce its value. 4k or 5k is rea
Microcontrollers :: 10-12-2016 15:20 :: BradtheRad :: Replies: 2 :: Views: 555
Subharmonic oscillation cannot happen at small signal. It is a large signal phenomenon which appears in peak current mode, mainly when the duty-cycle is greater than 50%.
Definitely this is not our case.
Just reduce the number of turns of the inductor and you will get the right fundamental frequency.
RF, Microwave, Antennas and Optics :: 10-07-2016 06:23 :: vfone :: Replies: 22 :: Views: 1739
Without going into the design details (AES encryption details)...
What can be done is already mentioned in simple English #1 to #3.
If you cannot use a larger device (#1) then go to #3.
I am assuming you have specified the correct no. of top-level ports (#2), else re-check.
If #1 is not feasible then #3 is your only option. reduce the encr
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-06-2016 09:02 :: dpaul :: Replies: 8 :: Views: 900
i found a graphical LCD driver chip, NT7538 i.e. ( other LCD controllers have same mode too)
in the datasheet, about "standby mode" is written:
Stops the operation of the duty LCD displays system and turns on only the static drive system to reduce current consumption to the minimum level required for st
Professional Hardware and Electronics Design :: 10-06-2016 08:53 :: hm_fa_da :: Replies: 2 :: Views: 523
Your attachment does not work so we do not know the function of the circuit.
The AD8610A low noise opamp has a typical open loop gain of 250 at 100kHz. Is it needed to reduce 100kHz distortion? It costs 2.8 times more than an OPA134 audio opamp that also has low noise and has an open loop gain of 100 at 100kHz where its distortion will be about 0.
Analog Circuit Design :: 10-04-2016 21:38 :: Audioguru :: Replies: 9 :: Views: 727
What about you reduce delay times by a factor of 1:50 for example? The above routine is doing absolutely nothing for 1.4 seconds (even w/o accounting debounce time), and writing in 6 memory locations in perhaps no more than a hundred millisecond. The whole funcion at all is masking the read of the Button() exectution for a long period.
Microcontrollers :: 09-28-2016 17:13 :: andre_teprom :: Replies: 13 :: Views: 776
i want to simulate 2 layer pcb and calculate s parameters. this 2 layer pcb have complex structure . in cst micro wave studio with frequency domain solver its have too long time for simulating and not appropriate . can any one help me to reduce thats needed time for simulation ?
RF, Microwave, Antennas and Optics :: 09-28-2016 12:06 :: amir_rch :: Replies: 0 :: Views: 522
If I am having set up violations in this situation, how can I fix it?
As a front-end logic design engineer I insert re-timing flops on the path, if the design allowa it (try to do an operation in two clock cycles instead of one). The newly inserted flop will reduce the long path.
ASIC Design Methodologies and Tools (Digital) :: 09-20-2016 07:31 :: dpaul :: Replies: 10 :: Views: 854
What are the ways to reduce these run times ( I cannot modify the rtl codes, I know there are combinatorial loops )
Already answered in #1
Also How can I efficiently utilize the time while its getting implementing. Anything which I can do in parallel to get results of multiple optimization techniques symultaniously or at leas
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-15-2016 07:55 :: dpaul :: Replies: 11 :: Views: 448
The aim is to prevent the battery going over 14.4V, and to prevent 'gassing' (bubbling electrolyte). Battery voltage is elevated during a charge. Afterward it takes several hours to settle down to its resting voltage, 12.8 V.
A taper charge is optimum. Start to reduce charge rate when battery reads 13.5V. reduce steadily until final voltage is 14.
Microcontrollers :: 09-12-2016 15:40 :: BradtheRad :: Replies: 2 :: Views: 694
First stage output/second stage input node is high impedance, too.
Diode connected? I don't see a diode connected MOSFET. The compensation network will of course reduce the OTA output impedance, as well as the input impedance of the second stage.
Analog Circuit Design :: 09-11-2016 17:57 :: FvM :: Replies: 2 :: Views: 513
I will suggest to work in the following way to reduce the simulation time
1. Define relatively thin mesh as mesh directly affects both the simulation time and accuracy so you can make a good bargain.
2. Try to reduce the maximum number of passes that will reduce the simulation time but again at the expense of accuracy but most of time (...)
Electromagnetic Design and Simulation :: 09-07-2016 14:41 :: nomigoraya :: Replies: 6 :: Views: 915
You did not mention so far for what kind of application all the 6 motors will be used, but if there is the need of real time geometric calculations to be done by the uC ( eg not synchronized steps, but interspersed at non-integer rates ), the use of delays will ruin the operation - or at the best case, will dramatically reduce the maximum speed of
Microcontrollers :: 09-06-2016 16:35 :: andre_teprom :: Replies: 11 :: Views: 647
In normal operation, there's no need for a series resistor. To calculate a resistor that protects the opto triac under all conditions, including load short, apply ohms law. R = 250V/0.07A = 3600 ohm.
Unfortunately, the series resistor would reduce the load voltage in normal operation to 70% (assuming a resistive load) and must be rated w
Power Electronics :: 09-06-2016 07:29 :: FvM :: Replies: 6 :: Views: 493
MNA-MAT, a MATLAB based analog circuit simulation tool, uses Modified Nodal Analysis to reduce a SPICE netlist to a system of equations which yield voltage at and current through specific points in the network. Monte Carlo analysis adds further functionality by evaluating possible uncertainties in real-world working conditions.
Business, Promotions, Advertising :: 09-02-2016 14:15 :: nik1106 :: Replies: 0 :: Views: 883
Hi. I want to regulate a 45VDC unregulated power supply down to 300mA at ~12V. I was going to use a LM7812 until another member pointed out they have a max Vin of 35V. My plan was to use the circuit shown on the
Elementary Electronic Questions :: 09-01-2016 07:02 :: JohnJohn20 :: Replies: 7 :: Views: 622
Due to skin effect of 0.6 um, most of the current flows on the edge, so will it be a good idea to assume sheet metal to reduce simulation time drastically? I've simulated several single-patch antennas and I didn't see a big change but if I try to simulate full-sized antenna with thick metal, ADS creates over 100,000 elements and my computer literal
Electromagnetic Design and Simulation :: 09-01-2016 18:43 :: usx :: Replies: 1 :: Views: 401
Two or more frames to animate means that your simulation time is very small or the probe setting you are using has very big step. This may be the reason you can check this by increasing the simulation time or if you are using any probe then reduce the time step.
I never got this error with HFSS but I am optimistic that by making one or both mention
Electromagnetic Design and Simulation :: 08-31-2016 07:14 :: nomigoraya :: Replies: 11 :: Views: 745
How can i reduce step size for faster simulation?Analysis time step is determined by "reltol", "relref", etc. parameters in Cadence Spectre.
I already tried option in transient analysis for TIME STEP PARAMETERS but it is not working.You can not control analysis time step even if you set
ASIC Design Methodologies and Tools (Digital) :: 08-27-2016 09:57 :: pancho_hideboo :: Replies: 3 :: Views: 563
In my design, I am having some congestion after post route stage. What are the different methods I can use to reduce the congestion without going back to the previous stages?
ASIC Design Methodologies and Tools (Digital) :: 08-17-2016 10:41 :: biju4u90 :: Replies: 2 :: Views: 445
Hi. I have a 12V PSU which I want to reduce to 4V 2A PSU. I have used a NPN power transistor (BD137) plus a 270Ω resistor and a 5V zener to make a regulator which gives me a 4.4V output which is still too high.
Is it a good idea for me to just put a silicon rectifier of some sort in series with the regulator output to give me a further 0.6V
Power Electronics :: 08-15-2016 06:56 :: JohnJohn20 :: Replies: 7 :: Views: 370
this would end up saturating core with large currents due to any DC content if not symmetrical.
INterleaving cycles also cuts starting torque by duty cycle.
VFD's use low ESR active switches to drive the motors with PWM half bridges to make pseudo sine waves to reduce Eddy current losses.Then 3 phase gives smooth torque at wide speed ranges.
Show your DIY :: 08-14-2016 21:57 :: SunnySkyguy :: Replies: 13 :: Views: 2491
You would have to route the source clock from the pad to the center of the chip, and that is not desirable.
Think about the net delay.
If you can place your design near the PLL and that would reduce clock net delay significantly.
Whereas if your PLL is somewhere at the center of the chip, and say you place your logic also at the
ASIC Design Methodologies and Tools (Digital) :: 08-12-2016 08:17 :: dpaul :: Replies: 3 :: Views: 476
Using EET I derived the following symbolic expression
C1*C2*C3*R1* (R2 //R3//RL)
I know that the expression reduces to this
C1*C2*C3*R1*R2 (RL //R3)
I don't know where to begin to reduce my expression to get the final answer. Can anyone help me? Are they identities to apply? Please point me to any reference material t
Elementary Electronic Questions :: 08-05-2016 13:15 :: Souljah44 :: Replies: 1 :: Views: 330
There is a mathematical solution, if you are interested , by computing impedance of LEDs and caps.
Also LEDs would benefit with a diode bridge after the triac to give DC instead of half wave rectified by LEDs to reduce flicker when on.
LIght dimmers often flicker on LED lamps not designed for this and need a small tungsten night light or load
Power Electronics :: 08-05-2016 01:01 :: SunnySkyguy :: Replies: 8 :: Views: 1705
In order to improve our prototype, quick-turn, small-medium size manufacturing lead time, and also help to reduce our company's manufacturing cost, a more than 4,000,000 RMB cost of laser direct imaging (LDI) equipment has been introduced recent successfully, and it's under in-house operating right now.
When this LDI passed our trial period suc
Business, Promotions, Advertising :: 08-03-2016 06:59 :: darrenyang20085 :: Replies: 0 :: Views: 43
I don't understand the problem.
It's a high side current sensor using differential Hall sensors to reduce stray magnetic effects with a single supply for unipolar DC current using a ratiometric supply reference added to the output to avoid the converted signal inside being near ground.
It is digitally compensated for linearity and tempco.
Analog Circuit Design :: 07-29-2016 23:09 :: SunnySkyguy :: Replies: 27 :: Views: 1864
Can you make a 50mV current shunt and scope current symmetry? especially harmonic content.
Saturation will reduce inductance, increase di/dt for the same voltage and be asymmetrical if there is remenance.
50mV/20A=2.5mΩ, a short pc. of wire calibrated.
using shielded twisted pair of magnet wire on the neutral side to a diff Amp with a
Power Electronics :: 07-28-2016 21:09 :: SunnySkyguy :: Replies: 8 :: Views: 565
It is easy to reduce noise say on 50mV SMPS ripple using LC filter to desired level combined with PSRR on chip.
CM and DM ferrite beads can also reduce ingress on high impedance inputs, if the layout causes crosstalk.
I have used SMPS for video amplifiers and AMLCD bias without noise effects, but with care.
In this case I stepped down 9V to 5V
Analog Circuit Design :: 07-26-2016 11:16 :: SunnySkyguy :: Replies: 6 :: Views: 410
For 1kV with fan cooling and dust accumulation creepage or leakage discharges with high voltage can reduce from 3kv/mm on a surface to 300V/mm or worse. Therefore for longevity they prefer air gaps between HVAC and LVDC using air slotted gaps.
But you have HVDC which requires more care.
HOw much of the board will have 1kV distributed around it?
Power Electronics :: 07-23-2016 20:51 :: SunnySkyguy :: Replies: 2 :: Views: 326
A 40khz squarewave has harmonics at 80kHz, 120kHz, 160kHz and many higher multiples. An RC lowpass filter can be made with one series resistor then a capacitor to ground and it can reduce the harmonics a little but the filtered waveform will not yet be a sinewave unless many RC filters like that are used, but then since the circuit has nothing acti
Elementary Electronic Questions :: 07-22-2016 03:51 :: Audioguru :: Replies: 7 :: Views: 840
With an inductor on the input side you will reduce the input ripple current, but lower the (loaded) capacitor voltage.
With an inductor at the output side you may influence the voltage to the load in a way that the load will refuse to work. (depends on load). But you won´t decrease input ripple current significantly.
Power Electronics :: 07-21-2016 15:09 :: FvM :: Replies: 10 :: Views: 1371
I tried to synthesize a 64-bit adder. It's pure combinational. When I set the virtual clk to 1GHz. The timing report is
clock vclk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
output external delay -0.10 0.90
data required time
ASIC Design Methodologies and Tools (Digital) :: 07-19-2016 15:44 :: ammmmlol :: Replies: 9 :: Views: 1704
Simple 1st effects are:
from Ic=CΔv/Δt or
Δt = CΔv / Ic
thus for Δt = 100 ns, C= 10 uF , let ΔV = 1 V, Ic= 100 Amps.. Is that what you used?
Also Consider ESR of 10 uF will have ultra low ESR*C product of 0.1 us best case and more likely 1us. Which do you have?
So to reduce Δt, now you can see the 1
Analog Circuit Design :: 07-12-2016 22:33 :: SunnySkyguy :: Replies: 7 :: Views: 511
HFSS is notorious for needing lot's of computer resources. In some cases you may be able to reduce the detail in your model. Usually that is not the case. Symmetry planes may help a bit but you probably want a bigger computer. RAM is your friend. So are more cores.
Electromagnetic Design and Simulation :: 07-11-2016 22:19 :: Azulykit :: Replies: 4 :: Views: 686
Is it between one TX and multiple RX or multiple TX and one RX. Which power are you referring to? Rf power?
The datasheet reference manual has the details on how power can be reduce through operation mode.
RF, Microwave, Antennas and Optics :: 07-09-2016 11:04 :: ahmed-agt :: Replies: 1 :: Views: 455
To get max power out of the device, you will have to excite it with an AC wave of 140V peak to peak (see post #2) at 40kHz. The output power has not been specified. It may be wise to reduce the max voltage by about 20% to leave some headroom. That will reduce the output power but that will depend on the nature of the coupling.
RF, Microwave, Antennas and Optics :: 07-08-2016 17:51 :: c_mitra :: Replies: 2 :: Views: 371
Most likely you have a large common mode noise interfering with a differential current source, sense.
Try a large CM balun or ferrite sleeve or twin coupled choke to the twisted pair to raise CM impedance and thus CMRR but keep DM impedance relatively low compared to Zc(f)
If that fails, reduce area of loop with a smaller gap . water has a diele
Hobby Circuits and Small Projects Problems :: 07-08-2016 02:35 :: SunnySkyguy :: Replies: 3 :: Views: 463
You'll notice that transmission lines of given impedance can be easily scaled in dimensions. If you have already a correct calculation for one substrate height you also know the results for others.
If you are stuck to a thick substrate you might consider coplanar scrips with to ground to reduce the trace width.
Electromagnetic Design and Simulation :: 07-04-2016 12:17 :: FvM :: Replies: 5 :: Views: 646
If you have any explanation, Could you please provide me?
scan chain length is proportional to the number of flops in your design. the number of test vectors is proportional to how complex the logic between flops is. compression can reduce the number of test vectors, but it will not alter the design. so th
ASIC Design Methodologies and Tools (Digital) :: 07-04-2016 15:54 :: ThisIsNotSam :: Replies: 4 :: Views: 669
Almost any electret microphone will work up to around 50kHz. Knowles make a number that are characterised beyond the normal 10kHz. Just put a high pass filter after it to reduce lower frequency audio. An amplifier may be needed as well. You can then process the signal however you like.
Look up bat detectors to get plenty of ideas of what you could
Microcontrollers :: 07-01-2016 10:47 :: G4BCH :: Replies: 2 :: Views: 2610