1000 Threads found on edaboard.com: Reduce
Can someone explain how IR drop increases with scaling?
It doesn't: Both width and length of interconnections reduce with scaling (height only minimally), so at constant current (s. below) IR drop stays essentially the same with scaling.
Also, since the volatge is scaled, s
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-01-2016 16:53 :: erikl :: Replies: 2 :: Views: 378
To reduce crosstalk track space to width ratio 3x is suggested here, but this assumes a ground plane.
50 ohm tracks are approx equal to dielectric thickness and approx. match CMOS driver impedance on most but not all LV logic.
PCB Routing Schematic Layout software and Simulation :: 01-28-2016 05:32 :: SunnySkyguy :: Replies: 6 :: Views: 735
The battery datasheet shows a load current of 100uA makes its life only 10,000 hours. You must reduce the load current to only 50uA for a battery life of 20,000 hours. If you cannot reduce the current then the battery is too small.
Analog Circuit Design :: 01-27-2016 13:40 :: Audioguru :: Replies: 4 :: Views: 446
How can we identify 2(or more) power gated domains have same power characteristic?
This is to reduce the number of power gated domain in a partition.
Please help me out here. Thank you
ASIC Design Methodologies and Tools (Digital) :: 01-22-2016 03:40 :: no_mad :: Replies: 1 :: Views: 492
Red LEDs are the ones which brings the smallest drop voltages, being perhaps the suited color.
Although alkaline batteries exhibit a smooth discharge profile over time, it sounds not a good idea to use a LED too close of the minimal drop voltage due to the fact that the smallest change in its characteristic would dramatically reduce the its bri
Hobby Circuits and Small Projects Problems :: 01-21-2016 12:43 :: andre_teprom :: Replies: 2 :: Views: 340
The problem with a diode may be an overvoltage condition with very low load, as well as significantly larger drop (loss of regulation) on maximum load.
The really elegant solution would be to use a low-dropout regulator ("LDO") to reduce the voltage from 5v to 4.2V. However, the "5V" is not always 5V, as tehre will be some load-dependent drop in
Analog Circuit Design :: 01-17-2016 20:03 :: ted :: Replies: 25 :: Views: 1997
Have you checked resistive directional couplers? There is an example at
However, its insertion loss is high. Hence, you should reduce the coupling below 30 dB..
RF, Microwave, Antennas and Optics :: 01-13-2016 09:24 :: metu :: Replies: 8 :: Views: 612
I have already designed and fabricated a 3D conical antenna working at GSM frequency bands (Height = 15 cm). Now in order to reduce the size of the antenna (Height cm in particular), I need to design or shape the cone in the form of Waves (sinusiod or meander in 3D). I would like to know how can I achieve this wavy structure
RF, Microwave, Antennas and Optics :: 01-13-2016 07:25 :: kela3kela :: Replies: 0 :: Views: 334
I can only answer it at a very top- (concept-) level.
In order to reduce the negative slack, try to reduce the combinational logic between two the two registers (flip-flops). Or adding a pipeline can also be a solution.
If your design is big, try out 'incremental compilation' to achieve timing closure for a particular partition that does not
ASIC Design Methodologies and Tools (Digital) :: 01-11-2016 09:52 :: dpaul :: Replies: 9 :: Views: 1355
I have doubt will something like this work?
Can MCU AT89S51 source current approx 20mA to drive the displays?
In fact, a resistor of 560R would limit the maximum current for something near to 8mA. I suspect that the intrinsic 51's inner pullup resistors would also reduce the current a few more. You could add some
Microcontrollers :: 01-07-2016 00:14 :: andre_teprom :: Replies: 15 :: Views: 946
reduce supply voltage to min and test for margin at speed with your design.
Avoid metastable or race conditions use synch clock for critical timing.
Poor design choices can obviously reduce speed integrity issues.
Raising voltage 5~10% can make marginal designs sometimes room temp or colder.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-06-2016 18:56 :: SunnySkyguy :: Replies: 3 :: Views: 495
"Reverse short channel effect" is now a thing. Used to be
that VT would reduce w/ L due to short channel effects,
drain field summing w/ gate field. But modern technolgies
are not much like what you are shown in school for a
classical MOSFET - multiple implants (halo, LDD) and
these are tuned for the bleeding edge leaving the long
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-04-2016 18:01 :: dick_freebird :: Replies: 2 :: Views: 667
1) Use resistors as a voltage divider to reduce the 500V to 100 V down to 10V to 20V.
2) Use an opamp to add an offset voltage of -10V to the voltages divided then the 10V becomes 0V and the 20V becomes 10V.
Analog Circuit Design :: 01-04-2016 15:05 :: Audioguru :: Replies: 3 :: Views: 395
This is basically an auto-transformer with 2 relays to choose 3 input taps and 1 relay to select either of 2 taps to give - 6 combinations of voltage ratios ,
- 4 combinations to boost,
- 1 combo to reduce line voltage
- 1 combo on 1:1 (240V tap)
- 1 relay just enables the output
you figure out the
Power Electronics :: 01-04-2016 04:40 :: SunnySkyguy :: Replies: 5 :: Views: 1115
Should I change the 2,5k Trimmer on the mic circuit? When I turn the speaker-unit to max it starts scratching, so I lowered the 42k to 22k. But is there another way to fix that problem?
The first circuit board you posted has an LM380 power amplifier fed from Pot M-10k which is its volume control. Simply turn down the
Analog Circuit Design :: 01-05-2016 14:29 :: Audioguru :: Replies: 38 :: Views: 2233
Provided you can connect the PIC VSS to the neutral wire it's easy, just use resistive voltage dividers to reduce the phase wires to within PIC VDD and clamp the signal so it can not go negative or higher han VDD (use a zener diode). Each phase will then see a logic signal of almost half one cycle. Pick one as the reference (zero time) and start a
Microcontrollers :: 01-02-2016 17:18 :: betwixt :: Replies: 7 :: Views: 545
I think this option has more potential if you reduce the coupling capacitors and apply more damping.
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Measurements on a breadboard test circuit also look promising.
Trace one is the primary drive signal and lower trace measured on the gate of main FET.
Power Electronics :: 12-31-2015 21:58 :: E-design :: Replies: 33 :: Views: 2418
I'm quite new to the subject of these tubes. I've made some basic models but when it gets to the point of creating a port I see that reflections from the input port seem excess to me.
For example an incident amplitude of 1 in port signals view has a value of 0.4 for O1,1 which I guess is pretty much.
I've tried changing port sizes, of c
Electromagnetic Design and Simulation :: 12-29-2015 14:50 :: rapidcare :: Replies: 3 :: Views: 484
How to reduce the height of a monopole antenna without using any lumped elements??
Electromagnetic Design and Simulation :: 12-21-2015 15:41 :: akhilpaulv :: Replies: 4 :: Views: 433
SDA and SCL waveforms look like you have too high pull-up resistor values. To allow checking of signal timing, you should capture SDA and SCL with two oscilloscope channels.
You should also reduce the image size of the screenshots before posting.
Microcontrollers :: 12-28-2015 14:57 :: FvM :: Replies: 24 :: Views: 1435
1) reduce total design mesh density. you can reduce in steps until simulator successfully complete the simulation.
2) reduce mesh density of particular section of the design. if you feel particular piece of the conductor not significantly affecting the design parameters, you can reduce the mesh density in that area.
Electromagnetic Design and Simulation :: 12-25-2015 07:02 :: pragash :: Replies: 1 :: Views: 362
In case of doubt, a H-bridge is the straightforward way to implement a peltier power supply. It's presumed that you have sufficient L or LC filtering to reduce the peltier current ripple to a level where it doesn't cause significant efficiency loss.
Nonlinear peltier characteristic is a point to consider. It can be either compensated in the cont
Microcontrollers :: 12-24-2015 22:37 :: FvM :: Replies: 9 :: Views: 2301
Inserting an additional low pass into the feedback loop will reduce the phase margin to about zero and might even cause oscillations. If you feel a need to compensate the voltage drop, there must be a forward AC path bypassing the filter. In case of doubt check the loop stability in a simulation.
Analog Circuit Design :: 12-22-2015 13:07 :: FvM :: Replies: 1 :: Views: 382
To fix the setup violation, one need to reduce the data path delay. So as you only suggested that it could be done through either up-sizing the cell or adding the buffer. Adding the buffer will need extra space as well as routing resources where as up-sizing the buffer will have advantage in terms of area. Adding the buffer will ONLY help if the t
ASIC Design Methodologies and Tools (Digital) :: 12-21-2015 04:45 :: navin_2cool :: Replies: 1 :: Views: 518
As all inductive loads, the motor causes contact arcing. You can reduce, but not completely avoid it by placing an RC snubber across the relay contact, e.g. 47 ohm + 100 nF. The capacitor must be rated for 250 VAC.
Power Electronics :: 12-17-2015 10:43 :: FvM :: Replies: 4 :: Views: 526
reduce the no.of passes
Electromagnetic Design and Simulation :: 12-21-2015 15:48 :: akhilpaulv :: Replies: 3 :: Views: 521
Equipment having heatsink designs based on passive heat conduction have their performance strongly enhanced by external forced ventilation. There are available on hot regions of the world cheap cooling stands designed with 2 fans which blows a continuous air flowing upwardly, and are able to reduce a bit the overall temperature. The only issue is w
General Computer :: 12-15-2015 18:22 :: andre_teprom :: Replies: 10 :: Views: 1205
The difference between TC and TC_int is that a 1'bz state in TC will get converted to 1'bx. It would make a difference if these signals were used in a casez() statement, but only if they could have been assigned the 1'bz value.
The comparator is written this way to reduce X pessimism by doing the comparison bit by bit. The === operator is only dif
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-14-2015 21:21 :: dave_59 :: Replies: 3 :: Views: 479
have you got a galvanic insulation for your AC signal ?
Any link with the MAin AC power ( ground, earth,neutral)
Maybe your AOP can oscille at H.F., because high speep AOP.
you can reduce the Frequency band width
C accross feeback
Microcontrollers :: 12-14-2015 10:47 :: paulfjujo :: Replies: 13 :: Views: 543
The cap value should not be so small that its charge loses more than a few percent during the idle half of the cycle. However if you need to reduce output voltage, it is possible to do this by reducing cap values.
A gang of small capacitors in parallel, may be better than one large capacitor, to carry large Ampere burdens.
Elementary Electronic Questions :: 12-09-2015 03:29 :: BradtheRad :: Replies: 3 :: Views: 528
reduce the 1k resistor to around 270 Ohm. That should give you near the 20mA you need through the LEDs for full brightness.
Microcontrollers :: 11-30-2015 17:14 :: E-design :: Replies: 4 :: Views: 506
hi thanks for that. what is the limitation on number of metal tracks? why cant we reduce less than 7 tracks? how do we fix them this many number of tracks should be there? i mean supporting calculation of tracks and their widths.
ASIC Design Methodologies and Tools (Digital) :: 11-30-2015 07:38 :: tejaNSRP :: Replies: 0 :: Views: 315
Capacitive loads often give rise to problems, in part because they can reduce the output bandwidth and slew rate, but mainly because the phase lag they produce in the op amp’s feedback loop can cause instability. Although some capacitive loading is inevitable, amplifiers are often subjected to sufficient capacitive loading to cause
RF, Microwave, Antennas and Optics :: 11-30-2015 05:59 :: picachu :: Replies: 5 :: Views: 579
The zener diodes produce distortion and the simple two RC filters will not reduce the distortion much.
Elementary Electronic Questions :: 11-25-2015 22:25 :: Audioguru :: Replies: 2 :: Views: 525
Two Options are there.
1. reduce the Higher layer metal area, which means change it to different track.
2. Add the reverse-bias diode at the gate.
ASIC Design Methodologies and Tools (Digital) :: 11-21-2015 17:14 :: kumar_eee :: Replies: 2 :: Views: 965
Consider that these "intelligent switches" are performing slow switching to reduce EMI, so pwm frequencies should be moderate, e.g. a few 100 Hz up to 1 kHz. And there should be a freewheeling means for inductive loads.
Power Electronics :: 11-15-2015 14:31 :: FvM :: Replies: 1 :: Views: 331
its weird problem you facing. what is the frequency step size you using for ADS simulation? reduce the step size to get more data points so the results will match your CST.
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to verify the cause of disappearance of two resonance frequency, 1st simulate the imported to
RF, Microwave, Antennas and Optics :: 11-13-2015 19:54 :: pragash :: Replies: 8 :: Views: 798
The rated Phase Margin is ΦM=60 Degrees @ CL = 20 pF for 220pF the graph shows 40 deg PM
YOu have RC 16k5 and 2.2uF which probably reduces the PM near 0.
COnsider 1st Opamp with non-inverting gain of ~4 and eliminate 2nd Op AMp to improve phase margin then reduce C8 and double R9
The reason is the CMOS output Z is 5V/7mA (shorted cct) = 0.7
Analog Circuit Design :: 11-12-2015 07:08 :: SunnySkyguy :: Replies: 8 :: Views: 506
I am working on ADC SAR, and focus on ENOB, therefore how to increase ENOB and reduce Power consumption.123033
Elementary Electronic Questions :: 11-10-2015 02:10 :: Murod Kurbaniv :: Replies: 0 :: Views: 500
If you plan 50 Hz frequency, then a 4H primary inductance is reasonable. That is the default value when I place a power transformer in the simulator (Falstad's).
However as post #2 states, you can make the frequency faster, allowing you to reduce certain parameters for the transformer.
Power Electronics :: 11-09-2015 17:49 :: BradtheRad :: Replies: 4 :: Views: 475
I bet no one tells you of the distortion of the CT output due to the magnetising current
It´s not too rare to see many CT somewhat oversized to the power consumed by the load resistence. Should we assume that it is done to reduce the effect of the remansescent magnetism ?
Elementary Electronic Questions :: 10-26-2015 17:05 :: andre_teprom :: Replies: 14 :: Views: 1056
You can use a 2 layer board with interleaved ground signals or guarding methods with ground planes, but as in TV tuners, you may need to fabricate a tin-plated brass lid (or purchase) to reduce E field crosstalk and rectification of RF onto input protection diode, causing modulated DC bias or added noise to high impedance inputs.
PCB Routing Schematic Layout software and Simulation :: 10-26-2015 16:16 :: SunnySkyguy :: Replies: 7 :: Views: 711
i cant understand.Neither we can't understand your problem because you didn't give any useful information about your antenna design.
But you could try to reduce all antenna dimensions by 10 percent....
RF, Microwave, Antennas and Optics :: 10-12-2015 07:28 :: FvM :: Replies: 4 :: Views: 569
pouring power planes is just about making current loops narrower in area, and thUs less radiative, and less susceptible to pick up interfering better for EMC.
IT MAY ALSO reduce I^2R losses. (sorry about caps)
Power Electronics :: 10-09-2015 05:04 :: treez :: Replies: 2 :: Views: 446
Sensing mains voltage can be of course done with an optocoupler and is often done this way. Use sensitive optocouplers to reduce the series resistor power dissipation to an acceptable amount.
Hobby Circuits and Small Projects Problems :: 05-09-2015 22:43 :: FvM :: Replies: 9 :: Views: 1658
I have been working on my ANC project. For this I have two microphone inputs and one loud speaker output, but initially I am using single microphone and dspStreamingPassthrough to pass microphone input to loud speaker. Here is my code
numIterations = 500;
% Construct sources (for all inputs)
src1 = dsp.AudioRecor
Digital Signal Processing :: 10-07-2015 11:31 :: charanbandi :: Replies: 1 :: Views: 1018
I think they mean XC not XL.
There isn't much you can do about that, the leakage is the normal operation of the capacitor, making it's value smaller or increasing the resistor value will reduce the leakage but also reduce the effectiveness as a snubber network.
What you might be able to do is provide an alternative path for the leakage current to
Analog Circuit Design :: 10-07-2015 09:20 :: betwixt :: Replies: 6 :: Views: 718
These filters are so simple that they does not do much for audio except to gradually reduce low frequencies and high frequencies. If you connect in series a lowpass and a highpass then the very simple resulting bandpass filter has poor performance.
Hobby Circuits and Small Projects Problems :: 10-06-2015 23:32 :: Audioguru :: Replies: 13 :: Views: 701
R9 is a load on the sensor output.
R8/C16 are a low pass filter to reduce fast variation in the measured voltage (= average it over a period) so it gives a more constant reading.
The pin on the IC will be an analog input to read the voltage.
Microcontrollers :: 10-06-2015 10:11 :: betwixt :: Replies: 1 :: Views: 357
You do not make the output resistance "more bigger" (higher). Instead for more gain you make the negative feedback resistance higher.
An opamp has a frequency compensation capacitor to reduce the gain at high frequencies so that its phase shift does not cause oscillation when negative feedback is applied then at high gain the bandwid
Analog Circuit Design :: 10-03-2015 13:42 :: Audioguru :: Replies: 1 :: Views: 379