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There are several ways to do this: 1. you can use a simple divider circuit but it limits you to exact integer ratios. 2. you can use a pulse swallowing circuit that passes some pulses through and blocks others. This has the disadvantage that the output pulses are not at a constant rate. 3. you can use a pulse swallowing divider that alternates it'
Hello Everyone... I have made antenna and tuning network which can detect MiFare and HiD iClass cards. i.e. 13.56Mhz... So for that i need to control unwanted harmonics of 13.56Mhz... I have designed antenna tuning circuit as per MiFare suggest. Card detection range in around 4 cm. So how can I reduce effect of harmonics??? And what is the s
It seems that this "large via hole" is designed for minimum path length to ground. The only way to reduce RF inductance is to keep the path as short as possible, so it would make sense. Using many vias at different distances is quite useless because vias with a longer path have almost no effect on total inductance at RF frequencies.
Depends on what's "high frequency" for you. CRGO (cold rolled grain oriented steel) is preferable below 10 kHz, it's usage may be reasonable in some cases at 10 or 15 kHz. Respectively low sheet/tape thickness (e.g. 0.1 mm) required to reduce eddy currents.
The datasheet for the INA149 shows that its inputs can survive 500V(!) for 10 seconds and operate normally with a common mode voltage as high as plus or minus 275V if its supply voltage is plus and minus 15V. It has a gain of 1 and it is used to show a small signal on high differential voltages. It is stable. You cannot reduce its gain.
There are several XMOS devices at Element 14, which do you have? Probably for one of these two reasons: 1. internally, one alone may not be able to carry all the current demand of the product. 2. using parallel grounds reduces the impedance between internal parts and the external grounds. This may help to reduce noise and unwanted signal transiti
Isolated devices are the devices which have their substrates isolated from the rest of the circuit. This comes in handy usually when you need to use S-B connection in NMOS devices, but if you use this as a design methodology you can significantly reduce the substrate noise coupling from whatever digital circuit you have on the outside. Some process
ferrite beads tend to be low Q and used more to reduce radiated noise transients or RF noise. Better way is to use 100 Ohm CAT5 type transmission lines from 50~100 Ohm CMOS LOGIC ( e.g. ALVC types) and termination R @ V/2 or equivalent Thevenin circuit with Pullup/dn if you want best speed and noise immunity. THen use large CM choke around cable
you can check the quality factor of the coil after extraction and compare before extraction , it seems that the quality factor of the coil drops significantly after extraction , why Q factor will reduce the output amplitude?
The problem with small spindle motors is poor bearing vibration and "runout" or wobble. The trick is to find a dummy spindle motor with a 0.5 or 0.75" shaft and cascade this spindle driven by the smaller motor to reduce the runout.
hi i have designed mixer using current bleeding. in this method we are decreasing current through LO stage to decrease noise by directly injecting current in to RF stage , but this will also reduce current of load resistor than how gain increases because gain = 2/Pi (gm.RL) please explain anybody have idea about it
Is there any EDA vender's simulator product can support parallel simulation of pure VHDL design ? Must take use of multicore CPU resource to reduce simulation time. Must supported by modern CPUs, not just limited by one old CPU family. Does the simulator need mannually partition or automatically ? I have read Synopsys's VCS LCA release
In some cases the purpose is to prevent static buildup. Or it may be to reduce mains hum and/or EM noise.
Hello, I am new to HSPICE simulations and might need a bit of your help. I have a simple 6T SRAM cell and I would like to reduce its supply voltage VDD for a short period of time (a voltage source). I expect the cell node Q and QB to flip after pulling the voltage supply to zero or at least to react accordingly, however they do not. What is wro
Frank, it works !!!! :grin: Thanks very much, but I have to dissipate large amount of power, about 15 mW, for delivering 1 mW power to the resistor. PAE will be very bad! Fortunately the dissipation from the source has reduced by a large amount. I can still reduce the dissipation through the source by adding small signal ampli
I am doing my research on Video Processing, When there two camera which has overlapped Field of view correlation methods is used to compress or send the video in a manner which reduce redundancy. I Don't know where to start and I need basics knowledge to be learned,From where I need to start? and is the research in this area is valuable? Pl
Solid State Relays (SSR) have integrated zero crossing and that significantly reduces the spikes. Some SSR include snubbers and some don't.
Hi Everyone, is it a common practice placing an LC filter at the INPUT of a non-isolated buck converter to reduce reflected noise? does LC filter add any problem? Regards, Ballimo
In Cellular communications this is named DTX (Discontinuous Transmission). This option is used to reduce interference into the cell and reduce power consumption of the transmitters. DTX can be implemented in ANY wireless system.
There has to be a resistor in series to each LED. The value can be 220R up to 2.2K. The resistor determines the current through the LED. without the resistor the LED can be damaged or the 5V supply overloaded and voltage collapses. You can start with 2.2K and if the LED is too dim reduce the resistance.
The inductor should be a value that does not restrict 50 Hz at the current level you desire. A larger Henry value restricts (chokes) current. This may be a handy method to reduce a high output voltage. To help you calculate a ballpark figure you can use the formula for inductive impedance: XL = 2 Pi F L The capacitor is necessary for power facto
Placing ground vias all over the PCB (stiching) to improve the EMI. Have all ground vias to be spaced the same distance? Or may they be separated different distances if it is under lambda/8? I mean, I have to place ground vias all over the PCB edge to reduce EMI. The space between these ground vias are below lambda/20, aroun
To achieve 0.3 mm trace width for 50 ohms on FR4, the substrate height must be about 180 ?m. Is it so? More usually, the feasible line width is far below that required for 50 ohms. So it's unavoidable to reduce tracks near a QFN pin. Consider that the bond wire inside the IC package neither continuous 50 ohms impedance. Traces shorter than &#
The area it dictated purely by function. If the 4/4 design requires all 4 inputs or outputs, then removing one will reduce some of the function and therefore area. The tool will not change the function of the circuit, unless the code is designed that way. So I dont really understand your question.
That means doing alteration in code !! Can you be little more specific :| Did you try going by the advice KlauST gave to you? I think your success lies in it. reduce the primary(previously Secondary) windings of your xformer or you get a transformer with 230ACV to 8ACV but i will advice you increase you voltage to
Hello users, I have an ofdm based modulation and would like to reduce its peak to average without generating spectral regrowth. Does clipping work at I&Qs ? People came up with a bunch of PAR reduction techniques for OFDM so I guess this is more complicated than just clipping the base band data. thanks
Using larger ( by maintaning W/L ratio) will reduce the larger MOS area has less mismatch..
In the old days of predicting BER with margin testing for high speed clock and data separators, we used many different tools to measure window margin. But often one of the most useful tools was to inject random jitter into the system to reduce phase margin but still be error free with minimal margin to see if any environmental stress would produce
You can also add a snubber circuit near to each switching device. This will reduce the peak current flowing inside during opening period. Another possibility, but it's kind of hard to evaluate without a notion either of the waveform or the board layout, is that the transistor base is receiving induced noise, which could cause undesired DC drivi
Maybe adjust gate resistor values on the switching power device? Increase value to reduce switching rise time. This will reduce radiated harmonics.
I am about to design a simple control board for an industrial equipment. To reduce the amount of cabling, the customer asks to have the earth connection on the PCB - along with live and neutral. If I remember correctly, there is a safety restriction which forbids having live+neutral+earth on the PCB. You can have live + neutral, provided you respe
The problem specification isn't very clear. Do you want a low (0.1%) modulation according to the input signal offset? Or reduce the offset to get maximal modulation depth?
The thick film resistor can dissipate 30W when its temperature is at its max of 150 degrees C or less and you cool its case to 25 degrees C somehow (liquid nitrogen?). If you mount it on a heatsink in an air conditioned room then of course the heatsink will get warm or hot so you must reduce the power.
Apply feedback ( series or series+parallel) to reduce the Gain and improve the will also improve the stability...
1. Any length is ok, both TX and RX as long as it fulfills your needed system functionality. λ/4 is a practical length due to its impedance is reasonable easy to match against common types of TX & RX impedances. Shorter monopole antenna then λ/4 will reduce antenna efficiency and radiation resistance will be lower, causing reflection loss
Your schematic had wires running around in circles (Multisim?). I fixed it. Why did you reduce the collector resistor value of Q2 to be so low?
Recently i made some calculations on series fed patch arrays using array factor, etc.. But also it is interesting that using different tapered feeding lines it is possible to reduce side lobes. It is all about how much power will go to the patch. Most sources refer to some coefficient = 1/2, 2/3, 3/4,
Hi , how to reduce high logic levels (present in datapath blocks) duirng synthesis using design compiler through better optimization ? I need proper attrbutes / any other way which can be used during synthesis so that logic level can be reduced .
You'll have to reduce the clearance, which can be found under Design => Rules => Electrical => Clearance. You can specify a clearance smaller than the general board clearance using InComponent('U1'). The white parallel lines indicate that the trace is unrouted, and will disappear automatically when you're routing the board.
115846 I do not know if I must put an Rc in the Q2 Sure, otherwise you would short the power supply by Q2. P.S. What's the purpose of R1? That will reduce the accuracy (feedback gain) of the circuit. Right, but I think it's intended to limit the p
hi raj, I'm not an expert on it, but I have somethings to share. - trans violations might come from big load as the previous pin drive. - to fix it, I think you need to use a stronger cell (of course you have to trade off timing/power/...) or break number of fanout (to reduce load) I have specified the max_trans value. But still i am get
`Hai every one, Can any one help me to reduce the noise with PCB for RE103 and CE102 tests. I don't have a much time to change my design and going for another new PCB. And i want to know whether it is possible to reduce the noise with out altering the design. Thanking you
I think to achieve GHz frequency you will have to reduce the gm/Id value (i.e. --> moderate inversion mode), which means reducing the transistor W/L ratio or increasing the drain current. S. the following (general) GBW (fT) vs. gm/Id plot: 115844
Hi Everyone, Just wanted to ask experienced antenna engineers, what is the expected sidelobe level, as i've designed a 4-patch antenna array with 10.5dB realised gain, but sidelobe levels of 2.5dB. Do you think this is acceptable at 12-13 GHz frequency? If not, can you suggest some ways to reduce the sidelobe level in array
Hello everyone, I'm having trouble reducing the spur in my subharmoniclly injection-locked ring oscillator. From literature I understood that reference spur can be reduced by ensuring that, F_ro = N*F_inj, where N is the frequency multiplication factor. I set up a ring oscillator in cadence and manually inject a pulse into it. I made my best tu
Feedback can only reduce the output voltage by decreasing the duty cycle. Looks like wrong transformer design or excessive ouput stage voltage drop.
I know voltage isn't amperage, but I have either a 12v or 5v source to choose from. This will be feeding a varying solenoid. The position I'd like it in will require 850 milliamps(say the instructions.) Since this isn't a simple voltage reduction I was wondering if you guys had any input. It would be even better if I could vary the amperage, just i
Decreasing the height of the substrate reduce the radiation loses but make the microstrip line thinner, with higher ohmic loss. Increasing the height of the substrate, the fringing fields from the edges increase, make the effective length of the line longer, and the input impedance of the line become slightly more inductive.
Try to keep the characteristic resonant circuit impedance √L/C Instead of reducing L only, reduce L and C by the same factor.
Probably you have not enough memory to solve your model. You can try to decrease the mesh ratio or use symmetries to reduce your model size.