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Any papers about this issue: high supply voltage but low voltage input diff pair is used in order to reduce size and to improve the matching issue. Thanks.
What are the different techniques to reduce gate delays and combinational logic circuit delays? I am aware of adding buffers to reduce circuit delays and sizing by the method of logical effort to reduce gate delays. What are the other techniques used by designers in the industry?
This is simple unencripted eeprom with SPI interface. You can use TL866 to read and write it. If SO8->DIP8 adapter have to be used, read it once and verify multiple times to be sure, that it is connected properly. For writing it is the same. And don't tell anyone that you are planing to reduce mileage of your car before sell it.
My question is why there is a need in darlington transistors to create these h-bridges? ..................................... if yes why darlington allow to switch high currents?To reduce input current. Ibase=Icollector/Beta. So if Icollector is large, Ibase is also large. Darlington makes Beta large. [QUO
If the chip was flip chip, but I want to further reduce the parasitic inductance. Any method I can do? Or the foundry has some method to reduce the inductance? Thanks.
Hello everyone, I need to know the difference between noise floor level and the spurs level of the system. I know the basic definition of these terms. Lets say if i want to reduce the spur level below -60dbc,than what will be the level of noise floor at this spur it possible to relate these two terms. Thanks
Just opening the PCB solder allow to reduce the calculated width of copper track required for that routing.
What you can do is wind your primary and secondary on separate sections of a split section bobbin, to reduce capacitance between them.
I think multi-band. Because of mobile phones (2sim gsm+cdma+gps+bluetooth). maybe. But more recent papers focus on beam steering, something like wifi wich alters beam direction to point in your phone/notebok/pad. To reduce interference, focus power, increase speed.
Dear all, I'm designing a patch antenna array with series feed network and I want to reduce the beamwidth but I don't know how to do that. Its beamwidth now is 26.9 degrees and I want it at 20 degrees. Please help me, any suggestion will be appreciate. Thank you
Guidelines for op amps state that input V should not exceed supply rails. A resistive divider might be sufficient to reduce your 0-10V input range down to a suitable level.
for a gear ratio of 1:8 , with o/p speed limited to 200rpm , the input speed will be 25 rpm. also , if the motor torque is 0.8Nm(holding) , will it not reduce the torque in the o/p for 1:8 ratio gearbox?
Hi, I have controlled the fan speed by TRIAC,I can regulate the ceiling fan step by step with phase angle control method.but i got little bit of noise from how can i regulate the fan speed smoothly without noise. I have attached my circuit diagram and waveform. Using a triac changes the waveform
To change frequency you have to change timebase for timer2. To change amplitude you have to shift PWM value to some bits right for example to reduce duty cycle for 2, 4, 8 and e.t.c. times.
The L21 & C23 forms a post filter to reduce ripple / noise on the output this is typical in flyback designs & very difficult to compensate most of the times, refer attached PDF for detailed analysis
128029 ... 128030 Sorry, your attachments expired for unknown reasons. It may help if you were to reduce the dimensions of your diagrams.
Hi, I am trying to design a capacitor bank for VCO. The thing is the MOSFET switches give a considerable OFF cap when they are OFF because of which I am seeing a reducing the capacitor range in the bank. I would like to reduce this OFF capacitance of the MOSFET and I don't want to reduce the size further because this would increase the ON switch
I am running PSS on Cadence Virtuoso for a wide-range Quadrature VCO. I am facing convergence issues sometimes. Sometimes it works. Do you know the reason behind these convergence issues and how to reduce/solve those?Show me log file. Can your QVCO satisfy oscillation condition surely ? Did you confirm initial t
I wonder what's the purpose of the capacitors? Battery cells have already very low impedance. You'll large capacitors > 1 mF to reduce it further. I never saw similar capacitors in a real battery balancing circuit.
Hi, I found that my simulation runs faster when I put `celldefine macro in big RTL sub-block or simulation models. Now, says I use `celldefine macro in my RTL sub-block INSTANT_1: 1. I am assuming by using `celldefine macro, the simulation use less memory as it now treats INSTANT_1 as a cell, and does not keep the details inside INSTANT_1 . Is t
If the design is intended to comply with power quality regulations, it must not use phase control of electric heaters. Full wave switching has to be used to reduce harmonic currents. Review IEC 1000-3-2.
For those microwave frequencies, whatever resistors you use, to reduce the parasitic inductance a good option is to place 2 or 3 resistors in parallel (on top of each other). Doing this, always I got better frequency response at high frequencies.
It could be the high impedance wiring that makes it pick up ambient electrical noise (mains hum, EM, etc.). Tentatively you can reduce amplitude of such effects by reducing impedances in your schematic. Consider adjusting resistor values downward, yet still getting proper response. - - - Updated - - - Did yo
A loudspeaker has a strong resonance. It causes sounds to be "boomy". Therefore modern audio amplifiers use a fairly high open-loop voltage gain and a lot of negative feedback to reduce the gain to a useable amount, reduce distortion a lot, increase the bandwidth and reduce the output impedance a lot. The output impedance of a typical audio (...)
8X470 is much better than 4X1000; this will reduce ESR because they will be in parallel. In addition, they are not ideal capacitors and also dissipate some energy as heat. 8X470 will provide additional robustness against failure. It is not possible to eliminate ripple 100% under load using a simple capacitor. It is important to decide a priori h
Try to reduce the size of your model if you can by using some sort of symmetry plane or simplify your model by using solid via plate instead of a large number of vias. Default "Maximum Delta S" is 0.01 and normally I st it to 0.005 to get better accuracy. Also maximum delta Zo, has a role and I set it to 0.5%. Also, if your air box is excessively l
It could be that the coil's Q is not high enough. But your coil looks like its inductance should be much lower than the original. And any shorting between turns will drastically reduce the effective inductance.
Hi, I have S parameters with 8 pins(4 inputs and 4 outputs). I know in Hspice the .Lin command can reduce the unwanted pins. For example, I only want 2 pins. Does anyone know how to operate in Hspice? Thanks.
how ADE7758 chip knows what ct i am using, assume a ct with burdern resistor of x it produces 100mv / amp , if i reduce the burdern resistor to half of x then i will get 50mv/amp, how this information is fed to the ad7758 chip. how much mv/ amp i must give. is there any register for this. assume i am connecting 1 amps load i a phase if i read
This is a strange problem that I also have encountered few times. Other than the advice that Dr. Volker gave you on the above, try to reduce (yes, reduce!) the mesh. This worked for me for a 60 GHz power combiner.
Hello everyone, What are the preconditions in order to couple inductors in a switching converter? I have two inductors in my circuit and I want to couple them for saving space and reduce the weight. I know that "waveforms should be the same", but which waveforms? What about volt.seconds? Can anyone explain all the requirements?
Hi, For a planar structure, the MoM (ADS momentum) method is a good one. You gain in time because the matrix to solve is reduce. With FEM, you solve the problem in three dimensions the matrix is more complex. For 3D structure FEM is preferable. I already designed some filters with ADS momentum and the simulation was quite good and fast. Good work
Hi Guys, I am designing a high current BTL filter with a high impedance load, whereas in normal designs you would expect a low impedance of say 6ohm I am looking at an impedance level of 3333ohm. My issue is that to give the filter a decent Q the inductor would have to be massive in size say 150mH, I cannot use something that large because of si
hi, The Neo serial levels are 3.3V 'TTL' levels, you need a level shifter between this module and your PC. A MAX232 i/c would be suitable, also you need a resistive divider between the MAX232 RX out to the Neo RX input. The divider will reduce the 5V signal from the MAX to 3.3v for the Neo. Do you follow OK.? E
I use HFSS to simulate a bandpass filter with WIDE gaps between its coupled lines. These wide gaps made the simulation time very long and hard to converge. In fact, very small meshes are required to correctly solve the problem. Is it any trick to manage this problem? I heard about spare lines in gaps (these spare lines should be assigned vacu
or there is another way to do it? An immediate workaround to reduce the oven temperature deviation could be achieved by splitting the heating ellement into 2 parts or more, controlling them independently. This way you would be able to quickly rise the temperature at the beggining of the process heating both, but
i have managed to come so far, am I going in right direction ? Right - so far. I see that you already reduced the via size which is reasonable and helpful to fit the routing. A possible problem can be seen in the initial post's screenshot, cutting the ground plane with too small residual connections.
Edit: Ok. Here you go. I am attaching the mikroC PRO PIC project I made. You can't reduce the delays more. It took just 15 minutes to write this code.
Hi everybody, I need a circuit that avoid crow bar current at the driver 125738 Please suggest me circuit that can do such a thing, and it produce smallest propagation delay. Thanks
Hi Can someone explain how IR drop increases with scaling? Also, since the volatge is scaled, shouldnt the current reduce?
To reduce crosstalk track space to width ratio 3x is suggested here, but this assumes a ground plane. 50 ohm tracks are approx equal to dielectric thickness and approx. match CMOS driver impedance on most but not all LV logic.
The battery datasheet shows a load current of 100uA makes its life only 10,000 hours. You must reduce the load current to only 50uA for a battery life of 20,000 hours. If you cannot reduce the current then the battery is too small.
Hi, How can we identify 2(or more) power gated domains have same power characteristic? This is to reduce the number of power gated domain in a partition. Please help me out here. Thank you
Red LEDs are the ones which brings the smallest drop voltages, being perhaps the suited color. Although alkaline batteries exhibit a smooth discharge profile over time, it sounds not a good idea to use a LED too close of the minimal drop voltage due to the fact that the smallest change in its characteristic would dramatically reduce the its bri
The problem with a diode may be an overvoltage condition with very low load, as well as significantly larger drop (loss of regulation) on maximum load. The really elegant solution would be to use a low-dropout regulator ("LDO") to reduce the voltage from 5v to 4.2V. However, the "5V" is not always 5V, as tehre will be some load-dependent drop in
Have you checked resistive directional couplers? There is an example at However, its insertion loss is high. Hence, you should reduce the coupling below 30 dB..
Dear Members I have already designed and fabricated a 3D conical antenna working at GSM frequency bands (Height = 15 cm). Now in order to reduce the size of the antenna (Height cm in particular), I need to design or shape the cone in the form of Waves (sinusiod or meander in 3D). I would like to know how can I achieve this wavy structure
I can only answer it at a very top- (concept-) level. In order to reduce the negative slack, try to reduce the combinational logic between two the two registers (flip-flops). Or adding a pipeline can also be a solution. If your design is big, try out 'incremental compilation' to achieve timing closure for a particular partition that does not
I have doubt will something like this work? Can MCU AT89S51 source current approx 20mA to drive the displays? In fact, a resistor of 560R would limit the maximum current for something near to 8mA. I suspect that the intrinsic 51's inner pullup resistors would also reduce the current a few more. You could add some
reduce supply voltage to min and test for margin at speed with your design. Avoid metastable or race conditions use synch clock for critical timing. Poor design choices can obviously reduce speed integrity issues. Raising voltage 5~10% can make marginal designs sometimes room temp or colder.