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Anyone know about low power VLSI design using Variable Body Biasing Techniques to reduce static power consumption? Can someone discuss on it? the information i found on this is it correct?
Your simulation uses a pre run time to achieve steady state, you didn't mention this fact and hide the simulation command. Unfortunately the simulator chooses a larger automatic time step to reduce simulation time. Try with a maximum time step of 1ns or so.
It's not impossible to use a PTC for the intended purpose, but its parameters must be matched to coil current and activation time. The choosen type is simply unsuited, looking at the operation time curve in data sheet clarifies why. You should however consider that a suitable PTC protection device will also reduce the coil current by some amount
You cannot do it directly but you may reduce the input voltage of this regulator ( mV uV range ) to a reasonable level then the task is easier. It will consists of simple CV/CC adjustable regulator.Look at in order to find a proper element ..
pls .. I need some one help me by sent to me code in any method like genetic algorithm or any method to object reduce power loss in radial system .. the topic .. optimal placement and sizing distribution generation .. thanks .
I have seen something like this in the past, and it was due to noise getting back into the ramp generator. Its the same identical ramp that is supposed to drive both alternate cycles steered by a flip flop. A quick and dirty fix is to reduce the resistance of the timing resistor, and increase the value of the timing capacitor by the same amount
I want to train my support vector machine to classify human vs non human using matlab. In training phase am getting a large feature vector matrix around 1*335214 for a single human image. Is there a way to reduce the feature vector size or to select the location of human alone?
Hi everyone~ I've designed a fully differential op amp but my common-mode gain is large how could I change the parameter to decrease my ACM to -20dB at DC Thanks for the reply.. below is my hspice code .subckt op vdd vss vip vin vop von vcm clk M1 3 vip 1 vss n_18 W=20u L=1.5u m=
I want to run a 2HP AC (3 phase) 440V squirrel cage induction motor from Solar panel (600V, 100Watts panel) through a motor drive. I am using 3 Phase IGBT bridge to produce 3 phase output. For starting we are using V/F control. But as ambient light reduces Imp reduces since the load is constant it makes the input voltage to fall drastically and wh
1. 1 layer pri, then 1 layer sec, then 1 layer pri, then the final sec. or Leakage inductance will be reduce ? th of regular primary secondary winding but inter winding capacitance will be double. Wave form rigging will be very less 2. 2 secondary layers directly together sandwiched between the two single primary layers. Leakage inductance will
A variac is just the thing to slow pump speed, assuming it really would reduce noise. * Just as an experiment I would try putting a resistive load in series with the pump. Say, a space heater. Maybe a high W bulb (or a few low W in parallel). Enough resistance to drop the pump to 70 or 80 percent of normal power. See if noise level drops. * Noise
Hi, This is the reorderng algorithm use to order test patterns to reduce switching activity.can anyone help me to understand this algorithm. step 3 & 4 are confusing..... Reordering Algorithm The various parameters used in the algorithms are as follows: t, t, ? t be n test vectors with m bits each. 12n T={1,2,? k ? n} where k represent
Hi, I've got a very large and resonant structure and I'd like to reduce simulation time by using AR-Filter option in CST. This option needs to setup some parameters. Is there someone who can help me to setup this function please? Thank you very much for your support!
Hi all, could you please help me to find some ideas to reduce the ringing in Vivaldi antenna at center frequency 2 GHZ? Best regards
The leakage inductance example results in < 10 mW snubber losses and shouldn't involve design problems for a RCD circuit. The low Vds rating imposes a low switch duty cycle and tight snubber dimensioning and doesn't sound reasonable. Although C555 can drive MOSFET gate you'll probably want a dedicated driver to reduce switching losses. [COLOR="
Currently have a relay thats rated for 15 amps for a 5amp AC PSU power source (high capacitive inrush current). I have it wired so that its in the NC state, and when the relay is powered it cuts power to the PSU (reason I want it like this is if the relay control logic fails on boot/power on, the AC circuit will still be closed and providing power)
Hello friends, I try to figure out the best option to have adjustable load current for this charger 134680 I have a external device that may experience low temperatures for several days (-10 deg C or more). The battery is a special Li that can be charger from -10 normally and up to -30 deg with reduce rate of about 0.
If a differential mode is not considered, I'd prefer to use single varicap but lower cap. values.Because series connected varicaps wil have higher loss parasitics such as package bonding inductance, series resistances etc. so each parasitic will reduce the overall quality factor of the tank circuit.
Out of context I can't be sure but it looks like a circuit to delay the rise of the regulator output as the 3.3V line rises. C54 charging through R22 will cause a slight increase in voltage at the ADJ pin which in turn will trick it into thinking it has to reduce it's output voltage to maintain regulation. D1 will be to discharge C54 again when t
Most modern inverters are pretty efficient these days. So if you want 500W out you need to feed about 600W in. That will be just about 80% overall efficiency and perhaps you can do better than 80% but is does not harm being a bit conservative. As you yourself has estimated, a 12V battery will deliver 600W/12V or about 50A. That is a lot of current
Hi, I need to add a buffer stage to my OTA design to make it an op amp. My design will be in 28nm VDDnom=1V (but I increase to 1.2V). Until now, when I heard buffer I always thought about CD but I realized that a CS stage with unity gain can also be a buffer. Can someone give the advantages/disadvantages or provide a reference? I played ar
How to reduced the size of Wilkinson power divider?
6 LiPo cells in series will drop to about 3V each when discharging (18V) when they should be disconnected from the load. If you reduce the voltage 1V then the total voltage will drop to 17V. The wires on a Lipo battery are thick because a LiPo battery can produce many amps of current. Thin wires on a diode melt with a high current. A 1N4007 can blo
No sense to use optocouple if you are using same ground. No sense to use zener diode and e.t.c. Emitter goes to digital ground, collector directly to pin with pull-up resistor. Zener protection actual only on left side. Not even zener, TVS! And ceramic capacitor to reduce ESD.
If you built the Correct Circuit, using Pins 1 & 8 for gain, it would probably be better. And Anytime your Powering HEADPHONES from ANY POWER AMP, You should Include a 100 Ohm Series Resistor going to the Headphones. Both these Will reduce that Noise. The Resistor will protect the headphones from getting too much Power and protect your Ears from
Referring to you original question, a possible configuration to reduce errors by non-ideal core is a compensating feedback circuit that zeros the total flux.
Considering that the compiler that you are using could be already configured to optimize program memory usage ( usually to detriment of speed ), even on this case it is always possible to reduce the code size by better structuring the program, and it is achievable only depending on the inventiveness of the programmer to have creative insights, and
Is there a way to reduce congestion in a perticular CLB. If I have a report that says the top ten most congested CLBs are CLE_M_X74Y125 and CLEL_RX74Y125 ? what can I do with this information to reduce congestion in the design ?
Apart from following good layout techniques, are there any other methods?
Hi, I am trying to measure AC rms voltage using PIC microcontroller. I have attached the circuit for measurement. I am connecting a 3V step down transformer out to the input of the circuit.The feedback capacitor has been added to reduce the noise, but I am getting noise if I add this. This is getting smooth after the low pass filtering. Everyt
The LA7693x series is a single-chip video and sound processor IC with a built-in microcontroller that supports all of the different worldwide broadcasting systems. The IC provides fully integrated solution to rationalize the design of color TV sets, increase productivity, and reduce total costs.
133629 Is it ok to add a potentiometer parallel to constant current source(CL2 see attachment) and LED to reduce the LED intensity(see my schematic in attachment). or if i am going to use TLC5916 to drive 8 Parallel led 133633 and add parallel potentiometer to each LED to reduce the intensity manual
Read the discussion thoroughly. It's assumed that the primary inrush current is caused by missing current limiting means in the secondary, inserting a secondary inductor would reduce both. It's however still unclear if the post #1 schematic is meaned as forward converter or a flyback with flawed polarity mark.
Thanks you. The original input compensation network has one compensation stage. Now I change to two compensation stage, which greatly reduce the low frequency gain.
I don't understand two parts in my text book. "for a simple common source How can we reduce the input-referred noise voltage? Equation implies that the transconductance of M1 must be maximized. Thus, the transconductance must be maximized if the transistor is to amplify a voltage signal applied to its gate whereas it must be minimized if the tra
since an antenna is, by definition, an electrically large object, you can not do a lumped element analysis of it. WHY would you want to terminate an antenna anyway? that would reduce the transmitter efficiency you heat up your termination.
Can we transfer the source code written in C to Beaglebone in some efficient way ? Is there some way out to reduce the development timeline ? :thinker: Obviously all the I/O has to be mapped or some reworks can be expected.
The motive for posing this questions arises from a difference of analysis between a colleague and myself. Our general environment is in the construction of an analog front end which takes in signals to an instrumentation amp in the low microvolt range. followed by a gain stage, which then feeds a 24 bit delta sigma converter. My understanding
NO you are driving a DC motor at less than 10% of it's rated voltage so there is little back EMF to reduce the current. It is like driving a car from a stop light in 5th gear
Changing RTL is always the easiest option. Have you got register merging turned off? Than can help reduce the register fan outs. All false paths and multi cycle paths specified? Finally you can try overconstraining a single path using a set max delay, but this can often make it harder to route adjacent nets and is a rather tedious job. Why can't
Wanted to ask "How to choose voltage rating of SMD ceramic capacitors"? It depends. AC or DC voltage load, low or high permittivity dielectricum. For the latter, you may reduce the voltage to 50 % of the rated voltage due to the capacitance drop versus applied voltage. - - - Updated - - - By reading manuf
Assuming it's not, in fact, the B terminal? Give us a picture, or something. Could be a field plate to control the nasty low quality oxide at the base surface, in which case tying to the emitter (or most positive potential) could stiffen up the surface concentration and reduce the injection of "doomed" carriers (destined to recombine at that sur
The shown topology can be expected to generate even harmonics due to the asymmetrical current mirror RF input. Should try a standard Gilbert topology with a differential RF input. Or reduce the RF input level.
You just need to reduce the current for a given W/L to enter subthreshold.
Don't use thermal spokes for RF PCB (L1 ground pad). I don't see an actual CPWG structure, rather a micro-strip with distant ground via fence, impedance is mostly that of the pure micro-strip. You could however taper the center line and reduce the ground separation towards the end. Or leave everything as is and put some series inductance for
2GBps would likely require at a minimum 16-bit transfers using a parallel bus @ 125 MHz, I would probably go to 32-bit just to reduce that clock rate down to 62.5 MHz SDR or stay with 16-bit DDR. It might be better to use a transceiver based solution a single 2.5Gbps SERDES link would suffice. Your budget seems low, as most of the boards Xilinx and
Hi, is it possible to drive EEPROM or some other chips like accelerometer and ... VCC directly through MCU IO ?!! i'm thinking of it in order to reduce components count (not using on/off transistor for VCC of each chip) and also reducing power consumption in those chips less than even power down modes by cutting off VCC. the max current co
Your hand is probably radiating ambient 50/60 Hz mains hum. Our bodies pick it up like an antenna, from all around in the room. A sensitive input pin (or mosfet gate, or transistor bias pin) easily responds to it, if the pin is unconnected and allowed to 'float'. What value is your pullup resistor? You may need to reduce its value. 4k or 5k is rea
Subharmonic oscillation cannot happen at small signal. It is a large signal phenomenon which appears in peak current mode, mainly when the duty-cycle is greater than 50%. Definitely this is not our case. Just reduce the number of turns of the inductor and you will get the right fundamental frequency.
Hello All, I am trying to synthesize AES encryption algorithm in vivado which was uploaded on open cores as shown in the link below When I synthesize it, i get the following errors IO Placement failed due to overutilization. This design contains 258 I/O po