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Hi Sir, I have a nrf24L01 module acting as a transmitter and multiple other nRF's acting as receivers. And every receiver has to receive data from Tx. How can synchronization be done between 1 Tx and multiple Rx's so as to reduce Nrf's power consumption. Any help is much appreciated. Thanks
The Schottky diode forward voltage drop will reduce the voltage to the battery resulting in not full charging. The base resistor value is too high causing the transistor not to saturate since the datasheet shows it saturating well when its base current is 1/10th its collector current.
Hi, I tried with low value resistance, but no improvement. Your schematic is not clear. Is the resistor that powers it 2.2k ohms? Then a 330 ohm resistor as I showed reduces the mic sensitivity about 8 times which is -18dB. Maybe the input of the mic preamp already has a low resistor value? which Mic. is
If I use two cores for one inductor will its saturation current increase? What arrangement you want to do? To wind around these two cores stacked side-by-side? This would in fact reduce the electromagnetic flux over each core, but it seems a bit unusual?
Is making a helix in Maxwell the same as in HFSS? If so, when you make your initial figure to sweep, I select changing "Number of Segments" from 0 to something like 8 or 12. This will make the simulation more polygonal and run more efficiently. It sounds like you need to reduce curves in general. Although sweeping wit the helix tool will start to r
Hello, Does earthing reduce electricity bill ?
You do not need a precision rectifier for a 230VAC mains input, ordinary rectifiers work fine. An electronic VU meter has a low input signal of maybe 230mV to be rectified that will not turn on a diode so the extremely high voltage gain of an opamp is used to reduce the 0.6V forward voltage of a rectifying diode to almost nothing.
I did not tried slit method, but i can give you an idea on size reduction: Assume your patch size is W x H (width and height). 1) Try to move feeding line from center of patch to the left by distance approximate = W/4 2) Center frequency now be different. Do the simulation, find center frequency. 3) reduce patch height H until center frequency
Hello, please help I have a problem in terms of the slit method I had to prove that the slit method can reduce the size of patch antenna by 5 to 30%. As seen in the figure below. 129794 without slits 129795 with slits It looks like there is no change to the width of the patch antenna. I
Because dynamic current does flow through the gate to charge and discharge the gate capacitance when the MOSFET switches. So a low gate poly resistance will reduce the gate charge and discharge time, increasing the maximum operating switching speed of the transistor.
Hi, I'm currently working on a project that requires both 5V and 3V7 with a max current demand of about 2A - I'm wondering if it's acceptable to simply reduce the 5V by placing a diode inline to the 3V7 input? Perhaps there is a better way of doing this? I have tried an adjustable buck boost regultor but the noise seems to be causing me proble
Most modern portable microphones are the electret type ( look it up ion Google). They have a Jfet inside to reduce the extremely high impedance to a useable impedance and the Jfet is powered by a voltage from 1.5V to 5V at a current of about 0.5mA.
The normal flip chip bounding character impedance is 50ohm. Is there any way to reduce the character impedance? It seems that the wider the bounding the less character impedance is. Is there any material that has less area to achieve the low character impedance of the bounding? Thanks.
Any papers about this issue: high supply voltage but low voltage input diff pair is used in order to reduce size and to improve the matching issue. Thanks.
What are the different techniques to reduce gate delays and combinational logic circuit delays? I am aware of adding buffers to reduce circuit delays and sizing by the method of logical effort to reduce gate delays. What are the other techniques used by designers in the industry?
This is simple unencripted eeprom with SPI interface. You can use TL866 to read and write it. If SO8->DIP8 adapter have to be used, read it once and verify multiple times to be sure, that it is connected properly. For writing it is the same. And don't tell anyone that you are planing to reduce mileage of your car before sell it.
My question is why there is a need in darlington transistors to create these h-bridges? ..................................... if yes why darlington allow to switch high currents?To reduce input current. Ibase=Icollector/Beta. So if Icollector is large, Ibase is also large. Darlington makes Beta large. [QUO
If the chip was flip chip, but I want to further reduce the parasitic inductance. Any method I can do? Or the foundry has some method to reduce the inductance? Thanks.
Hello everyone, I need to know the difference between noise floor level and the spurs level of the system. I know the basic definition of these terms. Lets say if i want to reduce the spur level below -60dbc,than what will be the level of noise floor at this spur it possible to relate these two terms. Thanks
Just opening the PCB solder allow to reduce the calculated width of copper track required for that routing.
I think multi-band. Because of mobile phones (2sim gsm+cdma+gps+bluetooth). maybe. But more recent papers focus on beam steering, something like wifi wich alters beam direction to point in your phone/notebok/pad. To reduce interference, focus power, increase speed.
Dear all, I'm designing a patch antenna array with series feed network and I want to reduce the beamwidth but I don't know how to do that. Its beamwidth now is 26.9 degrees and I want it at 20 degrees. Please help me, any suggestion will be appreciate. Thank you
Guidelines for op amps state that input V should not exceed supply rails. A resistive divider might be sufficient to reduce your 0-10V input range down to a suitable level.
for a gear ratio of 1:8 , with o/p speed limited to 200rpm , the input speed will be 25 rpm. also , if the motor torque is 0.8Nm(holding) , will it not reduce the torque in the o/p for 1:8 ratio gearbox?
Usually the noise is generated by magnetostriction of the stator core. Low pass filtering can be expected to reduce it.
To change frequency you have to change timebase for timer2. To change amplitude you have to shift PWM value to some bits right for example to reduce duty cycle for 2, 4, 8 and e.t.c. times.
The L21 & C23 forms a post filter to reduce ripple / noise on the output this is typical in flyback designs & very difficult to compensate most of the times, refer attached PDF for detailed analysis
128029 ... 128030 Sorry, your attachments expired for unknown reasons. It may help if you were to reduce the dimensions of your diagrams.
Hi, I am trying to design a capacitor bank for VCO. The thing is the MOSFET switches give a considerable OFF cap when they are OFF because of which I am seeing a reducing the capacitor range in the bank. I would like to reduce this OFF capacitance of the MOSFET and I don't want to reduce the size further because this would increase the ON switch
I am running PSS on Cadence Virtuoso for a wide-range Quadrature VCO. I am facing convergence issues sometimes. Sometimes it works. Do you know the reason behind these convergence issues and how to reduce/solve those?Show me log file. Can your QVCO satisfy oscillation condition surely ? Did you confirm initial t
I wonder what's the purpose of the capacitors? Battery cells have already very low impedance. You'll large capacitors > 1 mF to reduce it further. I never saw similar capacitors in a real battery balancing circuit.
Hi, I found that my simulation runs faster when I put `celldefine macro in big RTL sub-block or simulation models. Now, says I use `celldefine macro in my RTL sub-block INSTANT_1: 1. I am assuming by using `celldefine macro, the simulation use less memory as it now treats INSTANT_1 as a cell, and does not keep the details inside INSTANT_1 . Is t
If the design is intended to comply with power quality regulations, it must not use phase control of electric heaters. Full wave switching has to be used to reduce harmonic currents. Review IEC 1000-3-2.
For those microwave frequencies, whatever resistors you use, to reduce the parasitic inductance a good option is to place 2 or 3 resistors in parallel (on top of each other). Doing this, always I got better frequency response at high frequencies.
It could be the high impedance wiring that makes it pick up ambient electrical noise (mains hum, EM, etc.). Tentatively you can reduce amplitude of such effects by reducing impedances in your schematic. Consider adjusting resistor values downward, yet still getting proper response. - - - Updated - - - Did yo
A loudspeaker has a strong resonance. It causes sounds to be "boomy". Therefore modern audio amplifiers use a fairly high open-loop voltage gain and a lot of negative feedback to reduce the gain to a useable amount, reduce distortion a lot, increase the bandwidth and reduce the output impedance a lot. The output impedance of a typical audio (...)
8X470 is much better than 4X1000; this will reduce ESR because they will be in parallel. In addition, they are not ideal capacitors and also dissipate some energy as heat. 8X470 will provide additional robustness against failure. It is not possible to eliminate ripple 100% under load using a simple capacitor. It is important to decide a priori h
Try to reduce the size of your model if you can by using some sort of symmetry plane or simplify your model by using solid via plate instead of a large number of vias. Default "Maximum Delta S" is 0.01 and normally I st it to 0.005 to get better accuracy. Also maximum delta Zo, has a role and I set it to 0.5%. Also, if your air box is excessively l
It could be that the coil's Q is not high enough. But your coil looks like its inductance should be much lower than the original. And any shorting between turns will drastically reduce the effective inductance.
Hi, I have S parameters with 8 pins(4 inputs and 4 outputs). I know in Hspice the .Lin command can reduce the unwanted pins. For example, I only want 2 pins. Does anyone know how to operate in Hspice? Thanks.
how ADE7758 chip knows what ct i am using, assume a ct with burdern resistor of x it produces 100mv / amp , if i reduce the burdern resistor to half of x then i will get 50mv/amp, how this information is fed to the ad7758 chip. how much mv/ amp i must give. is there any register for this. assume i am connecting 1 amps load i a phase if i read
This is a strange problem that I also have encountered few times. Other than the advice that Dr. Volker gave you on the above, try to reduce (yes, reduce!) the mesh. This worked for me for a 60 GHz power combiner.
Hello everyone, What are the preconditions in order to couple inductors in a switching converter? I have two inductors in my circuit and I want to couple them for saving space and reduce the weight. I know that "waveforms should be the same", but which waveforms? What about volt.seconds? Can anyone explain all the requirements?
Hi, For a planar structure, the MoM (ADS momentum) method is a good one. You gain in time because the matrix to solve is reduce. With FEM, you solve the problem in three dimensions the matrix is more complex. For 3D structure FEM is preferable. I already designed some filters with ADS momentum and the simulation was quite good and fast. Good work
A class-D power amplifier usually has an 8 ohm or 4 ohm speaker as its load. Your load resistance is so high that the LC filter is resonating and has almost nothing to reduce its Q.
hi, The Neo serial levels are 3.3V 'TTL' levels, you need a level shifter between this module and your PC. A MAX232 i/c would be suitable, also you need a resistive divider between the MAX232 RX out to the Neo RX input. The divider will reduce the 5V signal from the MAX to 3.3v for the Neo. Do you follow OK.? E
I use HFSS to simulate a bandpass filter with WIDE gaps between its coupled lines. These wide gaps made the simulation time very long and hard to converge. In fact, very small meshes are required to correctly solve the problem. Is it any trick to manage this problem? I heard about spare lines in gaps (these spare lines should be assigned vacu
or there is another way to do it? An immediate workaround to reduce the oven temperature deviation could be achieved by splitting the heating ellement into 2 parts or more, controlling them independently. This way you would be able to quickly rise the temperature at the beggining of the process heating both, but
Splitting a ground plane with via's anywhere is a bad idea The spreading of vias along the plane a priori should be appropriate to reduce long paths of ground among layers, which could make the board less sensitive to induced EMI.
Ok. Here you go. I am attaching the mikroC PRO PIC project I made. You can't reduce the delays more. You are using bit-banging SPI instead of the PIC hardware SPI. It's hardly possible to achieve a similar speed this way. I don't see how the designs in post #16 and #17 can be helpful.