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You do not make the output resistance "more bigger" (higher). Instead for more gain you make the negative feedback resistance higher. An opamp has a frequency compensation capacitor to reduce the gain at high frequencies so that its phase shift does not cause oscillation when negative feedback is applied then at high gain the bandwid
But the coil will have interwinding capacitance and a Self Resonant frequency, so you will care and what frequency you choose and what losses you have. Skin Effect losses increase with frequency. Ferrite core losses increase with frequency But coupling losses reduce with rising frequency where the gap must be < diameter and gap losses reduce with
Putting enough decaps on the node connected to the pad (internally to the chip) should help improve the PSRR. Maximum number of pads you can have depends on how many you want to allocate. Typically, I have seen 3-4 bond pads being tied together to reduce the inductance.
It means the difference frequency is being filtered out. If you use the XOR gate Type I mixer, the capture range is strongly affected by the BW so lag/lead C-RC filter is used. YOu can also use dual BW in the loop to change bandwidth from fast lock (high BW) to (low BW) in order to reduce jitter once locked on.
A ferrite bead won't do. You need real storage inductor to reduce the current ripple to something like 30 or at least 50 percent. Ends up with an inductance of about 1 mH for the given parameters.
emergency landing of the quadrotor in case of a failure of a propeller. You'll want the craft to descend slowly. To ensure this you either need to (a) install an altimeter, or (b) spin the propellers at an rpm which you determined (by previous experiments) is the proper speed so that 3 propellers will reduce altitude
I have initialize clock, GPIO, DMA and SPI setting according to STM32CubeMx setting... But don't show how. I'm not working specifically with STM32 DMA, in so far can't help in this regard. I would expect you have already done some things: - checked SPI operation with non-DMA HAL functions. Seeing it working would reduce the prob
gauravkothari23, I just want to back up what Audioguru is saying. I have used a lot of Li-ion cells, often without protection circuits, and they stll make me nervous after years of using them. Mis-charging a NiCd or NiMH, or even a lead-acid, is not very hazardous. Most likely you will just reduce the cell's life. Mis-charging, over-charging
use eg axial diode and coat it to reduce surface leakage...the internal leakage in the rev biased semiconductor is always more than any surface leakage, and dwarfs it into significance, as you know.
Are you sure the value you placed physically is correct ? I couldn't see why this could happen, anyway you could reduce the value a few, to something close to 15pF for instance.
Peak current is 12V/Rs , Rs=2.4Ohm , Ipk= 5A Consider low cost PC PSU or use IDE Molex plug from PC and add Ferrite CM choke to reduce EMI to power cable twisted pair with Cap at load to avoid EMI effects on analog and logic cables above for different
RF Common mode chokes will be necessary to balance the impedance (BALUN) and prevent AM detection of RF into audio noise. interleaved grounds in layout is useful to reduce crosstalk in high impedance lines. use quality caps for low level signals to avoid microphonics (ceramic piezo) and high
There is a basic rule for a microstrip to reduce radiation: do not insert any inhomogeneity to it like bends and components. Otherwise it must radiate. You can add a metal screen above the line or make a symmetrical microstrip.
reduce your parasitics
I have default clearance set as 10, min is 10, I want to setup a new clearance of 7. But it does not let me define the clearance for nets, only the trace width. I cannot change the min also, it is readonly. What is the procedure to reduce the clearance for some nets? The CES tool is really confusing. thank you Ahgu
The audio draws power from the DC source. The DC source is not a true voltage source and has ESR or effective series reistance. Thus injected audio can reduce supply voltage when current increases. We call this % load regulation, the ratio of change in source DC voltage with full load signal.
You should take an IP3 measurement at ~10dB backed off from the PA's / RF Chains P1dB point. Thus reduce the I/P pwr till the O/P pwr is ~ 10dB lower than the P1dB point. You need to be in the Amp's linear region. If you put too much power you will be compressing Amplifiers, and the IP3 will get worse. Cheers
Vacuum dust yet? inspect heatsink? Reset BIOS yet? reduce FSB? Try MEMTEST86+ on a burned CD to boot from or any live Linux yet? Perhaps aging latent fault, means end of the road.
You need to compare IR LED's to ensure they are same .e.g. rated for 1A max impulse and 100mA continuous and also narrow angle for gain. (<10 deg) You also need to ensure if you are sending > 100mA pulses that the pulse width is differentiated to reduce the avearge power inthe LED but maintain high peak power. So compare LED currents in both usi
i would like see the transient response of dc motor. if i apply 24v to circuit, than take 2 wire from motor pins, what should i do with this pins ? 1) i want ta connect them to the analog input of microcontroler and it can only measure 0-5 V.. 2) the things that i will do to measurement wires shouldn't effect the motor circuit of course
Hi Everyone, I have achieved FAN Dimming using Phase chopping method, here I get smooth dimming on Incandescent Bulbs and I am also able to dim FAN using the same. But during FAN dimming it makes a lot of humming noise due to added harmonics. Can anyone explain this humming in detail and tell how to reduce this noise Reagrds, Ajit Wadekar
A full wave rectified bridge delivers 1.4 x the average voltage to the caps when there is no load. When you have some current limiting series resistors and a 10% preload the unregulated voltage variation can reduce 10 to 20% from 40% or X% where the X% ripple voltage equals the X% drop in average voltage , so it never reaches the root(2) peak vo
Dear Friend, I designed one portable device and battery is used to power the portable device. I choose one transistor, NSS20500UW3 which is from On Semi, to cut off the power supply from the battery when the portable device is in off work state. The schematic is shown in the following picture. X3101 is a switch. When the portable devic
THe current for Fans starts at a fairly constant current and then rises slowly to perhaps double the current from 12 to 24V as more work is done pushing air. Typical 4" muffin fans take about 5W and you would get perhaps 20% of the RPM at 12V. Adding resistors would only reduce the fan speed and dissipate more power in the series R's and be ineff
You need to determine characteristics of the noise in the frequency domain. The process of digital filtering consists to reduce components of the signal lying within a specific bandwidth.
Hi! I am relatively new to CST Studio Suite. I am using the Student Edition, which hugely limits the number of mesh cells allowed for a simulation. In time domain calculations, for example, it allows only 30,000 mesh cells. Unfortunately, this is a ridiculously low number of allowed mesh cells and barely any of my simulations can run due to this li
A CPLD chip can do all of this with a bi-directional bus to reduce pin count. A good design starts with a State Diagram.
Some cars have a whip antenna with a spiral of wire attached to the stalk of the antenna, as per the attached picture. I have read (on various groups) that the spiral is there to reduce wind resistance and noise, alternatively that it covers AM reception as opposed to the content of the stalk covering FM reception. Does anyone have a good re
The time to failure depends on the degree of mismatch among all the cells for specific gravity and ESR. Eventually one cell gets weak and destroys the battery. In practise it is better to put batteries in series to reduce the the probability for peak currents which can cause accelerated aging or shorted plates. As well it makes it easier to
A current meter in series with a circuit has a voltage drop that probably reduces the current draw of the circuit. The voltage drop caused by a current meter is called The Burden Voltage Drop in its spec's. Maybe your circuit uses a power supply voltage of only 3V and your current meter causes the supply voltage to drop to 2V then the current in th
I am using one of those all in one FM stereo transmitter chips. It works very well, but there is a lot of phase noise from the PLL. The chip's default crystal clock speed is 32khz, but the datasheet says the device can be programed for several crystals all the way up to 38.4mhz. Would increasing the clock speed reduce the PLL noise in any way? Is t
You reduce the ability of the transformer to deliver as much current as the current flowing through the secondary is DC. If it was a centre tapped transformer the currents in both halves of the secondary have their DC component opposed so the core does not saturate. Frank
Hi Thanks for Both.Right now Density of board will be reduce once SOC come to the PCB Right ??that time no need for More PCB designer Right ??.Nowaday people working for Density of High speed but SOC will be reduce work for PCB designer ??
Hi All, Suppose there is a long interconnect and we want to reduce the delay by adding buffers. Where should the buffers be added, at the mid point or towards the driver side or the destination side? Why? Thank you Hi, If there is a long interconnect than chances of antenna violations are more so try to pl
reduce winding doesn't work, you need to increase the secondary number of turns by 50 %.
Your supply seems unregulated type, which requires a preload of 5~10% to reduce the Vpk towards Vavg. You can also reduce coil current if necessary. Show schematic and ratings.
Insert a buffer in the clock path of the capture flop. A better approach is to reduce the delay in the data path of the capture flop.
The zener clips the + base drive pulse to bypass the base current and drain the 0.004 cap to reduce the output voltage. Raising the Zener voltage increases the duration of pulse and saturate the core more.
Determine the parallel load R 1st and desired gain up to 100 for practical considerations. The given Freq. , R, Q, there is only one value of L & C such that ω=1 / √(LC) But if you have highest R possible, then the leakage Rp of cap is used. The inductor will have a series resistance Rs which can be neglected if Load R ?Q*Rs, otherw
Hi I have this small problem. I am using a 20kV transformer and not sure why this seems to require a start-up it might be to energize the coil. The total time it takes is about 5ms. Which is too long for my application. Is there a way to reduce this start-sup time or at best remove it. Attached is the scope image. [url=obrazk
If chokes are selected to reduce pulsed %THD and ripple then you must use pulse mode to test equivalent value at rated current to see if it meets design requirements. If you want to verify part value against Mfg specs, then it must be tested in same method using same; f, current source, DC bias. Correlation between the two methods depends on
Diode in reverse only works when diode is across motor to supply , V+ for both low side switches. otherwise diode across motor to gnd. for high side switch. Then driver is protected for Vmax and diode current rating must match driver for continuous current. Small cap across motor may reduce EMI. Current will be limited by RdsOn or Vce(sat) +
The main problem is with the electrode where the oxygen is given off.This would cause any metal to oxidise, in the case of aluminium, would cause an insulator to form on the surface of the electrode ans reduce the current flow. Frank
Hello my friends, I am an academician in Department of Agriculture and I aim to make growth chambers for plants which have light, airconditioning (with computer fan) etc.. One of the important thing is light intensity of chambers. So I use 9 pcs, 3W power led for one chamber and adjust the light intensity with LM350 - potentiometer system (circl
I am doing some test experiment using high gain amplifier as I have very low input. but on general pcb or on bread board I am getting unwanted signal may be due to coupling. when I am applying 3 V AC from my signal generator I am getting 200 mv at oscilloscope when generator and oscilloscope probe are 2 or 3 mm apart in a
I also agree with Klaus suggestion to keep close contact with manufacturer. If you are planing to optimize the size of the PCB in order to reduce the waste of material ( consequently increasing the amount of boards per die - reducing the unit cost ) they could inform the copper sheet and the margin required between boards in photolithography.
I am using ORIGINPRO7 for drawing my research graphs. I have drawn two columns and single row using ORIGINPRO7. I want to reduce the height of VERTICAL lines of two columns using ORIGINPRO7 and retaining same horizontal length. What option I have to use for reducing the height of the VERTICAL line. Can you advice me. I have shown below screen sh
This RF oscillator for dielectric high frequency heating machine , operating at 27MHz but i ve check with spectrum analyzer that it produces much 2nd harmonic around 54MHz. The oscillator is Tuned grid tuned plate (I think) triode used is toshiba 8t25ra rating 25KW I draw a circuit diagram attached and a picture , anyone help ad
Hi, I would like to join the analog and digital grounds at only one place in the PCB using a 0E resistor in order to reduce the noise level in the design. But i stuck up with the SMPS Negative connection with the circuit. I don't know whether i need to connect the SMPS(0V) with analog section or digital section. I give the layout here.. [AT
I have cheap XD-RF-5V module. It is possible to reduce output noise when is present in missing active signal ? Thanks, Stefan