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Hi friends :lol: , does anybody knows a place, or does anybody have some files about "how to reduce the core size for a high power pfc-choke" !! Maybe that somebody knows some new Materials or something who helps to reduce the size from the choke !!!!! Thank you very much Regards :wink:
Designed a ring VCO using 0.18um CMOS process. The simulation tool is Hsp!ce. When measuring many different cycles (using .me@suRe statement), it was found that the durations per cycle were always changing. The design target is 1.140ns per cycle (about 877MHz), but the output varys from 1.138ns to 1.148ns. Anybody here can help me to reduce this va
hello, I need to reduce the current drawn by a ac bi-directional torque motor. - 240V 50Hz, 20Nm torque single phase. 3 wires - clockwise ,anticlockwise, neutral. The motor is direct triac control ie. on and off. Currently, the motor draws 0.4A rms 220Vac in one direction. How do I reduce the current to 0.2A 250Vac - by rule of thumb
in microstrip antenna design, if microstrip line edge-fed is applied, the pattern will be largely affected by the feedline. how to reduce this effect or which type microstrip antenna has the characteristics of low effect by feedline?
Hi tungchang, Are you talking about transmitter? if so, your "in-band noise' is defined as AM/AM and AM/PM effect. For the "out-band noise", it is defined as intermodulation distortion or spectral regrowth. Linearization technique can be applied to reduce those "noise".
hi all, my linter says high fanout (16) on some nets. Can anyone tell me how to reduce this .. tnx
Can anyone tell me how to reduce interrupt latency of MSP430F1121. Im using port interrupt and TIMERA0 (CCIFG i.e. CCR0=timer value) interrupt. this is very urgen for me thanks in advance niks
To reduce the noise for the mixed circuits some attentions should be paid.. - Very good seperated ground connections that are converged onto only one point which is power supply ground.. - Very clean noisless power supply - Seperate VCC lines which are passed "feedthru" capacitors into concerned circuits - On the VCC lines , some inductive lo
Anyone could give me some idea about the reason of frequency offset and how to reduce it?
What CTS method about generated clock & overlapp & gated clock can reduce skew?
Hello, everyone. I'm a newbie on microcontroller and meet with a problem. I'm using AVR Mega16 which has 32 I/O Pins, I often fell it's not enough at all! 4*4 Matrix Keyboard : 8 pins 16*2 LCD: 11 pins T0/T1,INT0/INT1 left for further used... 4 pins Now, left only 9 I/O pins.... If I want to use a RAM....It's not enoug
My TL074 OPAMP has gain of 40dB, and I see 10-20mV of 120hz, 240hz harmonics at the output. I think my ground noise is at 0.1mV, the LDO says it has 30-40uV RMS. Is it a good ground plane with noise of 0.1mV? I think I did the layout pretty good with ground plane and signal separation. But the 120hz harmonics is a little too high and shows up o
Can any one tell me how to reduce leakage and noise in typical domino logic design. Any link, lecture, ideas are very welcome. Thanks in advance, Huy Dang :oops:
Hi How we can reduce MOSFET leakage current for both P and N channel. Im designing low power equipment. Actualy Si3443DV and FDC6305 have more leakage current at VCC=3V. Can anyone tell me how we can reduce it or replacement for the same thanks Niks
A way to reduce charge injection is to put another switch that connects, assuming your input is on the top plate of the capacitor, the bottom plate of the capacitor to ground. Once you have sampled your signal, first open the bottom plate switch. This would always produce the same ammount of charge injection. Then, when the main switch is opened
Can I reduce parallel connection ?
Please adivse how to reduce NF after LNA in a BTS (Recevier). Hi, If you didn't take care of the NF in the LNA stage itself and even before it then, there is not much you can do after the LNA cause NF is additive. If you produce a poor NF, you will not be able to fix that. Enjoy, RF_Router
I need to reduce voltage from 5vDC to 2vDC, can anyone tell me how to do this and how to connect multimeter to check?? I THOUGHT I knew, but stubbornly stays at 5V!!!
Hello gurus, In FPGA design, does the Static Timing Analysis(STA) help to reduce functionals simulation test vetor quantity? I have read such statments in a lecture as"STA analyses all possible paths within a design which doing manually would take lot of time and effort." My question is whether functional simulation goal is to active all possible p
Hello gurus, In FPGA design, does the Static Timing Analysis(STA) help to reduce functionals simulation test vetor quantity? I have read such statments in a lecture as"STA analyses all possible paths within a design which doing manually would take lot of time and effort." My question is whether functional simulation goal is to active all possible
use a ext mosfet to reduce voltage drop,more smaller RDS will get more lower voltage drop.
I want to run many of vector for a chip in the test bench. every time I only change the vectors used . But the compile time is more. which way can be to reduce the run time.? tnx
How to reduce the noise of a gilbert mixer? :roll:
you need to study the source of the noise such as flicker, thermal etc.. study the equation and you can find which parameter can be adjuct to lowering the noise... for example... to reduce flicker noise...you can increase the width of the transistor!
I need to reduce the capacitance between the primary and the secondary in a 50 Hz transformer design using two chambers bobbin, to improve the insulation, and decoupling the circuit from the line. Is necessary to add a coppers lamina, and where? Thanks in advance PD: Please recommend me a book about transformers design and implementation
If you are limited to real axis poles, the best you can do is have a gain of 1.7x per stage and maximize the stage bandwidth. Your suggestion of a source/emitter follower at the output of each stage will reduce the effects of the following stage capacitance.
Hi, In the AMBA specs says "Using tri-state implementation to reduce area" can anyone justify how exactly are we optimising on area when we use a tristate design. Thanks, Gold_kiss
gggould, It is normal behave for VCO as you measured.Problem is mainlly determined by varactor diode exponent characteristic. It is not so easy to obtain VCO with constant Kvco. Some ideas for solution your problem: 1. Find varactor with better characteristic, better linearity 2. Made serial connection two diodes. Take care about DC current fo
Does anyone working on low power, If yes which is the best way to reduce power is by doing architectural analysis or gate level analysis My idea is: 1. If your problem is peak power : Use some power compiler or in apr stage to distribute your logic, make logic not to toggle at same time. 2. If your
hi, can someone give me some techniques to reduce power at a system level. and various techniques that can be used to reduce power at RTL level. i would be happy if i got some reference material too.
In my chip, it have 8 digital power pairs, 3 analog power pairs. when doing mask design, in order ot reduce noise, 1, 8 digital power rail is connected together? 2, 3 analog power rail is connected together? 3, should decouple each power pair each other? someone could give me detailed discription? thanks!
Hi all: I am looking forward to some algorithms to reduce bus switching to reduce power consumption. pls give me some idea.
Hi, I am designing a current source with a noise value less then 5uA rms. When I measure the noise in this current source, I found that there are noise from AC/DC bridge rectifier at the frequency of 120Hz and the radiation from the fluorescent lamp. I just wonder is there any good way to reduce the EMI from the fluorescent lamp? Thanks.
hi can anyone provide with information on detailed discussion on using master and slave mode in HFSS to reduce the simulation time for symmetric structures thanks
You can use power synthesis to reduce power. And power synthesis you can find at synopsys synthesis tools , but you need the power synthesis license.
Hi all Up to what point we can reduce tecnology? ( I mean, I heard about 90n. Can we take it up 1n or more?) Rahul
Hi, I've got this problem that maybe someone here can help. I've got incoming data at 64Kbps and I want to reduce the speed to 9600bps. Anyone has any idea how I can do this? Thanks
Is it possible to replace the transformer/inductor in a off-line type flyback converter by thick power-cable of equivalent inductance? In other words how can we reduce the weight/size of the laptop adaptor circuit which is majorly big/heavy due to transformers and other reactive components. Thanks..
surely making devices bigger will reduce your offset, but you should also pay more power if you want to maintain other parameters like Gain and GBW the same. Other than scaling, some circuit techniques can be used to reduce the offset of the opamp. These include autozeroing (AZ), which is a sampling technique, and correlated double sampling (CDS
Helllo friends I am new to DC. I would like to know how to reduce slack in the design with the help of DC. Can we replace the designware cells to reduce the critical path and if we can, then how? Please help me out. Bye Kshitij Sukhwal
Let me be more specific..I have designed one Bandgap circuit ..for that i am getting a quiescent current of 35mA,the customer is asking me to reduce the quiescent current. Could anyone propose any circuit or just lower the output resistance is enough. 35 mA ? I think it is too large. the bandgap core can be made < 100uA
When the chip is in sleep mode, all digital part has no clock, but the chip has >100uA leak current, Why? how can I find the leak source, and how to reduce it?
I use a fast optocoupler(6n137) to interface two circuits. When ON signal comes to input, the output transistor immediately turns on without a significant delay. But when OFF signal comes to input, the output transistor of the optocoupler doesn't turn off immediately. It takes 6-7us to turn off. How can i reduce this time. The load is an igbt driv
Hi everyone Is there any examples regarding clock designing and how to reduce setup violation and hold violation regards sandeep.
One way to reduce the jitter in digital data is to use a D-type flip flop. Output jitter in this case is defined by jitter of the clock of the flip flop plus inherent jitter of the flip flop.
another method is close this output stage when no input signal , but you should reduce output stage when Turn_on "noise" -> if use in earphone Amp .
hi!!! Thanks for answering my question. thanks I have another problem. I designed fully differential folded cascode circuit and reduce channel length(1um->0.5um) (also reduced width, so W/L is same) and simulated it. The result is Av is down, unity gain BW is up, PM is up I know why Av is down. but why GB and PM is up? please teach m
how to optimize a MUX with 256 input pins to reduce area? I find that the area of the MUX is too large. thanks a lot!
Anyone can help on how to reduce phase noise due to low frequency noise up conversion? Thanks a lot.
1. increasing the switching frequency 2. reduce ur crossover frequency but stability should be kept first