1000 Threads found on edaboard.com: Reduce
Hi friends :lol: ,
does anybody knows a place, or does anybody have some files about "how to reduce the core size for a high power pfc-choke" !!
Maybe that somebody knows some new Materials or something who helps to reduce the size from the choke !!!!!
Thank you very much
Professional Hardware and Electronics Design :: 13.05.2002 07:06 :: Vauxdvihl :: Replies: 0 :: Views: 937
Designed a ring VCO using 0.18um CMOS process. The simulation tool is Hsp!ce. When measuring many different cycles (using .me@suRe statement), it was found that the durations per cycle were always changing. The design target is 1.140ns per cycle (about 877MHz), but the output varys from 1.138ns to 1.148ns. Anybody here can help me to reduce this va
Other Design :: 25.07.2002 05:40 :: danielhzhao :: Replies: 8 :: Views: 3635
I need to reduce the current drawn by a ac bi-directional torque motor.
- 240V 50Hz, 20Nm torque single phase.
3 wires - clockwise ,anticlockwise, neutral.
The motor is direct triac control ie. on and off.
Currently, the motor draws 0.4A rms 220Vac in one direction.
How do I reduce the current to 0.2A 250Vac - by rule of thumb
Professional Hardware and Electronics Design :: 25.09.2002 11:10 :: Lak :: Replies: 5 :: Views: 2409
in microstrip antenna design, if microstrip line edge-fed is applied, the pattern will be largely affected by the feedline. how to reduce this effect or which type microstrip antenna has the characteristics of low effect by feedline?
RF, Microwave, Antennas and Optics :: 06.03.2003 10:35 :: :: Replies: 2 :: Views: 659
Are you talking about transmitter? if so, your "in-band noise' is defined as AM/AM and AM/PM effect. For the "out-band noise", it is defined as intermodulation distortion or spectral regrowth. Linearization technique can be applied to reduce those "noise".
RF, Microwave, Antennas and Optics :: 07.03.2003 09:59 :: mesfet :: Replies: 3 :: Views: 2220
my linter says high fanout (16) on some nets. Can anyone tell me how to reduce this ..
ASIC Design Methodologies and Tools (Digital) :: 27.03.2003 23:20 :: eda_wiz :: Replies: 11 :: Views: 3292
Can anyone tell me how to reduce interrupt latency of MSP430F1121.
Im using port interrupt and TIMERA0 (CCIFG i.e. CCR0=timer value) interrupt.
this is very urgen for me
thanks in advance
PC Programming and Interfacing :: 19.05.2003 06:23 :: niks :: Replies: 9 :: Views: 2118
To reduce the noise for the mixed circuits some attentions should be paid..
- Very good seperated ground connections that are converged onto only one point which is power supply ground..
- Very clean noisless power supply
- Seperate VCC lines which are passed "feedthru" capacitors into concerned circuits
- On the VCC lines , some inductive lo
Professional Hardware and Electronics Design :: 29.05.2003 12:32 :: BigBoss :: Replies: 5 :: Views: 3937
Anyone could give me some idea about the reason of frequency offset and how to reduce it?
RF, Microwave, Antennas and Optics :: 31.05.2003 01:21 :: yuhohang :: Replies: 6 :: Views: 1243
What CTS method about generated clock & overlapp & gated clock
can reduce skew?
ASIC Design Methodologies and Tools (Digital) :: 04.07.2003 02:38 :: zackwang :: Replies: 2 :: Views: 1541
I'm a newbie on microcontroller and meet with a problem.
I'm using AVR Mega16 which has 32 I/O Pins, I often fell it's not enough at all!
4*4 Matrix Keyboard : 8 pins
16*2 LCD: 11 pins
T0/T1,INT0/INT1 left for further used... 4 pins
Now, left only 9 I/O pins....
If I want to use a RAM....It's not enoug
Microcontrollers :: 07.07.2003 07:04 :: sick_man :: Replies: 15 :: Views: 2525
My TL074 OPAMP has gain of 40dB, and I see 10-20mV of 120hz, 240hz harmonics at the output. I think my ground noise is at 0.1mV, the LDO says it has 30-40uV RMS. Is it a good ground plane with noise of 0.1mV? I think I did the layout pretty good with ground plane and signal separation.
But the 120hz harmonics is a little too high and shows up o
Professional Hardware and Electronics Design :: 24.07.2003 11:33 :: ahgu :: Replies: 3 :: Views: 719
Can any one tell me how to reduce leakage and noise in typical domino logic design. Any link, lecture, ideas are very welcome.
Thanks in advance,
Professional Hardware and Electronics Design :: 08.11.2003 12:45 :: hdang :: Replies: 0 :: Views: 608
How we can reduce MOSFET leakage current for both P and N channel.
Im designing low power equipment.
Actualy Si3443DV and FDC6305 have more leakage current at VCC=3V.
Can anyone tell me how we can reduce it or replacement for the same
Professional Hardware and Electronics Design :: 02.12.2003 02:27 :: niks :: Replies: 0 :: Views: 1475
A way to reduce charge injection is to put another switch that connects, assuming your input is on the top plate of the capacitor, the bottom plate of the capacitor to ground.
Once you have sampled your signal, first open the bottom plate switch. This would always produce the same ammount of charge injection. Then, when the main switch is opened
Analog IC Design and Layout :: 26.12.2003 17:25 :: Humungus :: Replies: 30 :: Views: 5307
Can I reduce parallel connection ?
Hobby Circuits and Small Projects Problems :: 10.02.2004 00:31 :: elcielo :: Replies: 8 :: Views: 3977
Please adivse how to reduce NF after LNA in a BTS (Recevier).
If you didn't take care of the NF in the LNA stage itself and even before it then, there is not much you can do after the LNA cause NF is additive. If you produce a poor NF, you will not be able to fix that.
RF, Microwave, Antennas and Optics :: 12.04.2004 16:32 :: RF_Router :: Replies: 26 :: Views: 2372
I need to reduce voltage from 5vDC to 2vDC, can anyone tell me how to do this and how to connect multimeter to check??
I THOUGHT I knew, but stubbornly stays at 5V!!!
Analog Circuit Design :: 07.05.2004 05:26 :: cabman :: Replies: 8 :: Views: 4213
Hello gurus, In FPGA design, does the Static Timing Analysis(STA) help to reduce functionals simulation test vetor quantity? I have read such statments in a lecture as"STA analyses all possible paths within a design which doing manually would take lot of time and effort." My question is whether functional simulation goal is to active all possible p
Electronic Elementary Questions :: 29.05.2004 07:43 :: bittware :: Replies: 1 :: Views: 841
In FPGA design, does the Static Timing Analysis(STA) help to reduce functionals simulation test vetor quantity? I have read such statments in a lecture as"STA analyses all possible paths within a design which doing manually would take lot of time and effort." My question is whether functional simulation goal is to active all possible
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.05.2004 22:21 :: bittware :: Replies: 0 :: Views: 428
use a ext mosfet to reduce voltage drop,more smaller RDS will get more lower voltage drop.
Analog Circuit Design :: 15.07.2004 21:07 :: alphi :: Replies: 10 :: Views: 2092
I want to run many of vector for a chip in the test bench.
every time I only change the vectors used . But the compile time is more.
which way can be to reduce the run time.?
Electromagnetic Design and Simulation :: 05.08.2004 03:43 :: gaonkc :: Replies: 0 :: Views: 588
How to reduce the noise of a gilbert mixer? :roll:
Analog Circuit Design :: 06.08.2004 08:49 :: Kfactor :: Replies: 7 :: Views: 1083
you need to study the source of the noise such as flicker, thermal etc..
study the equation and you can find which parameter can be adjuct to lowering the noise...
to reduce flicker noise...you can increase the width of the transistor!
Analog Circuit Design :: 25.08.2004 21:12 :: guamak_menanak :: Replies: 8 :: Views: 1486
I need to reduce the capacitance between the primary and the secondary in a 50 Hz transformer design using two chambers bobbin, to improve the insulation, and decoupling the circuit from the line.
Is necessary to add a coppers lamina, and where?
Thanks in advance
PD: Please recommend me a book about transformers design and implementation
Electromagnetic Design and Simulation :: 26.08.2004 22:15 :: bomba :: Replies: 4 :: Views: 1318
If you are limited to real axis poles, the best you can do is have a gain of 1.7x per stage and maximize the stage bandwidth. Your suggestion of a source/emitter follower at the output of each stage will reduce the effects of the following stage capacitance.
Analog IC Design and Layout :: 05.09.2004 08:40 :: flatulent :: Replies: 1 :: Views: 1086
In the AMBA specs says
"Using tri-state implementation to reduce area"
can anyone justify how exactly are we optimising on area when we use a tristate design.
ASIC Design Methodologies and Tools (Digital) :: 08.09.2004 05:15 :: gold_kiss :: Replies: 4 :: Views: 758
It is normal behave for VCO as you measured.Problem is mainlly determined by varactor diode exponent characteristic. It is not so easy to obtain VCO with constant Kvco. Some ideas for solution your problem:
1. Find varactor with better characteristic, better linearity
2. Made serial connection two diodes. Take care about DC current fo
RF, Microwave, Antennas and Optics :: 14.09.2004 08:08 :: xtasa :: Replies: 3 :: Views: 1267
Does anyone working on low power,
If yes which is the best way to reduce power
is by doing architectural analysis or gate level analysis
My idea is:
1. If your problem is peak power :
Use some power compiler or in apr stage to distribute your logic, make
logic not to toggle at same time.
2. If your
ASIC Design Methodologies and Tools (Digital) :: 02.12.2004 03:16 :: abner :: Replies: 30 :: Views: 3527
can someone give me some techniques to reduce power at a system level. and various techniques that can be used to reduce power at RTL level.
i would be happy if i got some reference material too.
ASIC Design Methodologies and Tools (Digital) :: 27.10.2004 11:38 :: rogger123 :: Replies: 6 :: Views: 866
In my chip, it have 8 digital power pairs, 3 analog power pairs.
when doing mask design, in order ot reduce noise,
1, 8 digital power rail is connected together?
2, 3 analog power rail is connected together?
3, should decouple each power pair each other?
someone could give me detailed discription? thanks!
ASIC Design Methodologies and Tools (Digital) :: 28.10.2004 03:53 :: tavidu :: Replies: 1 :: Views: 785
I am looking forward to some algorithms to reduce bus switching
to reduce power consumption. pls give me some idea.
ASIC Design Methodologies and Tools (Digital) :: 24.12.2004 23:02 :: roger :: Replies: 3 :: Views: 486
I am designing a current source with a noise value less then 5uA rms. When I measure the noise in this current source, I found that there are noise from AC/DC bridge rectifier at the frequency of 120Hz and the radiation from the fluorescent lamp.
I just wonder is there any good way to reduce the EMI from the fluorescent lamp?
Analog Circuit Design :: 09.01.2005 17:47 :: arizona999 :: Replies: 3 :: Views: 2022
can anyone provide with information on detailed discussion on using master and slave mode in HFSS to reduce the simulation time for symmetric structures
Software Problems, Hints and Reviews :: 11.01.2005 12:30 :: hitmo :: Replies: 1 :: Views: 1071
You can use power synthesis to reduce power. And power synthesis you can find at synopsys synthesis tools , but you need the power synthesis license.
ASIC Design Methodologies and Tools (Digital) :: 21.02.2005 06:51 :: stormwolf :: Replies: 7 :: Views: 976
Up to what point we can reduce tecnology? ( I mean, I heard about 90n. Can we take it up 1n or more?)
ASIC Design Methodologies and Tools (Digital) :: 01.03.2005 09:02 :: shelkerahul :: Replies: 0 :: Views: 327
Hi, I've got this problem that maybe someone here can help. I've got incoming data at 64Kbps and I want to reduce the speed to 9600bps. Anyone has any idea how I can do this? Thanks
Microcontrollers :: 08.03.2005 01:16 :: joajas :: Replies: 3 :: Views: 438
Is it possible to replace the transformer/inductor in a off-line type flyback converter by thick power-cable of equivalent inductance? In other words how can we reduce the weight/size of the laptop adaptor circuit which is majorly big/heavy due to transformers and other reactive components.
Analog Circuit Design :: 10.03.2005 09:57 :: chanchg :: Replies: 1 :: Views: 961
surely making devices bigger will reduce your offset, but you should also pay more power if you want to maintain other parameters like Gain and GBW the same.
Other than scaling, some circuit techniques can be used to reduce the offset of the opamp. These include autozeroing (AZ), which is a sampling technique, and correlated double sampling (CDS
Analog Circuit Design :: 15.06.2005 06:12 :: Alles Gute :: Replies: 11 :: Views: 2434
I am new to DC. I would like to know how to reduce slack in the design with the help of DC.
Can we replace the designware cells to reduce the critical path and if we can, then how?
Please help me out.
ASIC Design Methodologies and Tools (Digital) :: 29.04.2005 07:47 :: kshitij_s81 :: Replies: 0 :: Views: 510
Let me be more specific..I have designed one Bandgap circuit ..for that i am getting a quiescent current of 35mA,the customer is asking me to reduce the quiescent current.
Could anyone propose any circuit or just lower the output resistance is enough.
35 mA ? I think it is too large.
the bandgap core can be made < 100uA
Analog IC Design and Layout :: 11.05.2005 00:43 :: Btrend :: Replies: 10 :: Views: 942
When the chip is in sleep mode, all digital part has no clock, but the chip has >100uA leak current, Why? how can I find the leak source, and how to reduce it?
Electronic Elementary Questions :: 19.05.2005 10:32 :: wkong_zhu :: Replies: 4 :: Views: 1288
I use a fast optocoupler(6n137) to interface two circuits. When ON signal comes to input, the output transistor immediately turns on without a significant delay. But when OFF signal comes to input, the output transistor of the optocoupler doesn't turn off immediately. It takes 6-7us to turn off. How can i reduce this time. The load is an igbt driv
Professional Hardware and Electronics Design :: 23.06.2005 04:57 :: seyyah :: Replies: 8 :: Views: 2587
Is there any examples regarding clock designing and how to reduce setup violation and hold violation
ASIC Design Methodologies and Tools (Digital) :: 24.06.2005 01:30 :: sandysuhy :: Replies: 3 :: Views: 759
One way to reduce the jitter in digital data is to use a D-type flip flop. Output jitter in this case is defined by jitter of the clock of the flip flop plus inherent jitter of the flip flop.
Analog Circuit Design :: 27.06.2005 11:51 :: rfmw :: Replies: 6 :: Views: 1877
another method is close this output stage when no
input signal , but you should reduce output stage when Turn_on "noise" -> if use in earphone Amp .
Analog Circuit Design :: 14.07.2005 05:31 :: andy2000a :: Replies: 5 :: Views: 996
the av is down,for the output resistance is smaller
GB and PM is up,is for size of the transitor is smaller,then parasitic capacitance is small,so the GB is up for the output node parasitc capacitance is smaller,so RC constant becomes smaller,then GB biger.
PM is up,for the second pole becomes bigger for that node's parasitic capcitance is smalle
Analog Circuit Design :: 22.07.2005 01:01 :: winsonpku :: Replies: 1 :: Views: 464
how to optimize a MUX with 256 input pins to reduce area? I find that the area of the MUX is too large.
thanks a lot!
ASIC Design Methodologies and Tools (Digital) :: 25.07.2005 22:15 :: mark_alin :: Replies: 4 :: Views: 939
Anyone can help on how to reduce phase noise due to low frequency noise up conversion?
Thanks a lot.
RF, Microwave, Antennas and Optics :: 24.08.2005 12:08 :: pi331133 :: Replies: 5 :: Views: 880
1. increasing the switching frequency
2. reduce ur crossover frequency but stability should be kept first
Analog IC Design and Layout :: 25.08.2005 03:14 :: Btrend :: Replies: 10 :: Views: 1471