41 Threads found on edaboard.com: Response Time Comparator
hi ,every one
now i have to design a comparator with 5mv offset and 40ns response time.what i want to ask to you is how i can measure the response time and offset with hspice.
as far as i know,the comparator's response have two ways that is linear and slew depending on the (...)
Analog Circuit Design :: 24.11.2005 10:08 :: gonewind :: Replies: 1 :: Views: 884
For a NMOS open-drain comparator circuit,
how to reduce the ?response time High to Low?？
Analog IC Design and Layout :: 14.09.2005 06:10 :: holddreams :: Replies: 3 :: Views: 679
Any idea where I can know what's the response time of the analog comparator inside the AT89C2051?
It does not seem to be mentioned in the datasheet anywhere!
Microcontrollers :: 23.07.2010 04:57 :: KamalS :: Replies: 3 :: Views: 1062
response time is a typical parameter to specify components with digital output, e.g. a comparator. It's no commonly used term for OPs.
Electronic Elementary Questions :: 13.09.2012 12:04 :: FvM :: Replies: 4 :: Views: 990
The LTC1841 commparator has a propagation delay of up to 14us
How can this be?
...i thought comparators were supposed to be fast?
The LM393 has a response time of 1.4us
....The 14us seems ridiculo
Analog Circuit Design :: 13.10.2012 11:13 :: treez :: Replies: 1 :: Views: 190
Actually, I am using a latched comparator in my switching reg controller now. It has some very good points in its favor like a 30ns response time. But the main disadv I have noticed so far is its resolution/accuracy. It's not its strong point! More info on latched comparator: check following IEEE paper,
Analog Circuit Design :: 14.04.2005 07:17 :: kart339 :: Replies: 4 :: Views: 1272
The following is a comparator datasheet:
How can simulate Ioh,Vol,Icc,tPLH,tPHL of this comparator?
Can anyone tell me how to add stimulus in the hspice netlist?
response-time measurement at low input signal levels can be greatly affected by the input offset vo
Analog Circuit Design :: 08.10.2005 04:51 :: holddreams :: Replies: 1 :: Views: 905
This is because normally opamp has compensation capacitor which will slow down response time of the output or the rising/ falling of the output. As comparator, you no need it because it is a open loop system.
Correct. The most popular OA, the 741, had a version without the compensation capacitor (if I'm not wrong, it was
Analog Circuit Design :: 09.11.2005 09:23 :: zorro :: Replies: 8 :: Views: 2854
I think response time is also extremely important (especially with faster switching speeds) and hysteresis to prevent multiple triggering caused by noise.
Analog IC Design and Layout :: 26.12.2005 05:27 :: johnsmith101 :: Replies: 5 :: Views: 1187
I know that traditionally, an op-amp connected as a comparator consistently underperformed dedicated comparators in most respects.
But that was when we were comparing a 741 and a 311.
Op-amp technology has progressed faster than comparator technology.
We have today op-amps with exceptional speed, which I would expect to (...)
Electronic Elementary Questions :: 23.01.2006 09:13 :: funberry :: Replies: 2 :: Views: 1473
I think , you should simulate the settling performance of the SHA first.
then you had better simulate the offset of the comparator. however, to simulate the offset of the comparator is very difficult task. I think you should design it and layout it carefully.
normally, the monte carlo simualtion can assist your analysis.
the response (...)
Analog Circuit Design :: 24.12.2007 00:02 :: renwl :: Replies: 9 :: Views: 3292
I believe you can increase the tail current to decrease the delay (what is your clock frequency?) of the output response or you could latch the output of the comparator with a delayed version of the sampling clock, say 160ps later. If neither is good for you, add a preamplifier or change the comparator topology.
Analog IC Design and Layout :: 14.03.2009 13:28 :: JoannesPaulus :: Replies: 2 :: Views: 1401
Does response time of a comparator in the datasheet means the time it takes the output to see the change of the input? and the slew rate is the time for the output to change its state?
if i am correct about the response time, is there a way to improve it?
Analog Circuit Design :: 18.05.2011 03:52 :: hayowazzup :: Replies: 8 :: Views: 681
does any one help me in designing the comparator?
what are all factor need to be checked in designing the comparator.how can i reduce the response time of the comparator.
Analog IC Design and Layout :: 30.06.2012 03:03 :: krishkannan :: Replies: 1 :: Views: 366
I am performing humidity measurement using the HS1101 sensor. The idea of measuring the humidity is charging anf decharging the sensor(capacitance). Please look at the link
As it is written in the link above, the solution is based on a timer which charges/decharges the cap
Analog Circuit Design :: 08.08.2012 00:22 :: lowpowermcu :: Replies: 1 :: Views: 344
Unless you have slowed down the op amp with capacitors. There is no way that a thermocouple will be faster than an op.
The time that the heater needs to warm the metal rods (when the heater is on) and the time in which the rods cool down (when the heater is off) produces a delayed response much slower than the op amp is capable to react.
Electronic Elementary Questions :: 06.04.2013 14:54 :: albert22 :: Replies: 1 :: Views: 195
BIST consists of
*)PRPG-> Psuedo random pattern generator
*)Memory for storing the expected results
PRPG pumps in random data to the DUT. DUT response is compacted and compared with expected response for corresponding to that particular input. The expected results will be (...)
ASIC Design Methodologies and Tools (Digital) :: 19.04.2004 09:48 :: eda_wiz :: Replies: 21 :: Views: 3293
Generally speakng 339 is not very precise comparator with average response time, so you can easily use 324 instead. The only difference will be that you can connect its output to larger voltages then its supply because of the OC output stage.
On the other hand, you can not replace 324 with 339 in linear applcations because 329 as (...)
Analog Circuit Design :: 28.01.2005 21:11 :: IanP :: Replies: 4 :: Views: 9889
comparator response can be improved by adding hysterisis equal to or greater than amount of largest expected noise amplitude.
Ways to introduce hyterisis is by external method and internal method..
Maybe the speed is better with internel method coz it does not require external feedback.
Analog Circuit Design :: 11.01.2006 01:33 :: Syukri :: Replies: 14 :: Views: 1888
Given the fixed input waveform signal, e.g. full swing square wave input is applied to one input of comparator and another input is fixed voltage, then you can observe how long it takes to response.
Analog Circuit Design :: 20.01.2006 05:07 :: paulux :: Replies: 4 :: Views: 1551
the comparator has a good offset(≤1mv) and a fast response(maybe :cry:) to the input pulse, for instanse, when the input- is holded at COM, the input+ is a step pulse very fast the delay of output is about 200ns.
When the input- is holded, the input+ changes very slowly, the switching point equals the voltage of input-. But if the speed o
Analog IC Design and Layout :: 16.06.2006 21:26 :: hunk :: Replies: 2 :: Views: 781
It is usually not same. comparators can have internal positive feedback that can make faster switching and response time... and so on...
Here is what you are interested in:
Analog Circuit Design :: 07.07.2006 06:36 :: pixel :: Replies: 8 :: Views: 1012
All I know is that comparators are used to compare signals and they are very important therefore are used in many types of circuits.
So how are comparators used in these circuits?
What makes a good comparator in different application?
Is faster response time and larger output voltage always better? (...)
Analog Circuit Design :: 14.09.2006 05:09 :: renwl :: Replies: 3 :: Views: 1128
Usually it is 100mV step with 5-20mV overdrive ..
Step represents the voltage change necessary to switch the input differential stage fully from one state to the other ..
To understand what an overdrive is read the following quotation:
If the input voltage to a comparator is more positive than the reference voltage plus the offset?VOS
Analog Circuit Design :: 16.05.2007 23:22 :: IanP :: Replies: 1 :: Views: 1200
Table 8.2-2 of Allen?s book <> gives us a procedure to design a two-stage open-loop comparator for a linear response, in step 3, there is a equation I5=I7(2CI/CII), but I really don?t know how and from where can I derive it, your suggestions and time will be highly appreciated.
Analog IC Design and Layout :: 12.07.2007 23:44 :: qiushidaren :: Replies: 0 :: Views: 794
Well first if you want to design 40 Msps-12 Bits SAR ADC, you need 480 MHz takt. That means your comparator, and your DAC need to have 2.1ns response time totally. That is quite a problem.
Second you need to design "12 bit good" comparator (regarding offset) and 12 bit good DAC (regarding matching) which is also very big (...)
Analog IC Design and Layout :: 10.01.2008 06:58 :: zajbanlik :: Replies: 2 :: Views: 814
I am calculating the steepest slope for the output time response of the the two-stage open-loop comparator. From the book (Allen, P.448, Eq.8.2-13), it says I need to find it by differentiating the equation of time response twice and setting the result the result = 0. Why???
I know the slope can be (...)
Analog Circuit Design :: 14.05.2008 18:57 :: joehwang :: Replies: 1 :: Views: 582
Try another speed of the triangle during transient simulation - and you will most probably see a voltage difference even other than 283 mV. The reason is that during Tran analysis all time dependent elements (in particular: capacitances) are considered - opposite to the dc analysis. Thus, all delay effects of the realistic amplifier model influence
Analog Circuit Design :: 25.09.2010 07:23 :: LvW :: Replies: 2 :: Views: 1053
LM393 is a comparator so Gain-bandwidth is irrelevant. Large signal response time is 300ns, small signal 1.3us so for 50kHz you will be fine.
Analog Circuit Design :: 20.01.2011 05:38 :: keith1200rs :: Replies: 1 :: Views: 885
i asked the tutor he said its the delay of the 555timer and flip-flop. that caused the phase shift between flip-flop output and comparator output.
Doesn't sound reasonable. 4027 and 555 have delays in < 1us range, even the comparator response time is much faster than the delays viewn in your waveform. The (...)
Hobby Circuits and Small Projects Problems :: 05.09.2011 06:34 :: FvM :: Replies: 18 :: Views: 1945
I think the most important spec for your opamp and comparator will be offset voltage. There's not really a 'gain' for the integrator, there's a volts/sec constant, and that's going to depend on your requirements.
In industry standard dual slope circuits, integrator and comparator offset voltage are eliminated, that's why these circu
Analog Circuit Design :: 09.09.2011 14:17 :: FvM :: Replies: 2 :: Views: 634
For short-circuit and overload protection you need currrent sensing methods. For short-circuit protection the response time must be very quick in order to prevent damage to the MOSFETs. For overvoltage protection, you can compare the scaled down DC voltage to a fixed reference and latch the output which will shut down the IR2153.
Hope this helps.
Power Electronics :: 18.01.2013 01:04 :: Tahmid :: Replies: 7 :: Views: 2322
What makes you think that you can get away with 0 delay?
The datasheet says
Typ. response time TRES 200ns
Analog Circuit Design :: 28.06.2012 06:57 :: alexan_e :: Replies: 2 :: Views: 189
Nominal Resolution of dual-slope ADC is usually referring to the resolution of the time measurement of de-integration phase and is simply given by your hardware design. Usable resolution is a matter of various error terms and more difficult to determine. Ponts to consider are
- integration capacitor loss factor
- comparator response (...)
Analog Circuit Design :: 22.09.2012 10:54 :: FvM :: Replies: 2 :: Views: 578
In ocean script, I am trying to if clock is = 1 and output is = 1 in an transient response, then get the x-value. From that x-value, get the y-value of input. I am not sure where to start.
I don't think this is right, because there is no timing information.
If( (VT("/clk")==1) && (VT("/Vout")==1) ....)
Anyone can help me solve this
Analog Circuit Design :: 29.07.2013 22:03 :: chaosatom :: Replies: 1 :: Views: 386
Hi can you please give me some quick tutorial on how to start designing differential comparator? it would really help me. thank you in advance.
hi, thanks for your interest in this topic...
first of all you must know what a comparator is.... for example ... op-amp can be used as a comparator...
Analog IC Design and Layout :: 22.08.2013 02:20 :: kenambo :: Replies: 5 :: Views: 578
I think your system is slow in response. Because you are waiting one(or a bit more) revolution to compensate the speed error. And until you reach the desired speed, a lot of time passes. Also i wonder how do you adjust the speed. I mean if the motor is slow than you expected than you need to increase the duty cycle. But how do you decide how much y
Robotics and Automatics Forum :: 06.10.2004 14:36 :: seyyah :: Replies: 20 :: Views: 6503
There is no such definition,
You might be confusing propagation
delay and VIH.
When you apply a signal at the input
it takes for a while for the output to respond,
But at the same time if you keep increasing the
input, you might think that the input value at the time of output signal is changing state is VIH and/or VIL, this is not true. T
Analog IC Design and Layout :: 26.10.2004 14:22 :: devrimaksin :: Replies: 3 :: Views: 2404
You could use LEDs of different color to shine in turn (not together) on the sample paper.
An ADC will convert the response of a light sensor, for each color, to values between 01 and 255.
The combination of those values will identify one paper "color".
As far as I know, the disadvantage is that every time you repeat this circuit (build a
Hobby Circuits and Small Projects Problems :: 29.12.2006 06:25 :: atferrari :: Replies: 4 :: Views: 1663
If you got the correct model, you can break the loop with current feedback loop closed. Then you got a bode diagram that push LC poles to the high frequency. You can series connect a resistor and a cap to form a zero. You also can obtain another zero by parallel connecting a cap with feedback resistor divider. With enough zero, you get the loop sta
Analog IC Design and Layout :: 18.01.2008 07:10 :: leo_o2 :: Replies: 4 :: Views: 1082
100MHz to 1 GHz high switching speed would imply a comparator that converts the sine to a square wave. I understand, that you intended a rectifier or RMS detector however.
It would have switching delay clearly above several 10 ns for a simple design. Accuracy may be improved by filtering the measurement with a higher time constant (us and above)
Analog Circuit Design :: 12.06.2008 03:27 :: FvM :: Replies: 11 :: Views: 677