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9 Threads found on edaboard.com: Response Time Ldo
Define Input and output voltage, max avg and surge current at present and desired response time and current limit. Or define the circuit and load which causes the surge.
I think first you need to prevent overshoot. A regulator that outputs higher than desired voltage will probably damage everything it's connected to; that's why you use a regulator to begin with. I think you are on the right track: you need to improve the response time. A regulator is a feedback system, and you should look at it as such.
Bandwidth and gain are tradeoffs. The unity gain maximum bandwidth of OP AMPs used inside ldo's, limits the settling time. Beyond this you have to consider parasitic inductance, current limits and capacitance load of step response.
There is no general recommendation for Co. As soon as you know the reason for including Co (time response to input voltage and load changes, loop stability) you will see that the value depends on several parameters (placement of poles and zeros) . And don't forget the ESR effect.
0.35 divided by your edge time (you wrote first 0.1nsec!) = Fbw to 3dB_ this is my source:-) I never see this formula, where do you get this? in the ieee paper titled "An Improved Fast Transient response Low Dropout Voltage Regulator" by Mohammad Usaid Abbasi They are using 1ns rise and fall time with 44ns settling (...)
Maybe you need a large external Capacitor to imrpove tansient response!
hello i need your help with this problem. attached picture presents ldo's time response when the output voltage is reprogrammedform 0.8 to 1.4 and vice versa. it's the simplest ldo with OTA + PMOS and feedback resistors. as you can see. the falling time is not symetrical with rising one. the blue (...)
I have designed ldo with 0.3V dropout. But in trasient voltage variation my ckt works fine for rising load current but during falling load current ! O/P is not settling for lower cap values (giving oscillations) and with higher cap values the fall time is very high then rise time ? why ? what is going wrong ?
no, NMOS needs a voltage supply HIGHER than vdd to achieve low dropout, such as an on-board charge pump. If you can accept this (takes a lot of supply current when the pump is running) then NMOS will beat PMOS every time in both device size and ease of compensation. Also, with less poles you can usually get the bandwidth (response) of the NMOS de