1000 Threads found on edaboard.com: rs232 Vhdl
Would anyone share the rs232 vhdl code ?
If you have rs232 test program , please share.
Thanks a lot.
Other Design :: 03-30-2002 04:47 :: cssheu :: Replies: 11 :: Views: 13108
Hi.I am so sorry because of my poor English speaking!
I am trying to write a simple code in vhdl for rs232 to receive data through a wire as you know.here is my code!
something is wrong! please help me to solve this challenge!thanks :)
as you can see,bit_cnt pulsed twice!!!!!why? and number of "get" state must
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-02-2013 04:29 :: vishy71 :: Replies: 5 :: Views: 323
I have a Xilinx Spartan-3E and what i want to do is this:
Press a button ex. East Button on the board and send a signal eg. "00101100" to a device on the other end of Spartans rs232 port.
Like when i press the button and the leds are on i want to send this signal over the serial port lets say to a PC on the other end.
The only thing i have
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-12-2008 09:47 :: frid4y :: Replies: 5 :: Views: 8897
here is a good thread for it.. rs232 vhdl-core | Comp.Arch.FPGA |
maybe interesting.. i used it to do a part of my own UART
Electronic Elementary Questions :: 09-07-2010 03:45 :: Electro_Nic :: Replies: 5 :: Views: 1202
I assign both outputs and inputs of my uart vhdl codes to the 9 pins of that correct?? In the entity part of the uart vhdl code below, rx_data_out and tx_data_in are 8 bits width.I don't know how to assign them with the pin of rs232..anyone can help me??
entity uart_serial is
-- Global signal
PC Programming and Interfacing :: 09-11-2008 07:49 :: brunokasimin :: Replies: 1 :: Views: 1445
Does anyone have uart example of vhdl where i can test my rs232 on my board altium?
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-19-2008 05:48 :: brunokasimin :: Replies: 3 :: Views: 1334
We are trying to do some homework making a rs232 transmitter...
This is what we made so far and there is a lot of faults it it.. but we don't know what. We think its something with the way we written the states. Please rewrite it to some useful syntax
this is what we made so far
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-17-2011 13:50 :: Ivan-Holm :: Replies: 3 :: Views: 515
Doing Complete calculator in vhdl wont turn out to be economical design.
What you can do is you need to write / use some 8 bit vhdl CPU to do the job.
Using this cpu you can interface keyboard and display to it. And use it for doing
calculations also. 8051 core in vhdl is available you can use it. For testing you
can use (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-05-2004 02:20 :: nand_gates :: Replies: 1 :: Views: 4376
I am in need of source code of vhdl OF -- PS/2 and rs232 --Protocal!!
if you have it ,or you know how to program it in vhdl , please help me!:|
thank you very much!:D
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-31-2006 21:45 :: vvsvv :: Replies: 1 :: Views: 1127
I am doing my final project in computer engineering and I need to connect a CMU cam into Ethernet.
I was thinking of building a hardware using vhdl which will transfer between the Camera's serial port to Ethernet (and the opposite of course).
Does anyone know where I could find such code?
ASIC Design Methodologies and Tools (Digital) :: 12-06-2007 07:23 :: liorbaz :: Replies: 2 :: Views: 1385
www.fpga4fun.com....and get verilog source code there
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-23-2008 06:40 :: amburose :: Replies: 7 :: Views: 18176
hi , i didn2t want to open a new topic for this, thats way i write here, could you tell me which rs232(i think there are rs232 on different voltages) should i choose for FPGA, i also will implement uart.
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-20-2009 05:53 :: deniz88 :: Replies: 7 :: Views: 6820
This is really getting nowhere. Do you know ANYTHING about USB or FPGA at all?
First of all, Using USB to communicate between an FPGA and a PC is like trying to fly a 747 in order to go to your friends home next door.
USB is complicated, difficult and complex protocol and in NO WAY it is communicating in ASCII, unless you have a special devic
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-15-2010 04:55 :: farhada :: Replies: 19 :: Views: 12203
you could create a memory with the values of the text file, generate it through IP wizard and read it. Every time that you want to read a image you have to modify your memory and recompile the entire project. This is like and "offline" solution.
Or, if you want to read "online" the text file, you could send the values through serial (rs232) cone
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-25-2010 16:55 :: mersault :: Replies: 43 :: Views: 6753
i need for a project to decode characters sent to rs232 Receiver module the RS 232 receiver will feed its data to the LCD display and that will be on spartan 3A .
i have the rs232 Receiver module done but what i am missing is the part related to the LCD display as i want one and i hope it is in vhdl and not relying on (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-25-2010 06:00 :: amronasr :: Replies: 9 :: Views: 1514
i had written uart receiver module and baud generator module for baudrate:9600 bps in vhdl. This code is working properly for all 1 digit values. Now i want to send a text file containing datas such as
eg: 123 56 234
175 34 100
how do i send this through rs232 to fpga???
Thank you all in advance..........
Electronic Elementary Questions :: 02-16-2011 05:27 :: lucky :: Replies: 0 :: Views: 935
Please look at opencores.org. They have rs232 as well as ethernet mac core.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-17-2011 00:42 :: tariq786 :: Replies: 3 :: Views: 2363
I am using my FPGA(virtex-6) kit for the project,
project is rs232 to Ethernet converter,
1) i ll write a code for the rs232/434 and dump my code in FPGA then i need to transfer the data by Ethernet to other device or PC.
2) vice versa the data which is coming from the PC or device from the ethernet port need to be stored in the rs23
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-10-2012 02:25 :: manojb :: Replies: 1 :: Views: 822
some issues are apparent:
1.) rs232 is lsb first, so "z" will come up as 0 0101 1110 1.
2.) you appear to transmit "M" lsb first (correct), but the start/stop bits are swapped (incorrect). eg, x1(0) = '1' and x1(9) = '0'. Thus the framing will be incorrect. the receiver may see 11001001 as the data byte, which would be an extended ascii charac
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-08-2012 04:24 :: permute :: Replies: 1 :: Views: 402
I have a problem with rs232 transmission. It doesn't work even when i send the first, start frame($55). Next frame $3x choses a led and the last one turns it on/off. I cant even turn on a led when i get start frame. I cant find any mistakes in a code. Maybe You will find something or give some advice. I enclose code with a problematic part.
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-30-2012 03:38 :: lonerpl :: Replies: 1 :: Views: 260
I m working on a Altera DE2-70 board, and i need simple vhdl/verilog programs to make use of all the resources in the system.
The available resources are
? 2-Mbyte SSRAM
? Two 32-Mbyte SDRAM
? 8-Mbyte Flash memory
? SD Card socket
? 4 pushbutton switches
? 18 toggle switches
? 18 red user LEDs
? 9 green user LEDs
? 50-MHz oscil
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-25-2012 04:37 :: walker_iit :: Replies: 1 :: Views: 899
I need to implement an uart module written in vhdl to comunicate with another module, I have tried to use this code (source) with this main:
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-31-2013 07:24 :: shedo :: Replies: 3 :: Views: 1156
there appear to be a total of 64 elements in a small implementation and 4096 elements in the large implementation. What specifically are you expecting the vhdl to do?
for example, is this a simulation only construct?
is this a synthesizable construct?
how do you plan to put data into the structure? eg, data from a PC (ethernet/usb/rs232 interfa
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-27-2013 03:01 :: permute :: Replies: 6 :: Views: 305
My favorite example for rs232:
The code used in that article is verilog, but a lot of useful hints in there that you can use directly in your vhdl design.
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-06-2014 21:57 :: mrflibble :: Replies: 4 :: Views: 251
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments....
For FPGA design, what I have used synthesis tools(only to synthesis vhdl code): Synplicity Synplify > Synopsys FPGA Compiler II > Mentor Leonardo Exemplar
It is only my personal opinion...
Professional Hardware and Electronics Design :: 07-13-2001 17:19 :: :: Replies: 7 :: Views: 3631
I need to connect two PIC using USART, but considering the long distance, I think I'll
need to convert rs232 to rs485 and then back
to rs 232. Does someone has suggestions, esperience about the solutions I should use ?
Professional Hardware and Electronics Design :: 07-13-2001 19:04 :: proton :: Replies: 26 :: Views: 25426
If you want an audio interactive tutor to learn Verilog or vhdl.. I did upload it for someone who did ask me... ES PERAN Verilog & vhdl.
If you are interested let me know
Professional Hardware and Electronics Design :: 08-06-2001 13:01 :: henrik2000 :: Replies: 5 :: Views: 9953
I am a student from Harbin China. Now I am building a behavioral model of a Direct Sequence Spread Spectrum Communication system using vhdl-AMS. So i want to know where can I find some example similar to that or something that may give help to me.
Can you give me some advices. Thank you!
[ This Message was edited by: flybear on
Professional Hardware and Electronics Design :: 10-29-2001 04:17 :: flybear :: Replies: 0 :: Views: 1504
i'm looking for a circuit or a pic program
to convert from irda to rs232!
Please don't reply unless you have useful information to add on this post.Thanks
Professional Hardware and Electronics Design :: 01-11-2002 16:11 :: tomato223 :: Replies: 4 :: Views: 1846
vhdl QUICK Reference Guide
Ready for onboard prints
Uploaded file: vhdlref.pdf
Microcontrollers :: 02-21-2002 06:04 :: jimjim2k :: Replies: 2 :: Views: 3114
where to get test bench with vhdl for SDH chip?
Microcontrollers :: 02-22-2002 00:49 :: coolsniper :: Replies: 10 :: Views: 2312
The vhdl Golden Reference Guide
A 136 pps ebook.
Uploaded file: vhdl-golden-reference.pdf
Please don't reply unless you have useful information to add on this post. Thanks !
(No Me-too's, no Thanks-you's, etc ... use
Microcontrollers :: 02-24-2002 06:48 :: jimjim2k :: Replies: 3 :: Views: 7723
Here is the vhdl code for 8051 MC.
Uploaded file: 8051 in vhdl.zip
Microcontrollers :: 02-24-2002 06:59 :: jimjim2k :: Replies: 8 :: Views: 7735
LEON is a synthesisable vhdl model of a 32-bit SPARC* compatible processor, developed by the European Space Agency (ESA) for future space missions. To promote the SPARC architecture and enable development of system-on-a-chip (SOC) devices using SPARC cores, ESA is making the full source code freely available under the GNU LGPL license.
Microcontrollers :: 02-25-2002 09:00 :: jimjim2k :: Replies: 5 :: Views: 3606
vhdl Language reference manual. latest edition.
Please don't reply unless you have useful information to add on this post.
Any other replies are always welcome via PM.
[ This Message was edited by: KARLZ on
Microcontrollers :: 03-01-2002 15:09 :: KARLZ :: Replies: 3 :: Views: 2352
Online vhdl Testbench Generator
1. TestBench Tool
3. -> t
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-02-2002 08:40 :: jimjim2k :: Replies: 6 :: Views: 6609
These materials are made available for ECE 4170: Introduction to HDLs with Applications to Digital Design taught during the Spring 2000 Semester at Georgia Tech.
This text focuses on presenting the basic features of the vhdl language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by fami
Microcontrollers :: 03-02-2002 09:09 :: jimjim2k :: Replies: 9 :: Views: 3311
Anyone interested in a single entity vhdl testbench generator, try this. Code is free to do with as you wish. If you add significant enhancements, please send me a new copy too. You will need to have Tcl/Tk installed on you system to use this.
Uploaded file: tb_gen.tcl
Microcontrollers :: 03-04-2002 20:12 :: mexico_mike :: Replies: 2 :: Views: 3712
Would you please upload IEEE Standards
for verilog and vhdl to this place.
1. If you have uploaded files in some other boards, please leave a URL pointer only.
2. Please rename the files before uploading by the a definitive words to distingush files from each other. It seems that the forum replaces every newer file with
Microcontrollers :: 03-05-2002 02:40 :: jimjim2k :: Replies: 0 :: Views: 1599
Which most prefer or popular? vhdl or Verilog?
ASIC Design Methodologies and Tools (Digital) :: 03-09-2002 12:13 :: cadb0y :: Replies: 113 :: Views: 15393
Anyone has a DSP core in vhdl or Verilog? Prefer TI but anyone will do.
Microcontrollers :: 03-14-2002 11:16 :: ASIC :: Replies: 14 :: Views: 5349
Please suggest good books in this thread for vhdl/Verilog ASIC design
ASIC Design Methodologies and Tools (Digital) :: 04-04-2002 05:12 :: antipattern :: Replies: 7 :: Views: 1950
The R4 are for current limiting, protecting in some way the PC rs232. Because of the high impedance of both input the current carried by the GND is little, so you don't need high power resistor.
Instead of 0.1 uF you can use 1uF in m@x232, I have already tried and everything works fine.
Professional Hardware and Electronics Design :: 05-04-2002 10:16 :: neuralc :: Replies: 4 :: Views: 1036
Tutorials for vhdl and Verilog.
HDL Synthesis for FPGAs: Design Guide (PDF 2MB)
SystemC -- Technical Papers
Cypress: Programmable Logic: vhdl Page
Cypress: Design Resources : Technical Articles
Logic Synthesis with vhdl System Synthesis
vhdl SYNTHESIS TUTORIAL
vhdl Coding Style manual (...)
Microcontrollers :: 05-09-2002 06:32 :: jimjim2k :: Replies: 5 :: Views: 3313
I am looking for any replacement for Am186ED + CS8900. (Because Am186ED stay obsolute)
Solution is preferable SIMPLE and LOW COST SoC with:
Ethernet 10Base-T (also 10/100Base-T is ok),
2 normal hardware UARTS (rs232),
2 x I2C (it is sufficient to emulate it by software)
1 x SPI (Sync full duplex serial controller, also sufficient software e
Microcontrollers :: 05-15-2002 15:56 :: dainis :: Replies: 19 :: Views: 6601
signal rd,dr : std_logic;
ad_bus,ram_bus : inout;
process(rd) ---- right.
if (rd='0' and dr='1') then
process(rd) ---- error.
if (rd='0') then
if dr='1' then
ASIC Design Methodologies and Tools (Digital) :: 05-19-2002 10:17 :: 75 sinfocia :: Replies: 9 :: Views: 1162
This object of this course is to introduce the student to more of the vhdl modeling language than what has been covered in previous courses.
1. -> t
Microcontrollers :: 06-09-2002 08:29 :: jimjim2k :: Replies: 0 :: Views: 1432
1. -> t
Microcontrollers :: 07-11-2002 03:09 :: jimjim2k :: Replies: 0 :: Views: 1451
1. -> t
Microcontrollers :: 07-11-2002 04:11 :: jimjim2k :: Replies: 0 :: Views: 1404
is there any software which convert matlab code to vhdl?
how can i get it?
PC Programming and Interfacing :: 07-13-2002 04:04 :: baa110 :: Replies: 32 :: Views: 15108