50 Threads found on edaboard.com: rs232 Vhdl
Would anyone share the rs232 vhdl code ?
If you have rs232 test program , please share.
Thanks a lot.
Other Design :: 30.03.2002 04:47 :: cssheu :: Replies: 11 :: Views: 13069
I have a Xilinx Spartan-3E and what i want to do is this:
Press a button ex. East Button on the board and send a signal eg. "00101100" to a device on the other end of Spartans rs232 port.
Like when i press the button and the leds are on i want to send this signal over the serial port lets say to a PC on the other end.
The only thing i have
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.07.2008 09:47 :: frid4y :: Replies: 5 :: Views: 8846
Doing Complete calculator in vhdl wont turn out to be economical design.
What you can do is you need to write / use some 8 bit vhdl CPU to do the job.
Using this cpu you can interface keyboard and display to it. And use it for doing
calculations also. 8051 core in vhdl is available you can use it. For testing you
can use (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.11.2004 02:20 :: nand_gates :: Replies: 1 :: Views: 4325
I am in need of source code of vhdl OF -- PS/2 and rs232 --Protocal!!
if you have it ,or you know how to program it in vhdl , please help me!:|
thank you very much!:D
PLD, SPLD, GAL, CPLD, FPGA Design :: 31.07.2006 21:45 :: vvsvv :: Replies: 1 :: Views: 1116
I am doing my final project in computer engineering and I need to connect a CMU cam into Ethernet.
I was thinking of building a hardware using vhdl which will transfer between the Camera's serial port to Ethernet (and the opposite of course).
Does anyone know where I could find such code?
ASIC Design Methodologies and Tools (Digital) :: 06.12.2007 07:23 :: liorbaz :: Replies: 2 :: Views: 1374
www.fpga4fun.com....and get verilog source code there
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.02.2008 06:40 :: amburose :: Replies: 7 :: Views: 18141
I assign both outputs and inputs of my uart vhdl codes to the 9 pins of that correct?? In the entity part of the uart vhdl code below, rx_data_out and tx_data_in are 8 bits width.I don't know how to assign them with the pin of rs232..anyone can help me??
entity uart_serial is
-- Global signal
PC Programming and Interfacing :: 11.09.2008 07:49 :: brunokasimin :: Replies: 1 :: Views: 1430
Does anyone have uart example of vhdl where i can test my rs232 on my board altium?
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.09.2008 05:48 :: brunokasimin :: Replies: 3 :: Views: 1321
hi , i didn2t want to open a new topic for this, thats way i write here, could you tell me which rs232(i think there are rs232 on different voltages) should i choose for FPGA, i also will implement uart.
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.12.2009 05:53 :: deniz88 :: Replies: 7 :: Views: 6729
This is really getting nowhere. Do you know ANYTHING about USB or FPGA at all?
First of all, Using USB to communicate between an FPGA and a PC is like trying to fly a 747 in order to go to your friends home next door.
USB is complicated, difficult and complex protocol and in NO WAY it is communicating in ASCII, unless you have a special devic
PLD, SPLD, GAL, CPLD, FPGA Design :: 15.01.2010 04:55 :: farhada :: Replies: 19 :: Views: 12014
Hi, im really new to this project and i dont know where to start. All i know is that i could use the hyperterminal for me to send data towards the FPGA... but i dont know how to do it... also the hardware stuff for the connection between the PC and FPGA... what i want is to make a simple project that sends data only towards the FPGA so that i could
PC Programming and Interfacing :: 19.01.2010 02:20 :: chimera086 :: Replies: 11 :: Views: 4470
I have a project using the Xilinx Spartan 3E starter kit board. Currently the project is used to measure the duty cycle of a signal and displays the value on the LCD. I would like to use uart so the user can see the value on the computer as well. Is this hard to do??
So far I have added the uart_tx and uart_rx vhdl code (kcuart_tx, kcuart_rx,
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.06.2010 16:37 :: ntropy :: Replies: 1 :: Views: 2516
you could create a memory with the values of the text file, generate it through IP wizard and read it. Every time that you want to read a image you have to modify your memory and recompile the entire project. This is like and "offline" solution.
Or, if you want to read "online" the text file, you could send the values through serial (rs232) cone
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.06.2010 16:55 :: mersault :: Replies: 43 :: Views: 6654
here is a good thread for it.. rs232 vhdl-core | Comp.Arch.FPGA |
maybe interesting.. i used it to do a part of my own UART
Electronic Elementary Questions :: 07.09.2010 03:45 :: Electro_Nic :: Replies: 5 :: Views: 1185
I want to check status of DIP switch conecting rs 232(DCE) in xilinx edk 11.1,
what will be my source code?
Analog Circuit Design :: 12.11.2010 02:45 :: rourabpaul :: Replies: 2 :: Views: 582
i need for a project to decode characters sent to rs232 Receiver module the RS 232 receiver will feed its data to the LCD display and that will be on spartan 3A .
i have the rs232 Receiver module done but what i am missing is the part related to the LCD display as i want one and i hope it is in vhdl and not relying on (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.11.2010 06:00 :: amronasr :: Replies: 9 :: Views: 1497
i had written uart receiver module and baud generator module for baudrate:9600 bps in vhdl. This code is working properly for all 1 digit values. Now i want to send a text file containing datas such as
eg: 123 56 234
175 34 100
how do i send this through rs232 to fpga???
Thank you all in advance..........
Electronic Elementary Questions :: 16.02.2011 05:27 :: lucky :: Replies: 0 :: Views: 919
We are trying to do some homework making a rs232 transmitter...
This is what we made so far and there is a lot of faults it it.. but we don't know what. We think its something with the way we written the states. Please rewrite it to some useful syntax
this is what we made so far
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.05.2011 13:50 :: Ivan-Holm :: Replies: 3 :: Views: 508
Hi, Since the DE2 board has rs232 and Ethernet, you can use either of these to interface with the PC.
Using rs232, from PC you can send / receive data with the help of hyperterm.
For using Ethernet, i think you have to use Embedded OS if your board supports this.
Now if you are looking for the FPGA to load the images from Hard disk directly, then y
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.07.2011 05:42 :: Iamventure :: Replies: 3 :: Views: 2324
I am using my FPGA(virtex-6) kit for the project,
project is rs232 to Ethernet converter,
1) i ll write a code for the rs232/434 and dump my code in FPGA then i need to transfer the data by Ethernet to other device or PC.
2) vice versa the data which is coming from the PC or device from the ethernet port need to be stored in the rs23
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.01.2012 02:25 :: manojb :: Replies: 1 :: Views: 811
some issues are apparent:
1.) rs232 is lsb first, so "z" will come up as 0 0101 1110 1.
2.) you appear to transmit "M" lsb first (correct), but the start/stop bits are swapped (incorrect). eg, x1(0) = '1' and x1(9) = '0'. Thus the framing will be incorrect. the receiver may see 11001001 as the data byte, which would be an extended ascii charac
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.04.2012 04:24 :: permute :: Replies: 1 :: Views: 389
I have a problem with rs232 transmission. It doesn't work even when i send the first, start frame($55). Next frame $3x choses a led and the last one turns it on/off. I cant even turn on a led when i get start frame. I cant find any mistakes in a code. Maybe You will find something or give some advice. I enclose code with a problematic part.
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.05.2012 03:38 :: lonerpl :: Replies: 1 :: Views: 255
I m working on a Altera DE2-70 board, and i need simple vhdl/verilog programs to make use of all the resources in the system.
The available resources are
? 2-Mbyte SSRAM
? Two 32-Mbyte SDRAM
? 8-Mbyte Flash memory
? SD Card socket
? 4 pushbutton switches
? 18 toggle switches
? 18 red user LEDs
? 9 green user LEDs
? 50-MHz oscil
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.06.2012 04:37 :: walker_iit :: Replies: 1 :: Views: 873
I need to implement an uart module written in vhdl to comunicate with another module, I have tried to use this code (source) with this main:
PLD, SPLD, GAL, CPLD, FPGA Design :: 31.01.2013 07:24 :: shedo :: Replies: 3 :: Views: 1103
I m trying to communicate between FPGA and my pc ( sending information for my fpga to my pc )
but i dont find the code of uart transmitter (vhdl) which will work exactly!!
I have to send 8 bits which will receive by an other programme of java.
thnx for help :)
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.05.2013 06:37 :: osama_hf :: Replies: 2 :: Views: 391
there appear to be a total of 64 elements in a small implementation and 4096 elements in the large implementation. What specifically are you expecting the vhdl to do?
for example, is this a simulation only construct?
is this a synthesizable construct?
how do you plan to put data into the structure? eg, data from a PC (ethernet/usb/rs232 interfa
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.06.2013 03:01 :: permute :: Replies: 6 :: Views: 286
Hi all ,
Iam doing a new project on FPGA . I used to make a port on the FPGA for debugging and connect it to PC using serial or parallel interfaces to debug the code while it's running using simple GUI (VB) .
Now I thought that , why don't I use the JTAG port which is implemented in the FPGA as a debugging port and make an intrface board to co
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.03.2004 07:33 :: Vonn :: Replies: 5 :: Views: 1528
i have spartan3 fpga starter kit from xillinx
i want vhdl or verilog code to interface with ps/2 and serial (rs232)
thanks for any help
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.11.2005 04:32 :: alieeldin :: Replies: 0 :: Views: 784
i have spartan3 fpg starter kit from xillinx
i want vhdl or verilog code to interface with ps/2 and serial (rs232)
thanks for any help
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.11.2005 18:51 :: alieeldin :: Replies: 1 :: Views: 802
i need your cpld suggestions for reading mpeg packets from digital satellite tuner. actually the task is very easy but i need speed.
- the tuner gives me 8 bit paralel data, clock and packet start output.
- every packet starts with hex47 and next 2 bytes identifies the packet.(PID)
- every data packet is 188 bytes total.
so now i have to
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.12.2005 18:47 :: orpheus :: Replies: 0 :: Views: 681
I'm trying to write a small program that sends data using USART (through rs232).
I don't have any hardware, only using the MPLAB IDE 7.20.
In the lab at the University we have the equipment and we use HyperTerminal to see the output, I was wondering if it could be done with the simulator at home.
Microcontrollers :: 10.04.2006 10:02 :: morag :: Replies: 2 :: Views: 1020
One side of my UART controller is on board rs232 traceiver,
will the other side of UART controller definetly needs a processor or DMA.
Can't I use the other side (lets say parallel 8bits)8bits to store directly into different
registers of my design in FPGA.These registers will be refreshed only at the
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.10.2006 22:44 :: samuraign :: Replies: 6 :: Views: 1639
Xilinx website contains some applications which use PicoBlaze ,
I thought that is a software , but when i downloaded it from website i found something called KCPSM3 .
I would like to know how to use it to build an interfaces for somethings like rs232 or ADC or DAC or PS2 ... for Spartan 3e Kit
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.06.2007 12:52 :: a_fetoh :: Replies: 2 :: Views: 1644
This is different to my last woes with a previous development board. Rather than confuse things, including myself, more, I though a new thread might be better.
I have built a couple of MicroBlaze cores with different settings for the board (RevD) using the BSB wizard with EDK 9.1.02i. I can get very simple things such as print("Something... Plea
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.03.2008 22:00 :: Rob B :: Replies: 4 :: Views: 2378
Using a LED as output, and acting on a digital input is the most basic application you could implement.
If you are looking for some 'communication' with the outside world, then a rs232 interface is probably one of the easiest to implement (both in software and hardware).
For the software have a look at this post:
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.08.2009 14:24 :: Marcel Majoor :: Replies: 4 :: Views: 1655
You can either send it serially for example with rs232 or send it parallel using timeplexing. There are more ways also.
Can you refer me to more info on timeplxing...
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.01.2010 16:37 :: lmtg :: Replies: 8 :: Views: 2480
i have spartan 3E fpga kit and i want to store image on it in order to do some digital processing on it.
knowing that : this kit include that : plat form flash also SDRAM
and i do not know what is the best way. using RAM or FLASH to store image
and how can i store it , is this by rs232 from PC to fpga kit? or
is this by vhdl code
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.09.2010 10:50 :: hodahussein :: Replies: 9 :: Views: 5570
hi guys i need help for using hyperterminal in win xp for interfacing to fpga.
i'm a novice and i hav a few questions that in not clear about:
1. when i click on send text the entire text file transmitted or is it a single character.
there any commands to be used in hyperterminal for transmitting single charac
PLD, SPLD, GAL, CPLD, FPGA Design :: 14.04.2010 13:17 :: electronic_jas :: Replies: 0 :: Views: 999
I am trying to send a command followed by a set of data through the serial comm.
E.g. The application from the PC writes char "S1000E" to the serial. The FPGA UART receives this as "S" "1" "0" "0" "0" "E" (I have it write back to HyperTerminal). In ASCII, "1" = 31(hex) or 49(dec) or 11001(bin).
The question is... how do I store the value 1000(d
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.04.2010 17:40 :: blueice2 :: Replies: 1 :: Views: 2609
Hi all I'm a beginner to FPGAs and vhdl. I have a project in which the FPGA is to be used as an arbitrary waveform generator. The FGPA I'm using is the Xilinx Spartan 3A DSP 1800 board.
The idea I have for implementing this is to generate the required waveform from another program, e.g. Matlab, and send the generated values of the waveform into
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.06.2010 03:22 :: oldfoggy :: Replies: 0 :: Views: 1497
isnt this just node based rs232
old hat stuff?? 432 made a better job for serial stuff
as for network
man as above the right foldback cables ,,,
if you want three way rxtx on urban systems no cpu and network based
you need to use i2c
to solve this using midi to rs232 properly i had to use 2 micros per i/o
to provide 0 latency and
Network :: 02.01.2011 11:02 :: VSMVDD :: Replies: 4 :: Views: 623
Not quite sure what the problem is, but since you mention rs232 ...
Check out this uart module on fpga4fun. It's explained pretty well, and more importantly, it actually worked the first time around! Just change clock frequency and baud rate parameters and you are good to go!
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.12.2010 12:06 :: mrflibble :: Replies: 3 :: Views: 463
Thanks for reply!
If use UART, I have to use rs232 right? Since my laptop don't have rs232 port, can I use the converter rs232 to USB? If can, will the data transferring speed become very slow?
PLD, SPLD, GAL, CPLD, FPGA Design :: 12.01.2011 10:35 :: doremifaso :: Replies: 6 :: Views: 1699
i'm doing m.tech project on implementation of hdlc procedures on fpga...
i did vhdl coding for the same......
i'm using spartan 3e fpga kit.........
the output is serial data....
i need to show the output in CRO by connecting rs232 cable from SPARTAN 3e to CRO......
coding has been downloaded into spartan3e by using xilinx ISE tool.....
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.04.2011 08:12 :: devendra saikumar :: Replies: 1 :: Views: 519
It is receiving data from a gyroscope, the format is a synchronized signal, when the gyro-clock has pulses the data is valid. A whole frame is 32 bits. then the clock goes zero for a little period.
The data is saved to a vector and it's sending the data through rs232 format to a computer.
The question is that it should only send after receiving a
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.05.2011 13:51 :: fredrichodie :: Replies: 2 :: Views: 1095
it is possible where possible. Ethernet has a fairly wide range of PHY's. so things like 1000BaseLX, an optical standard, would still require an external PHY. Really, 1000BaseT would need an external PHY as well due to the multi-level signalling requirements. 1000BaseX can be done, but that is more for interchip communications.
the same even f
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.05.2011 10:26 :: permute :: Replies: 3 :: Views: 729
Mplab Sim is able to generate complex waveforms, emulate external hardware, simulate complex serial protocols, verify response of algorithms and detect errors, analyse system latency and real-time response to stimulus, and more.
A not very well documented aspect of mplab sim is its support for SCL, the Stimulus Control Language.
You can find a
Microcontrollers :: 28.05.2011 05:09 :: btbass :: Replies: 5 :: Views: 588
Hey guys, I'm trying to write a code of SPI, and I have 0 experience in this :
The device needs to be designed to provide translation between the rs232 and SPI protocols in
either one of the following modes:
? A1 is a rs232 receiver. It will receive a serial bit-stream from a PC and perform the
necessary error checking on the data. It will th
PLD, SPLD, GAL, CPLD, FPGA Design :: 24.07.2011 16:14 :: LoyC :: Replies: 1 :: Views: 1496
You need an UART of some sort, be it USB or rs232. It dependeth on the required bandwidth.
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.02.2012 21:06 :: mrflibble :: Replies: 5 :: Views: 689
Agreed. A serial interface is a good way to get started. The rs232 code on fpga4fun Just Works so you can concentrate on other stuff... You only need to assign the RX/TX IO's in your top level design, change the baudrate and you're good to go.
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.06.2013 08:57 :: mrflibble :: Replies: 7 :: Views: 372