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6 Threads found on edaboard.com: Rtl Compiler Start
Why don't you debug right from the start, including the rtl startup code? You say, there are no compilation errors or warnings and all compiler listings and memory maps look fine?
By using rtl compiler i synthesized a design and reported it's worst path by the command report timing -worst 200000 -summary > file_location it dumps a file approximately containing 169379 path with slack -2988ps. is there any command to categorize these path according to path groups or cost groups?? my requirement is to dump paths with
hai all, plz check and correct steps to create memory block 1) i started rtl coding size of RAM design is datawidth=8,addresswidth=8 2) next steps i start with DESIGN compiler from that i generated RAM netlist,sdc,sdf 3)using RAM netlist,sdf,sdc as input to PRIMETIME from that i generated .lib,.db files (...)
hai all, plz check and correct steps to create memory block 1) i started rtl coding size of RAM design is datawidth=8,addresswidth=8 2) next steps i start with DESIGN compiler from that i generated RAM netlist,sdc,sdf 3)using RAM netlist,sdf,sdc as input to PRIMETIME from that i generated .lib,.db files (...)
Check out for free HDL implementations of various processor architectures. If you have never done a CMOS run or don't have access to uber-expensive ASIC design tools you can start by using free FPGA tools and later switch to Alliance CAD which comes with a free VHDL-to-rtl compiler
Q1. What's the max gate number (limit) for DC(can handle ) and for RCC(can handle )? Q2. I start to use RC compiler(Encounter rtl compiler ), anyone can share the RC compiler training material/tutorial (with lab is better)? tks in advance!