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22 Threads found on Rtl Ram
Hi, Can you please tell me how to use those files(rtl,SIM) in EXAMPLE CODES. How to write Data From pc -> fpga ddr3 ram (with reference to ) Regards, Devi
Hi all, I had used Xilinx CoreGen for block ram generation, then have used the instantiation of it in my design. This ram is working fine for read and writes - proven in rtl sim. What I want now is to dump out this particular ram's addresses and its contents correspondingly as this memory is accessed. This is want to (...)
Just like TrickyDicky said, use the templates as stipulated in the coding guidelines aka Xilinx Libraries Guide in your case. And to verify that what you get from the synthesizer is what you intended, you can check the results with "View rtl Schematic" and "View Technology Schematic". I always find those quite useful when I am not entirely sure the
Hi, I have technology library for 2048x32 ram and I want to use it with my VHDL design in Cadence rtl compiler. This library contains *.lib flies and VHDL simulation model. When I include this ram as a component in my VHDL code the rtl compiler interpret it as a black box. Do I need a VHDL file for this (...)
Totally new to verilog, working on a HW project where I'd have to design a single port ram that is 8 bits wide and has 16 memory locations. The description is as below; Write rtl description and testbench for the Single Port ram, which is 8 bit wide and has 16 memory locations. The data can be written on a memory location by providing (...)
What kind of PC/Workstation do you use for ASIC or FPGA design works ? I have used dell Vostro 430 for FPGA design( rtl logic simulation, synthesis, FPGA implementation) - i7-860(2.8G) - 8G ram - 1T HDD Now I am considering to upgrade PC to speed up my work. So I would like to know what kind of PC/Workstation other people use. Thanks, The idea of performing LEC is do a verification of rtl with the GLN (Gate Level Netlist) after synthesis. Hence during synthesis the memory models are not synthesized and are only macros hence to avoid their compare all memories, analog blocks and non-synthesizable constructs rtl constructs are treated as notranslate. Also your (...)
rammodule ram (addr, clk, din, dout, we); input addr, din; input clk, we; output dout; reg memory; reg dout_r; always @(posedgeclk) begin if (we) memory <= din; dout_r <= memory; endendmodule I think the above code is a behavioral code of a ram. How can we write a
HI i have some questions regarding the verilog validation. I have known that the Behavioural model is just checking the functionality of the circuit. Since im working in Sram, the customer asked me to validate the timings specified in the ram document? Is this part of rtl validation or is it related to circuit validation. (...)
Bram is just standard Xilinx Block ram. Look at the the Xilinx datasheet for Bram to get an idea of the timing diagrams for reading and writing. Then write an rtl module that takes the serial SPI data and then writes it to the Bram as parallel data.
This paper explains the fundamentals of the dual clock FIFO. Although the rtl is verilog, the theory will the useful.
Hi, I'm doing Equivalence Checking between the rtl and the Netlist of a design, which has 4 ram IPs. Of course, I can't use the behavioral HDL models of the rams since they're only used for simulations! So, what should I do now in order to verify the design?! Should I mark the rams as black boxes, or just use their (...)
I need to synthesize Instruction and Data memory modules. How can it be modelled in rtl using Verilog. In fact for behavioral memory modelling I use reg array_name
Hello guys ~ I would like to know: Is there any tools that can transform gate-level verilog netlist TO rtl verilog netlist? Your guidance is highly appreciated !! Will
hai all, plz check and correct steps to create memory block 1) i started rtl coding size of ram design is datawidth=8,addresswidth=8 2) next steps i start with DESIGN COMPILER from that i generated ram netlist,sdc,sdf 3)using ram netlist,sdf,sdc as input to PRIMETIME from that i generated .lib,.db files (...)
hai all, plz check and correct steps to create memory block 1) i started rtl coding size of ram design is datawidth=8,addresswidth=8 2) next steps i start with DESIGN COMPILER from that i generated ram netlist,sdc,sdf 3)using ram netlist,sdf,sdc as input to PRIMETIME from that i generated .lib,.db files (...)
Target Library is the library, which you will use to 'map' your rtl onto. There can be multiple target libraries. where as link library is the library, which you may use to 'link' sub modules of your design such as ram/rom etc. dc will use the operating conditions, from the target library. you can set the oprating conditions by using set_operatin
You can only synthesize rtl codes .. Memories are not designed obeying the rtl flow .. Memory suppliers do supply memory models, through what usually called Memory Compilers .. What you do is to decide which memory type and size you need to have in your design .. go to the memory compiler and get the model .. simulate your design, and when
Digital designer today use synthesis tools and rtl description of design. For simulation he uses Verilog or VHDL models. They don't need to know device physics. ram designer more close to analog because he used Spice-like simulator and Spice models. Unlike analog designer he never will run AC analysis. But he should develop and verify Verilog or
Mentor Mbistarchitecture is powerful tools to give memory bist logic in rtl format. It is readable. You can design memory BIST circuit by a LFSR and PREG, It is two FSM. You can see any DFT book. And you can refer synopsys DW_rambist about the memory bist arch. For test algorithm and fault model, please search in IEEE or google. There are l
q:how to couple with the ram/rom in primetime?? i write blank modules for ram/rom in rtl netlist.After synthesis and P&R,i generate a postlayout gate netlist from Apollo.Read the postlayout netlist into Primetime,i find the ram/rom is still black box.i think the timing infromation of the ports in (...)
for ADC, if you means your synthesis is tranlate behavior rtl to netlist. i am afraid you can't. your lib may be only the GDSII lib or some abstract model. those don't not include the enough info to DC . but you can instance those modules in your design then link them in DC if you have the DC lib formats of your ADC. for ram. you can do the