1000 Threads found on edaboard.com: Run Spectre Simulation Cadence
I have a downloaded a PSpice model file (in .lib) from On Semiconductor.
I am wondering how to run spectre simulation in cadence with this file. For the same diode, there are .sp2 and .sp3 models are available as well. Am I using the right one (.lib) for spectre simulation?
Analog IC Design and Layout :: 06-18-2009 18:10 :: florescent :: Replies: 6 :: Views: 3044
I want to run spectre simulation of transformer, how can I add following characteristics into my spectre simulator to run the simulation properly?I found only turns ratio of default xfmr device can be modified.
Open-circuit inductance: 1.2mH
Inter-winding capacitance: 35pF (...)
Analog Circuit Design :: 05-06-2008 23:21 :: eda_range :: Replies: 0 :: Views: 476
If you use hspice simulator(you can choose simulator in cadence enviroment if you have such license), you can run simulation directly with hspice model. Otherwise you need spectre model, which is quite different format from hspice.
Analog IC Design and Layout :: 04-05-2006 23:50 :: hk2004 :: Replies: 9 :: Views: 1981
Do you really have the license to run spectre simulator?
Analog Circuit Design :: 03-26-2007 16:50 :: nxing :: Replies: 5 :: Views: 2137
In the Results Display Window of noise summary in cadence spectre simulation, there is a list like the following:
Device Param noise distribution % of total
/M0 id 1e-7 40
/M0 fn 2e-8 8
I want to know what's the meaning of the param. In other word, what kind (...)
Analog IC Design and Layout :: 01-09-2006 12:44 :: freewing :: Replies: 3 :: Views: 5685
I want to run a simulation using cadence(icfb). The simulation should show time transient result with a time varing resistor value. Basically, I want to assign the value of resistor as res = sin( w* time) + some offset. Is there any way to do this?
The value of the resistor should vary along with the time (...)
Analog Circuit Design :: 04-25-2006 06:58 :: tsb_nph :: Replies: 28 :: Views: 7496
I have a question regarding some parameter setting for transient simulation with spectre. there are two parameters : step and max step, are used to control the time step, but after run the simulation, I do check the data step and it corresonds to none of them. Cany anybody tell me how to really control the (...)
Analog Circuit Design :: 09-14-2006 14:54 :: nxing :: Replies: 1 :: Views: 469
Now I have done lpe for the layout, then I get the netlist of SPICE.DAT.
I use spectre for simulation. But I don't know how to use it for post-simulation after I get the netlist.
Can you help me, or please give me some usefull way to simulation the netlist from LPE. Thank you!
Analog IC Design and Layout :: 07-14-2007 07:55 :: zgz1983 :: Replies: 3 :: Views: 2676
Dose anybody know how to simulate the dc current with spectre in cadence?
I can only see the voltage of every net, and can not see the DC current.
Software Requests :: 04-24-2009 22:17 :: mustangyhz :: Replies: 1 :: Views: 447
I got some problems confusing me a long time. Can anybody help me? Thank you very much.
When doing spectre simulation, some fatal errors occur as follows:
-env artist5.1.0 (...)
Software Problems, Hints and Reviews :: 08-24-2009 23:49 :: xxgeneral :: Replies: 0 :: Views: 1270
I designed a comparator in a transistor level.
I connected the comparator to a digital logic gate, like inverter or AND gate from the NCSU_Digital_Parts.
But whenever I use the logic gate, It gives me an error.
My question is,
1. Can I use digital logic gate in spectre simulation?
2. How can I fix this error message?
Analog Circuit Design :: 12-01-2011 23:26 :: Giveitatry82 :: Replies: 1 :: Views: 921
How to install the SiMKit library(Philips) for spectre in cadence IC_50?
Analog IC Design and Layout :: 06-08-2004 09:09 :: rfic :: Replies: 1 :: Views: 1441
for example, in Hspice
"ecmfb vcmfb vss poly(4) vb1 0 vcmref 0 vop 0 von 0 0 1 -1 0.5 0.5"
is function as a idesl CMFB block
Similarly, Can I use the ideal CMFB block in spectre simulation?
What's the name of that block
Analog Circuit Design :: 05-02-2007 01:40 :: pinhead :: Replies: 0 :: Views: 1033
when i start spectre simulation, the it often shows "Greated directory input .ahdlcmi(770),compiling ahdtcmi modeule library'in the beginning of the output log file. what is really mean of the sentence in my simulation ?
Analog Circuit Design :: 08-13-2008 01:35 :: jeremy_zhu :: Replies: 0 :: Views: 785
Foundary gave us a .pm3 model, can anybody tell me how to use it in a spectre simulation. Thanks in advance!
Analog IC Design and Layout :: 01-14-2009 20:23 :: jianjing526 :: Replies: 0 :: Views: 508
Does anybody know how to simulate the low pass filter with spectre in cadence?
Software Requests :: 05-05-2009 08:36 :: mustangyhz :: Replies: 0 :: Views: 346
When I run spectre simulation in cadence, I get an error message.
The error is for Schottky diodes. From NCSU CDK package (I am using AMI06, I bring Schottky diodes in Schematic and run)
The error is that it requires to use of a model for Schottky diodes. I think I need a model file or at least (...)
Analog IC Design and Layout :: 06-12-2009 00:53 :: florescent :: Replies: 0 :: Views: 1070
when doing spectre simulation(IC5141, mmsim 7.1 version), there exist the following warnings and notice:
1\WARNING(CMI-2114):Define Q:Unit of quantity 'Q' is changed from 'coul' to 'C'
2\WARNING(CMI-2114):Define Freq:Unit of quantity 'F' is changed from 'N' to 'Hz'
3\Notice from spectre during IC analysis, during transient analysis 'tran' (...)
Analog Circuit Design :: 11-16-2009 06:02 :: lhlbluesky :: Replies: 3 :: Views: 2323
How can I use instances from bmsLib, which have veriloga and verilogams views, in a spectre simulation? I added veriloga and verilogams to the beginning of my switch view list and the circuit netlists without warning/error, but the state of the instance does not change when an input is given. I can't even get an inverter to work. Do i have to use i
Analog IC Design and Layout :: 11-30-2009 17:21 :: oermens :: Replies: 2 :: Views: 1058
700V MOSFET 0f TSMC. When I use 700V MOSFET model in spectre. Error of spectre simulation is that 'hisim_hv' is an undefined primitive device.
When I exchange "hisim_hv" with "hisim" in process file of TSMC, warning of spectre simulation is that 'xqy' is not available in HISIM1.0.1, and error occurs (...)
Power Electronics :: 09-28-2010 04:43 :: bean123 :: Replies: 1 :: Views: 762
Hi,when i run my simulation modelled by simulink and matlab it displays an error" The periodic sample time 1 is not allowed because the ratio of this sample time over base rate (1.01010101010101e-014) is greater than the maximum value of uint32".Can you please help how to fix this problem?Thanks alot!!!
Digital communication :: 02-27-2012 04:47 :: yilmataye :: Replies: 0 :: Views: 490
I m currently using VCS for functional simulation. My testbench toplevel contains a parameter for a data input file that should be streamed into my model under test. To control this I use 'vcs -gfile foo.dat' to overwrite the parameter at compile time.
Now I want to run my simulation with several input files (up to 20 inputs (...)
ASIC Design Methodologies and Tools (Digital) :: 03-06-2012 07:36 :: hbeck :: Replies: 0 :: Views: 424
After installing IC5141 on Redhat ES3, I can run icms on C-shell, with the following message:
Incorrectly built binary which accesses errno or h_errno directly. Needs to be fixed.
Then, when I tried to run spectre simulation in Analog Artist, I get the following warning/error message also:
Error: Unable to (...)
Linux Software :: 03-29-2006 02:16 :: willyboy19 :: Replies: 0 :: Views: 1123
I am using Verilog-A to generate a carrier-frequency stimulus to an power amplifier in virtuoso schematics, but saw a mysterious frequency shift in the stimulus when I run spectre simulation. It reduces to a basic test case where,
parameter real omega = 2* `M_PI *20e9;
V(pure_sine) <+ sin(omega * $abstime);
V(test) <+ (omega * $a
ASIC Design Methodologies and Tools (Digital) :: 04-19-2011 13:52 :: zhipeng :: Replies: 0 :: Views: 458
I have the verilog code for the sigma delta modulator and the PLL circuits in cadence. How can I run the co-simulation on the whole PLL including the PLL circuits and the verilog code?
Analog Circuit Design :: 02-27-2006 19:45 :: eejli :: Replies: 4 :: Views: 1681
go to your results folder/design/schematic/spectre/netlist and type .runsimulation
Analog IC Design and Layout :: 08-18-2009 17:19 :: oermens :: Replies: 13 :: Views: 6732
I want to use corners to simulate circuit in different technics, like tt,ff,ss,etc.
But many items under the corner window is dark, which means there are some file unsetup, I guess.
Is there any body know such situation? what files I need to setup in spectre before I run corners simulation?
THX a lot!
ASIC Design Methodologies and Tools (Digital) :: 08-31-2010 04:53 :: iiiiisland :: Replies: 6 :: Views: 1647
Why not using spectreVerilog run the simulation. it can also seperate digital and analog part to run a mixed-signal simulation. you can refer to openbook.
Analog Circuit Design :: 04-13-2004 08:20 :: piao :: Replies: 1 :: Views: 1920
No idea how to run it from the command line. Always use analog artist. Why don't you use it, too?
Analog Circuit Design :: 08-13-2004 00:13 :: sutapanaki :: Replies: 12 :: Views: 6450
I have problem using spectre in cadence. when I choose the simulation environment as spectre, it says that first I need to convert spectre siminfo from spectreS (basically convert spectreS models to spectre models) using the conversion toolbox, but when (...)
Analog IC Design and Layout :: 08-02-2005 08:39 :: ASICK :: Replies: 0 :: Views: 635
When I run the simulation , several errors were found like this:
"input.scs" 32 : function 'pPar' is undefined or is used recursively
cadence IC version is 5033 in my notebook ,in our lab it's the same ,but it run quite well,how can i do?Is there any Configuration problems?
please help me , I have tried many ways (...)
Software Problems, Hints and Reviews :: 03-30-2006 01:11 :: kevinlin :: Replies: 4 :: Views: 1708
You actually do not need to write all the script. You can make cadence enerate the script then modify it to include your own loops to sweep on the corners.
To generate the ocean script from cadence. In the Analog Design environment choose:
Session -> save script
Then go to the file, and place your model file inside the loop, changing the c
Analog IC Design and Layout :: 05-17-2006 12:00 :: elbadry :: Replies: 6 :: Views: 3176
I run my simulation with spectre of cadence. One diode i wish
to use is only .scs file and no symbol with it.
You know the simulation flow is usually draw schematic first and
add stimi, then evoke spectre and run simulation. (...)
Analog IC Design and Layout :: 01-23-2008 08:38 :: fxxjssc :: Replies: 5 :: Views: 4248
there is no fft in spectre ther is dft which you can use first you need an ideal dac you can write the dac equation on the calculator (weight each bit) then you run SFDR simulation you enter a full sine wave and put the ideal dac behind the adc and take
dft for the output
Analog Circuit Design :: 06-21-2008 15:24 :: mahgoub :: Replies: 1 :: Views: 1963
so what is the problem?
Is it due to old version of IC5?
can I run this PDK on IC5?
I mean if it should be used for IC184.108.40.206 and later, can i run in a compatibility mode for ic5?
thanx in advance,
Software Problems, Hints and Reviews :: 05-21-2010 18:54 :: mohamedabouzied :: Replies: 5 :: Views: 4136
I am learning to run a design using AMS simulator with spectre solver. The set up looked fine and the netlist was generated without any problem. But when I run the simulation, I am getting the following error message:
Failed to elaborate ("amsPLL" "pll_160MHZ_sim" "config").
How can I resolve this. Please help. (...)
Analog IC Design and Layout :: 02-04-2009 04:07 :: sunil_rpine :: Replies: 3 :: Views: 1362
I currently use spectre simulation in cadence. I am wondering if there is any method to run the spectre simulation with layout only.
It's simple and no problem to run the layout simulation if based on its schematic or symbol. My question is to (...)
Analog IC Design and Layout :: 07-07-2009 14:45 :: florescent :: Replies: 3 :: Views: 967
when i extracted PEX netlist (for ex: circuit1.pex.netlist)using calibre, how to run simulation with the PEX netlist in spectre (ic5141)? what is the procedure?
In input.scs, i delete the netlist part (with no parasitic parameters), and include the PEX netlist (for ex: include ./circuit1.pex.netlist), then run the (...)
Analog Circuit Design :: 10-12-2009 07:39 :: lhlbluesky :: Replies: 1 :: Views: 2437
Hi, I'm using spectre to simulate my analog circuits. But the circuit is slightly complex.
When I run transient analysis for 2 us, the output file (named tran.tran.trn) is as large as 40G. So I set software output time to 1.5 us.
Then the output file is much smaller. However, when I plot some signals to verify the simulation result, (...)
Analog IC Design and Layout :: 01-17-2010 20:52 :: liqiyue :: Replies: 3 :: Views: 1121
I have simulated a fixed geometry 6-port transformer in Momentum and I have the s6p file. How may I import this into cadence to do spectre simulation?
I used the Nport element in analog lib and mounted the s6p file with it. But the DC simulation in spectre does not give expected result. I guess for DC, (...)
RF, Microwave, Antennas and Optics :: 12-13-2010 07:16 :: wht4665453123 :: Replies: 1 :: Views: 1058
I have a testbench-schematic for an
If I start cadence and open this schematic and ADE GXL with the related adexl view and I run the simulation everything is alright. But if I subsequently "Check a
Software Problems, Hints and Reviews :: 10-11-2013 04:15 :: Dr. von Rosenstein :: Replies: 3 :: Views: 963
hai to all,
can we tune the parameters of LNA in cadence spectre like we doing in ADS???
RF, Microwave, Antennas and Optics :: 11-07-2013 01:34 :: gold :: Replies: 2 :: Views: 179
I'm doing DC sweep simulation with cadence 5141. Now I've got V1~VX plot and V2~VX plot, from which I want to obtain the V1~V2 plot. How to do this?
I know that this is possible through exporting the data to MATLAB or Origin and replot, but can I do it with cadence spectre? THANKS
Analog Circuit Design :: 04-01-2014 01:08 :: czq1419 :: Replies: 0 :: Views: 189
I am now do a SAR ADC design and need to do mixed-signal simulation on my design.
The digital part of the circuit is descripted with VerilogHDL at RTL level. And then I make it as a symbol and integrated into a schemetic with analog part. The stimulus to digital part is descripted with verilogHDL and the stimulus to analog part is directly adde
ASIC Design Methodologies and Tools (Digital) :: 09-14-2003 09:19 :: hoteagle :: Replies: 0 :: Views: 1472
I have a question about co-simulation of extracted view and schematic view. My question can be very dumb, but if you know anyting about this issue, let me know.
My situation is this. I draw a schematic and it is a componet of higher schematic. I also did layout. After that, I run extracter and got the extracted view.
What I wan
ASIC Design Methodologies and Tools (Digital) :: 04-25-2004 20:06 :: jjang :: Replies: 2 :: Views: 955
Long ago, I have run the simulation about mixed signal. I remember that the most important thing is to generate a "config" part, which can combine the digital part and analog part. Detailed information can be found in the manual.
Analog IC Design and Layout :: 06-03-2004 22:54 :: flyinspace :: Replies: 3 :: Views: 1251
Read Ken Kundert' s paper at - the tricks of simulation are perfectly expressed there. He also provides the files for an example, you can learn how to run spectre from there (although you'd still better find cadence documentation..)
Analog Circuit Design :: 10-28-2004 19:28 :: borodenkov :: Replies: 4 :: Views: 1638
I?m simulating a Sampling and Hold circuit, which has 14 bit resolution. The simulator is spectre. When I set ?accuracy (errpreset)? to ?moderate?, the result (after DFT of transient simulation results) shows about 12 bit resolution. However, after setting ?conservative?, it has about 14 bit performance. My question is, which result is more reliabl
Analog Circuit Design :: 09-23-2004 04:14 :: hspice :: Replies: 3 :: Views: 2350
For the cadence spectre simulation using BSIM3 model, does the capacitance in the DC operating point result such as Cgs, Cdg already include the overlap capacitance? i.e., does the value add both intrinsic device capacitance and parasitic capacitance?
Analog IC Design and Layout :: 10-04-2004 22:52 :: tumati :: Replies: 1 :: Views: 2432
How to run mixed-signal simulation without cadence graphic interface?
I use cadence4.x to run circuit simulation.You know,when successfully run the simulation once,the tool automatically create a executable file named 'run????',wherr ???? (...)
Software Problems, Hints and Reviews :: 10-18-2004 01:40 :: joskin :: Replies: 0 :: Views: 765