151 Threads found on edaboard.com: Run Spectre Simulation Cadence
I have a downloaded a PSpice model file (in .lib) from On Semiconductor.
I am wondering how to run spectre simulation in cadence with this file. For the same diode, there are .sp2 and .sp3 models are available as well. Am I using the right one (.lib) for spectre simulation?
Analog IC Design and Layout :: 18.06.2009 18:10 :: florescent :: Replies: 6 :: Views: 2607
If you use hspice simulator(you can choose simulator in cadence enviroment if you have such license), you can run simulation directly with hspice model. Otherwise you need spectre model, which is quite different format from hspice.
Analog IC Design and Layout :: 05.04.2006 23:50 :: hk2004 :: Replies: 9 :: Views: 1682
I want to run a simulation using cadence(icfb). The simulation should show time transient result with a time varing resistor value. Basically, I want to assign the value of resistor as res = sin( w* time) + some offset. Is there any way to do this?
The value of the resistor should vary along with the time (...)
Analog Circuit Design :: 25.04.2006 06:58 :: tsb_nph :: Replies: 28 :: Views: 5510
Do you really have the license to run spectre simulator?
Analog Circuit Design :: 26.03.2007 16:50 :: nxing :: Replies: 5 :: Views: 1848
Why not using spectreVerilog run the simulation. it can also seperate digital and analog part to run a mixed-signal simulation. you can refer to openbook.
Analog Circuit Design :: 13.04.2004 08:20 :: piao :: Replies: 1 :: Views: 1642
I need to add a save statement in the cadence netlist that will give me a direct plot of power dissipated. If I goto the netlist file and add this statement and run it using the analog artist GUI, the netlist goes back to its original state( save :pwr statement is not saved). Is there any other way to change the netlist and run the (...)
ASIC Design Methodologies and Tools (Digital) :: 25.04.2004 16:08 :: knataraj :: Replies: 3 :: Views: 1260
I have a question about co-simulation of extracted view and schematic view. My question can be very dumb, but if you know anyting about this issue, let me know.
My situation is this. I draw a schematic and it is a componet of higher schematic. I also did layout. After that, I run extracter and got the extracted view.
What I wan
ASIC Design Methodologies and Tools (Digital) :: 25.04.2004 20:06 :: jjang :: Replies: 2 :: Views: 751
No idea how to run it from the command line. Always use analog artist. Why don't you use it, too?
Analog Circuit Design :: 13.08.2004 00:13 :: sutapanaki :: Replies: 12 :: Views: 5430
run the simulation,
Hit op button - little popup will (should) appear. Select on schmatic the device you are interested in and the in pulldown menu list in the pop-up select gm.
Then hit plot in calculator.
Analog Circuit Design :: 05.01.2005 19:22 :: Teddy :: Replies: 9 :: Views: 3281
Read Ken Kundert' s paper at - the tricks of simulation are perfectly expressed there. He also provides the files for an example, you can learn how to run spectre from there (although you'd still better find cadence documentation..)
Analog Circuit Design :: 28.10.2004 19:28 :: borodenkov :: Replies: 4 :: Views: 1361
You can run spectre from Analog Artist by selecting the spectre (not spectreS) simulator.
Analog Circuit Design :: 25.11.2004 21:28 :: Hughes :: Replies: 14 :: Views: 1790
cadence Analog Artist has an option "Corners" for a corner analysis.
It works like a more complex parametric analysis.
You need to defind a path for your corner models and run Corners Analysis.
As a result you'll get a set of curves for different corners.
Open "Analog Design Environment " window, choose "Tools", "Corners" and get "Co
Analog Circuit Design :: 14.01.2005 04:48 :: uladz55 :: Replies: 6 :: Views: 3204
I run spectre with command "spectre aaa.scs" not in cadence ADE
and got the result file tran.tran.
How can I open this file to view some waves? By which tool?
Analog IC Design and Layout :: 22.02.2005 21:10 :: flushrat :: Replies: 4 :: Views: 1954
What's your digital part seems like? Do you write it with verilog. If this right,you should setup your digital part in "behaviral" view and run with "spectreverilog",Or you can run with spw. The process is quite similar.
Hope this helpeful.
Analog Circuit Design :: 02.05.2005 23:00 :: hanm :: Replies: 8 :: Views: 1069
I have problem using spectre in cadence. when I choose the simulation environment as spectre, it says that first I need to convert spectre siminfo from spectreS (basically convert spectreS models to spectre models) using the conversion toolbox, but when (...)
Analog IC Design and Layout :: 02.08.2005 08:39 :: ASICK :: Replies: 0 :: Views: 547
I have problem using spectre in cadence. when I choose the simulation environment as spectre, it says that first I need to convert spectre siminfo from spectreS (basically convert spectreS models to spectre models) using the conversion toolbox, but (...)
Software Problems, Hints and Reviews :: 03.08.2005 09:37 :: ASICK :: Replies: 0 :: Views: 479
Invalid command character following '[' in: ' type=pwl
si:simin didn't completely suessfully
I am trying to simulate my design using a text stimulus file in spectre. I
included this file in the Stimulus File field via Setup -> simulation files from
the ADE window. My stimulus file contains
Analog IC Design and Layout :: 19.10.2005 23:19 :: alchen77 :: Replies: 1 :: Views: 1170
a) do you really have 5 cpus in host 3?
b) is it host 8 or host 3?
c) I recommend to kill ANY CDS application - from my experience it does not work when any cds app runs - recommend kill -9 -1
d) I do not run it as a root. Despite what the documentations says and also to big surprise of cadence help line - you can run (...)
Analog IC Design and Layout :: 01.12.2005 22:31 :: Teddy :: Replies: 2 :: Views: 1460
checkSysConf cadence IC version number>
in the command prompt. If the command runs successful then there is no problem. If it doesnt then probably u wont be having the necessary patches to run spectre. It will specify all the patches that u dont have. Install all the patches and run the command again.
Analog IC Design and Layout :: 16.01.2006 01:18 :: Chethan :: Replies: 1 :: Views: 978
I try migrating to BJT by reading the textbook by Gray & Meyer. simulations should be the best way to get an insight into the methodologies.
But I need advice on the starting point, say, on how to run simulations in cadence. I don't know what Vcc I should choose for the supply, how to size the transistors, etc...
Analog Circuit Design :: 16.01.2006 22:38 :: EMfox :: Replies: 1 :: Views: 626
I have the verilog code for the sigma delta modulator and the PLL circuits in cadence. How can I run the co-simulation on the whole PLL including the PLL circuits and the verilog code?
Analog Circuit Design :: 27.02.2006 19:45 :: eejli :: Replies: 4 :: Views: 1468
When i use simulation by spectre,there's an error.
Error found by spectre during hierarchy flattening
V1:Waveform type must be specified if any waveform parameters are given.
It's seem as the Independence source,just like(Vsin,Vpluse and so on)
How did you run spectre? Did you run (...)
Software Problems, Hints and Reviews :: 17.03.2006 19:06 :: Hughes :: Replies: 14 :: Views: 4671
You probably know where you place .scs file.
You should define the path in analog environment.
I do this each time i run the simulator , i need to efine the paths of the model to the simulator to use it by itself each time i run a simulation
Analog IC Design and Layout :: 23.03.2006 01:14 :: ashi :: Replies: 4 :: Views: 867
When I run the simulation , several errors were found like this:
"input.scs" 32 : function 'pPar' is undefined or is used recursively
cadence IC version is 5033 in my notebook ,in our lab it's the same ,but it run quite well,how can i do?Is there any Configuration problems?
please help me , I have tried many ways (...)
Software Problems, Hints and Reviews :: 30.03.2006 01:11 :: kevinlin :: Replies: 4 :: Views: 1534
You actually do not need to write all the script. You can make cadence enerate the script then modify it to include your own loops to sweep on the corners.
To generate the ocean script from cadence. In the Analog Design environment choose:
Session -> save script
Then go to the file, and place your model file inside the loop, changing the c
Analog IC Design and Layout :: 17.05.2006 12:00 :: elbadry :: Replies: 6 :: Views: 2717
spp only converts the format of the netlist and it can not convert spice model to spectre model. This is why foundries usually provide both hspice and spectre models.
A good news is that cadence did a lot efforts to make spectre compatible with hspice models and netlist. You can use spectre to (...)
Software Problems, Hints and Reviews :: 21.10.2006 13:05 :: tsinghua :: Replies: 2 :: Views: 2084
in the ADE ,you can go to analysis ---
in the analysis section you find noise just left click on the noise you will get a new form for noise analysis ...enter the field and run a simulation...
Analog IC Design and Layout :: 14.12.2006 10:29 :: kumard35b :: Replies: 6 :: Views: 706
Use .connect command,
.connect gndd! gnd
.connect vdd! vdd
And run simulation
Analog IC Design and Layout :: 20.12.2006 05:59 :: gafsos :: Replies: 7 :: Views: 1829
In the pre-simulation schematic veiw, build a config file, replace the schematic file with your extracted file in the popup config dialogue box, run the just simulation file, the results you get this time are post-simulation ones
Analog IC Design and Layout :: 20.08.2007 08:12 :: abcyin :: Replies: 4 :: Views: 3247
I installed the TSMC 0.35um CM Process design kit in my unix system.
When I run the simulation in the analog envirnment in cadence Virtuoso, I always got the error message so I can not use that at all. I am not sure this error is originally design kit error or cadence error/
Do you know what this error message means? (...)
Analog IC Design and Layout :: 15.08.2007 20:19 :: whitewiz :: Replies: 6 :: Views: 1086
There is perl script provide by cadence in converting the spice netlist to spectre netlist.
By the way, TSMC always provide digital/analog library pdk to designers. So what you do is use include the spectre model inside tsmc pdk to run the simulation.
Analog Circuit Design :: 18.09.2007 22:35 :: skynet :: Replies: 6 :: Views: 2584
I installed cadence 5141_usr4 on RHEL 5 WS(I installed RHEL 4 WS first and then updated to 5) and I can run "icfb" properly well.
But when I tried to run a simulation(I opened Virtuoso Analog Design Environment), I cannot see the information on the top right corner. That part is just black and invisible. That part (...)
Linux Software :: 21.10.2007 15:18 :: bnagain :: Replies: 4 :: Views: 1985
I run my simulation with spectre of cadence. One diode i wish
to use is only .scs file and no symbol with it.
You know the simulation flow is usually draw schematic first and
add stimi, then evoke spectre and run simulation. (...)
Analog IC Design and Layout :: 23.01.2008 08:38 :: fxxjssc :: Replies: 5 :: Views: 3472
there is no fft in spectre ther is dft which you can use first you need an ideal dac you can write the dac equation on the calculator (weight each bit) then you run SFDR simulation you enter a full sine wave and put the ideal dac behind the adc and take
dft for the output
Analog Circuit Design :: 21.06.2008 15:24 :: mahgoub :: Replies: 1 :: Views: 1704
I tried in the past also to reuse some of the netlist work and calling from ADE to setup up batch spectre runs. But it fails because there is some hidden com between the ADE and if you call spectre by the ADE option. I think all these special features, like restart, period state file write, waveform marching and so on depend on other (...)
Analog Circuit Design :: 01.07.2008 15:38 :: rfsystem :: Replies: 1 :: Views: 432
so what is the problem?
Is it due to old version of IC5?
can I run this PDK on IC5?
I mean if it should be used for IC18.104.22.168 and later, can i run in a compatibility mode for ic5?
thanx in advance,
Software Problems, Hints and Reviews :: 21.05.2010 18:54 :: mohamedabouzied :: Replies: 5 :: Views: 3662
Did you run MMSim?
Analog IC Design and Layout :: 07.01.2009 19:05 :: psmon :: Replies: 6 :: Views: 1135
I am learning to run a design using AMS simulator with spectre solver. The set up looked fine and the netlist was generated without any problem. But when I run the simulation, I am getting the following error message:
Failed to elaborate ("amsPLL" "pll_160MHZ_sim" "config").
How can I resolve this. Please help. (...)
Analog IC Design and Layout :: 04.02.2009 04:07 :: sunil_rpine :: Replies: 3 :: Views: 1157
I am doing a full custom IC design using cadence Virtuoso tools.
I have a problem with the calculator associated with spectre Simulator.
It often happens that I run a simulation with spectre and i want to evaluate some parameters of the calculated waveform using the calculator. To do (...)
Software Problems, Hints and Reviews :: 05.06.2009 07:20 :: pinifrancesco :: Replies: 0 :: Views: 630
When I run spectre simulation in cadence, I get an error message.
The error is for Schottky diodes. From NCSU CDK package (I am using AMI06, I bring Schottky diodes in Schematic and run)
The error is that it requires to use of a model for Schottky diodes. I think I need a model file or at least (...)
Analog IC Design and Layout :: 12.06.2009 00:53 :: florescent :: Replies: 0 :: Views: 882
I currently use spectre simulation in cadence. I am wondering if there is any method to run the spectre simulation with layout only.
It's simple and no problem to run the layout simulation if based on its schematic or symbol. My question is to (...)
Analog IC Design and Layout :: 07.07.2009 14:45 :: florescent :: Replies: 3 :: Views: 882
go to your results folder/design/schematic/spectre/netlist and type .runsimulation
Analog IC Design and Layout :: 18.08.2009 17:19 :: oermens :: Replies: 13 :: Views: 5419
You may have a license to run only some types of simulations (just guessing).
Try to check your license server log (if you have access to the log) and see if there is something there about some missing feature.
Software Problems, Hints and Reviews :: 03.11.2009 08:55 :: R00KIE :: Replies: 3 :: Views: 1838
I want to do a corner analysis along with several other variable
parameters for my design.
At present the line specifying the model file looks like this...
All I need to change
Analog IC Design and Layout :: 22.12.2009 07:49 :: pd :: Replies: 2 :: Views: 1506
Hi, I'm using spectre to simulate my analog circuits. But the circuit is slightly complex.
When I run transient analysis for 2 us, the output file (named tran.tran.trn) is as large as 40G. So I set software output time to 1.5 us.
Then the output file is much smaller. However, when I plot some signals to verify the simulation result, (...)
Analog IC Design and Layout :: 17.01.2010 20:52 :: liqiyue :: Replies: 3 :: Views: 993
With the new cadence token system, an individual now can use almost any of cadence's advanced features as long as there are free tokens. It also means a user can easily suck up many tokens and leave everyone else waiting...
Is there a way add priority levels to the tokens, such that a token-hogging feature such as APS simulation (8 (...)
Software Problems, Hints and Reviews :: 13.04.2010 14:05 :: gszczesz :: Replies: 0 :: Views: 1065
I want to use corners to simulate circuit in different technics, like tt,ff,ss,etc.
But many items under the corner window is dark, which means there are some file unsetup, I guess.
Is there any body know such situation? what files I need to setup in spectre before I run corners simulation?
THX a lot!
ASIC Design Methodologies and Tools (Digital) :: 31.08.2010 04:53 :: iiiiisland :: Replies: 6 :: Views: 1351
I don't use Pspice but my approach for doing this sort of thing is to change the obvious syntax differences and then run a simulation. Then try to work out what the error messages mean and fix them. Comparison with a working Pspice model in a similar technology would help. For example - how fingers are handled in the symbol & template.
Analog Circuit Design :: 23.10.2010 03:11 :: keith1200rs :: Replies: 4 :: Views: 825
Did you try it the other way round: run all these programs from a UNIX (shell) script?
See also dick_freebird's posting.
Analog IC Design and Layout :: 31.10.2010 08:09 :: erikl :: Replies: 2 :: Views: 940
I simulate the PA using model from Infineon. I can't do the load-pull properly because of non- convergence errors. Additionally when i run LSSP simulation the results is the same. When i decrease the input power by 5-10dB from saturation level the problem dissapears. HB for single tone when i make some changes at setup (Krilov method) i can wor
RF, Microwave, Antennas and Optics :: 19.06.2011 08:28 :: bubuta77 :: Replies: 6 :: Views: 603