Search Engine

Sample And Hold Circuit

Add Question

1000 Threads found on Sample And Hold Circuit
Hi, I am designing a SC sample and hold circuit as shown in the following picture. When I used a large holding cap of 1pF, the output of the opamp takes a longer time to settle down at phase 1. Furthermore, the output during phase 2 seems to deviate more from the ideal sampled value. Could (...)
I'm using Miller capacitance sample and hold cirucit. For an 8-bit resolution my sample circuit must be able to detect and hold at least 12mV. Right now I'm only able to make the resolution to 0.2V @ 200mV. Can I get ant suggestion of how can i achive my targeted (...)
in sample and hold circuit. the OTA is not used during sampling, so, will the GBW and return ratio of the OTA during the sampling mode have any effect on the s/h? and, if the load capacitor of the sample mode and hold mode are differnet (...)
dear friends can any one provide me with a sample and hold circuit diagram with appropriate switches. i have got one on the net but its not giving proper result. i am simulating it in pspice.i have got it at i use the 1 M resisto
hellooooo.... m new to orcad.... i am doing a project on sample and hold circuit...but am not getting the results i am attaching the papers and capture commands... even if someone can suggest anything how to do this with schematics(orcad 9.2 (...)
Hello everybody, I want to design sample and hold circuit using double sampling technique at 160MHz clock (320MS/s) and 70dB IMD. Here I choose the two-stage opamp, the schematics are here. (Two stage module and the double sampling). But slew rate and charge injection (...)
i have to design sample and hold circuit for ADC with this spec:1000MSPS and 8bit resolution.input of this circuit(S/H) is single ended(Vi) and output is single ended too. most of S/H that i saw in papers are fully differential thus are useless for me. any suggestion will (...)
I think you might be better off code-modeling the various functions and artifacts of interest, in a more straightforward and expressive way. Why would you want to do it using polynomial math, when you can talk sample time and slope error, sample pedestal, through-delay and rise-fall? (...)
Why dont you use simulink? It has a block for sample and hold
i am trying to modify an old synthesizer to accept a 0v / 5v or 15v trigger input to trigger a sample / hold circuit. currently there is a slider that controls the sample time (frequency) of a sample and hold circuit. the dc output on scope after the (...)
i Hello I am designing a sample and hold circuit ,whose out put will be given to ADC in ARM signal is analog signal of on time 2-4 micro sec and period >=10ms . I am using comparator before to this sample and hold circuit whose (...)
Hello, It is probably a simple question, but I struggle with this a little. I use an RF detector and I need to integrate after the detector, so I have about every 10's sample or less. If its detector, that should basically produce an envellope, is it possible just to use low pass filter as integrator? I am using LT5507 as integrator. So I ju
Hi, I need help to understand the circuit to be implemented in my project. Can someone provide me guidance to understand how this sample and hold circuit works? Thanks. ---------- Post added at 18:32 ---------- Previous post was at 18:30 ---------- Sorry... I need (...)
hi, i need help for constructing a sample-and-hold together with a bit-to-symbol converter in 1 circuit board. From what i had understand, a sample-and-hold circuit consist of a input, switch(BJT or Mosfet) and a (...)
Hey guys, I need some help here. Can you please give me some direct hint on how to build a 22Mhz sample and hold circuit? It's for my lab next week. Thanks.
Hi All, Am working on sampling analog signals. In my work I need a sample and hold circuit that can sample analog signals in GHz (10 HGz is nice) region. May somebody help me if there is a link to such a S/H circuit. Thanks in advance.
ok i'm designing a sample and hold circuit, using a mosfet and a capacitor, maybe a buffer at the output but im still not past this point yet. my question. as i'm using the mosfet as a digital switch or CLK , so ofcourse as i learnt it will be operating in the linear region. so when im applying the voltage (...)
Hi All, In my design I would like to sample analog signal whose frequency is 350 MHz using a 600KSPs ADC. In this case I thought of scaling down the frequency from 350 MHz to around 100KHz using a sample and hold circuit. Is my idea O.K or are there other techniques that I can use to scale down the (...)
Hi all, during the simulation of the sample and hold circuit, i have encountered one problem. the circuit is a simple sample and hold circuit consisting of a switch and a capacitor. the input is vsin with pac mag set to 1. (...)
Hi, can u please tell me how to draw sample and hold circuit in cadence using two stage opamps.....and can u please tell me if i give input voltage 1.8v the how the output voltage in sample and hold circuit..Can u send me the (...)
What are the sample and hold circuit ..... What are it's specification..?
Hello everyone, I am doing thesis on CMOS image sensor design and layout for my 4th yr undergraduate. I have researched and decided on sample and hold (S/H) circuit. I tried and troubleshooted but not succeed. Does any one has SIMPLE(not so complex) S/H (...)
Hello guys , I'm student in swiss federal institute of technology in Zurich . I'm very grad tojoinin this forum with all of you . In this semester, I have a semester thesis : design a high speed sample and hold (SH) circuit. I use T 0.13um CMOS technology ... For the OTA, that is used in SH circuit, I (...)
i am using the above sample and hold circuit for a 16-bit ADC> the switch is realised using both nmos(W=500n L=1.6u) and pmos(W=1u L=1.6u). the input voltage range is 0-2v. the sampling freq is sample pulse width is 100usec and hold period is 4.9msec. (...)
1. differential sample and hold circuit using gate capacitances of following stages to hold the sampled value. 2. transmission gate sample and hold circuit.
The S/H is the idealized T/H Every sample and hold circuit need some time to aquire the input signal. While this aquiring phase the output is typical tracking the input. If not there is a second energy storage element which buffer the signal. Depending on the design specification the tracking or aquisitation phase could (...)
Should the turn on time of MOSFET be longer than 5RC? Then cap can get the stable input voltage and hold this voltage till MOSFET turn on again? Which wideband FET can be used as the Buffer next to sample and hold cpa? Thanks.
I am using ADC to acquire a signal 1MHz. Would I require a sample and hold circuit before ADC? I am using ADC--> ADS5474
For 1 stage of the pipelined ADC During the sampling time: the output of the pipelined ADC stage is zero, During the amplification mode: the output equals the right expected value. So when i put a second stage, its input (from the first stage) changes between the zero and the right value; therefore the output of the second stage becomes wrong b
With reference to It is the time to charge the hold capacitor
Hi guys I am trying to simulate the PSS & Pnoise of simple sample and for circuit for thermal noise simulation. 109671 The clock signal for gate voltage swings from 0 to 2.4V (for rail to rail sampling) The input source (PORT0) generates sine signal from 0 to 1.2V Accoring to kT/C noise theory, I expect to noi
can anyone tell me or give me circuits to solve input dependent charge injection in sample and hold ...i have to use this for 16-bit adc so it should be very accurate...i have tried switched capacitor but no luck..i'am using 1.6u tech
hi, this picture (which i'm sending) is of "PC Based Data Logger" which was published recently in a magzine (sorry for reproducing here), The circuit is using sample-and-hold stage, using LF398. I want to know what's the purpose of this. What i uderstand is the designer must be using it to limit the number (...)
I'm using close loop track and hold circuit... The circuit use 2 analog buffer before the sample capacitance and after it. On the analog buffer design firstly I've used ideal current source to trigger the tail current. the value is 100?A. Then i get dynamic range between 0.04V to (...)
You can use sample function in calculator . The get the data into matlab, then do FFT...
im a i attach the circuit of my study 1)i also attach a little bit that i understand now...but i still not sure if it right or wrong i hope some one can tell me if i wrong. 2) i want to know more about the complementary differential pair that been used as an input in this circuit.and the (...)
do i need seperate sample and hold for different parallel stages of 6 bit flash adc using 0.18u or only one S/H can take load of all stages
Thanks for your reply, but do you mean the input capacitance of the opamp will be charged during the sample period by VB, and when the hold period comes, the voltage could be maintained for some while? if not, could you explain how would the input bias be settled ? Best regards
hello, everyone I have following questions about track and hold circuit. (1)What's the difference between track and hold(T/H) and sample and hold (2)how to T/H improve ADC input bandwidth? by (...)
Thank you in advance. I am designing a switch cap for sample and hold. I use transmission gates as switch and a cap to hold charge. The control signals to control PMOS and NMOS are C and CZ, then: a) To avoid clock feedthrough, should the Tr/Tf of C/CZ be sharp or not? (...)
What is the difference between the Alexander and the sample and hold phase detector??
in Razavi's Book P408 figure 12.4 He said, when hold clock rises, S1, S2 off, S3 on, Vout will be Vin*(C1/C2) I did some simulation, set C1=C2=1pf, and found out Vout was 0 and VB=-0.3v (vin=0.6v) what was wrong in my HSPICE code? *Razavi P408 Fig 12.4 * Used to test ideal sample and (...)
Hi All Would you please provide me the schmatic diagram of a sample and hold amplifier, power supply rejectiopn ratio >80db?
1) what is the function of sample and hold in ADC.i know that it hold the interval and sampling it again...but what is it effect in ADC.the advantage of it 2)what is the advantage of using rail to rail op amp than other op amp. is there any disadvantage or drawback by using rail to rail amplifier (...)
hi everyone, I am designing a adc in TTL LOGIC.i am in need of a ttl sample and hold crkt..can anyone send me any crkt or materials regarding this topic. thanks
Hi, I am doing sample and hold. I think capacitor question. I have some questions. which one is correct ? why? What is bottom plate? Thanks.
can anybody help me about the sample and hold structure for the first stage of pipeline adc. (It will sample 10Ms/s.)
I have one question regarding the sample and hold amplifier in the picture. During phase 1, SH(1), S1, Seq, and S2 are all closed and S3 is open. During this time, Vx and Vy are equal to the offset voltage of the opamp. During phase 2, SH(2), S2 opens and injects some (...)
Hi, A simple track and hold circuit could be found in the attachment. This Track and hold circuit is used for the front end of high speed flash ADC, say 5Ghz. By using 5GHZ as sampling frequecy, when the input frequency is 2.5GHz, the simulation shows that the output signal is (...)