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115 Threads found on edaboard.com: Sample And Hold Circuit
Hi guys I am trying to simulate the PSS & Pnoise of simple sample and for circuit for thermal noise simulation. 109671 The clock signal for gate voltage swings from 0 to 2.4V (for rail to rail sampling) The input source (PORT0) generates sine signal from 0 to 1.2V Accoring to kT/C noise theory, I expect to noi
You need way, way better than 1MHz BW for that fast of a conversion rate. I'd suggest that you think of track/hold rather than sample/hold (the latter implying a shorter sample window to me, short window makes the settling time a greater problem). Depending on the loading of the "S/H" you might have a bare cap (...)
some PA systems will sense the ambient sound level and automatically adjust the volume so it is above the background sound level so you might look at the circuit blocks they use. I would surmiss it is a sample and hold circuit feeding a DC controlled voltage amp
Hey guys, I have a basic question about SC circuits. Say we want to have a switched cap circuit as a sample and hold in an ADC or as an integrator. If the resolution of the converter is expected to be 10 bits, I wonder if it means that the voltage stored on the capacitor should be within one LSB error of (...)
Hello all, I have a basic question, when we design a sample and hold or switch cap circuit, the output of the circuit (voltage on the sampling cap in SH, or on the integrating cap in integrator) would not be exactly like the input voltage. Now I am not quite sure about these issues: 1) which parameter (...)
Hi, I'm trying to design an two staged Op amp for a sample and hold ciruit with 125v/us slewrate and GBW>50 mhz with 60 degrees phase margin. My main problem is that i can t fullfill both gbw and phase margin requirement. Am i doing something wrong or should i just use a different amplifier? I (...)
What are the sample and hold circuit ..... What are it's specification..?
Hello, I'm designing a differential sample-and-hold. I have some specifications I have to met. The maximum supply voltage is 1.2V and there is chosen to be 100mV margins on the supply lines leaving a voltage swing of 1V from 0.1V to 1.1V. The kind of circuit I am designing is the differential equivalent (...)
Hi, can u please tell me how to draw sample and hold circuit in cadence using two stage opamps.....and can u please tell me if i give input voltage 1.8v the how the output voltage in sample and hold circuit..Can u send me the (...)
Hi all, during the simulation of the sample and hold circuit, i have encountered one problem. the circuit is a simple sample and hold circuit consisting of a switch and a capacitor. the input is vsin with pac mag set to 1. (...)
cant use microcontoller its IC. Seems like a though question...Yes, but how do you make the circuit to "know" the next pulse? Anyway, you have to make at least two storage circuits (sample and hold), probably more.
Hi, i am Dev working for a project Flash ADC design using Tanner EDA, I am very much new to this tool and facing lot of problems with the design of FLASH ADC. Please help me how to start.I am want to design sample and hold circuit using CMOS 180nm Technology. Please help me how to start.
It's very difficult (if not impossible) to build an analog sample and hold with <0.1mv acquisition and hold accuracy from a 12V signal for 10 minutes. I would suggest you use a digital approach. Convert the signal with an A/D converter to a digital value and then output the digital value (...)
The S/H (sample & hold) is a separate function that is part of the inputs of many (but not all) ADCs. The S/H captures a short slice of the analog input signal and holds it as a DC level during the time it takes the AD to convert the analog sample to a digital word. The S/H function certainly can be (...)
The circuit is used in a high speed sample hold circuit. The output swing for both circuit is enough. So can any one tell me which one is better, the right or the left? Why? 3X! 74073
Hi, I meet a problem of convergence when I use veriloga to model the SH circuit. I first use veriloga to build the model of capacitor, ideal switch and ideal opamp, but when I do the simulation with spectre, It tell me no convergence, how can I do with this problem? thx!!
With reference to It is the time to charge the hold capacitor
The exact hardware equivalent of taking a reference on button press would be a sample and hold circuit. in "older days", they have been implemented with large capacitors (e.g. a 10 uF foil type) and low input current FET amplifiers. They have been able to keep a reference may be for hours with acceptable (...)
To decide about component values, we need to know the OP and switch transistor types first. In addition, there's no particular need to give the input stage a gain > 1, it can be configured a s buffer similar to the output stage as well. A reasonable capacitor value depends on the signal time scale, sample rate and available acquisition time.
dear all good day i am a R&D engineer and search about ADC with following specs -2channel -2 sample and hold circuit -SPI interface -100khz sampling frequency wait your reply for impartance best regards
Dear all, I am designing a low-to-medium S/H circuit for an ADC. The sampling switch is a bootstrapped switch to linearize the on-resistance. I first designed a bootstrapped switch, and I simulated the waveforms and obtained DFT and THD in cadence with the calculator. After that, I also designed a dummy switch to (...)
Hi, how to suppress charge injection effect in sample hold circuit ?
I want to make a sample and hold circuit. I want to know if there is a way to simulate and plot graphically the number of time constants. To be more specific : I know from behavioral model that 1 time constant is max 30ns. The Tsample is 250ns. So the minimum UGF is 1/(2pi*tau)=5.3MHz. (...)
Hi All, In my design I would like to sample analog signal whose frequency is 350 MHz using a 600KSPs ADC. In this case I thought of scaling down the frequency from 350 MHz to around 100KHz using a sample and hold circuit. Is my idea O.K or are there other techniques that I can use to scale down the (...)
ok i'm designing a sample and hold circuit, using a mosfet and a capacitor, maybe a buffer at the output but im still not past this point yet. my question. as i'm using the mosfet as a digital switch or CLK , so ofcourse as i learnt it will be operating in the linear region. so when im applying the voltage (...)
hello everyone, i am trying to write the equation for charging of a capacitor. Vo = Vin(nT)*(1-exp(-t/30)); for nT< t<(n+1)T. where, the T=hold time for a sample and hold circuit. I have to write this equation in matlab. Can anyone suggest me the code....
Hi All, Am working on sampling analog signals. In my work I need a sample and hold circuit that can sample analog signals in GHz (10 HGz is nice) region. May somebody help me if there is a link to such a S/H circuit. Thanks in advance.
Hey guys, I need some help here. Can you please give me some direct hint on how to build a 22Mhz sample and hold circuit? It's for my lab next week. Thanks.
hi, i need help for constructing a sample-and-hold together with a bit-to-symbol converter in 1 circuit board. From what i had understand, a sample-and-hold circuit consist of a input, switch(BJT or Mosfet) and a (...)
Hi, I need help to understand the circuit to be implemented in my project. Can someone provide me guidance to understand how this sample and hold circuit works? Thanks. ---------- Post added at 18:32 ---------- Previous post was at 18:30 ---------- Sorry... I need (...)
Hello, It is probably a simple question, but I struggle with this a little. I use an RF detector and I need to integrate after the detector, so I have about every 10's sample or less. If its detector, that should basically produce an envellope, is it possible just to use low pass filter as integrator? I am using LT5507 as integrator. So I ju
I have had the "pleasure" of designing a JFET based S/H product once. The key is to ensure that when "on" the JFET switch gate is roughly at the sampled signal potential, and when "off" it is pinched off as little as possible, beyond "what works" so you minimize charge injection and sampling pedestal. I did this with a secondary (...)
I am rigging circuit sample and hold circuit using LF 198 but when i make S/H(BAR) low it is not holding the value of sampled..Pls suggest me a soln..I am using 0.01 m icro farad capacitance.
i Hello I am designing a sample and hold circuit ,whose out put will be given to ADC in ARM signal is analog signal of on time 2-4 micro sec and period >=10ms . I am using comparator before to this sample and hold circuit whose (...)
hello, everyone I have following questions about track and hold circuit. (1)What's the difference between track and hold(T/H) and sample and hold (2)how to T/H improve ADC input bandwidth? by (...)
What you suggest is a perfectly valid way of doing it and probably easier to get working accurately than a sample & hold based circuit. Keith.
I am using ADC to acquire a signal 1MHz. Would I require a sample and hold circuit before ADC? I am using ADC--> ADS5474
I tried this topology but I have offset problem . these opamps are working 500Mhz but they have offset such as 4-5mV. but I have 20mV range for every step. 2^6=64 step . so 4mV is large for me when I decreased offset I have settling problem. I didnt find any opamp with low offset and high speed at 0.18tsmc . any suggestion for hig
Thank you Frankliner. The design is a sample and hold circuit. If out of 1000 runs, I have, let's say, 50 runs where the output is not stable (oscillates) and the remaining runs result in good Harmonic distortion figure. Is that considered acceptable or good circuit?
i am trying to modify an old synthesizer to accept a 0v / 5v or 15v trigger input to trigger a sample / hold circuit. currently there is a slider that controls the sample time (frequency) of a sample and hold circuit. the dc output on scope after the (...)
Hi, all, I am designing a switched-capacitor S/H circuit, and from some documents, I found that the opamp used in the circuit takes use of a switched-capacitor CMFB, what I want to know is that, why this specific CMFB should be used here, but not a general CMFB circuit? and also any literature about (...)
hi, I design a bootstrapped switch used in a simple sample/hold circuit( a bootstrapped switch with a cap load). The bootstrapped circuit and simulation result is in the following graph. In the simulation, the blue line is a ideal switch result. the red line is using a bootstrapped switch. It (...)
Hi, all, I am trying to build a testbench for ADC in ADS, to get some behavioral information. and I got an example in the design guide, but it seems that only sample-and-hold circuit is provided there, so the question now is how to quantize the sampling results, to get the digital codes? which component (...)
Your apparently refering to a sample & circuit. It can be basically built from an analog switch, a capacitor and a buffer OP. until we don't change.doesn't seem a clear condition, however.
Should the turn on time of MOSFET be longer than 5RC? Then cap can get the stable input voltage and hold this voltage till MOSFET turn on again? Which wideband FET can be used as the Buffer next to sample and hold cpa? Thanks.
I think you might be better off code-modeling the various functions and artifacts of interest, in a more straightforward and expressive way. Why would you want to do it using polynomial math, when you can talk sample time and slope error, sample pedestal, through-delay and rise-fall? (...)
Why dont you use simulink? It has a block for sample and hold
I designed a sample/hold amplifier for 14bit 100Ms/s ADC input. In typical simulation, the sample/hold amplifier shows good performance, which has 95dB SFDR. However, in slow corner(mos slow, cap slow, 120deg temp), the sample/hold amplifier shows bad fft results with 80dB SFDR。 I (...)
The S/H is the idealized T/H Every sample and hold circuit need some time to aquire the input signal. While this aquiring phase the output is typical tracking the input. If not there is a second energy storage element which buffer the signal. Depending on the design specification the tracking or aquisitation phase could (...)
Hello, How do you have your reference tensions defined in the microcontroller??? Any floating in the Vdd voltage of the micro??? Any problem with input impedance, remember that the micro is and and sample and hold and the serial impedance of your circuit can be (...)