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129 Threads found on edaboard.com: Sampling And Quantization
When you sample a continous signal (a continous signal is something like sin(w*t), you can find its value for any time t), the signal exists only at the sampling instant (like t=1s, 2s, 3s, ...). Else the signal is not zero, but doesnt exist.
The signal can be quantized, which means that the signal is now restricted to have a few voltage level
Digital communication :: 17.08.2007 07:09 :: bulx :: Replies: 2 :: Views: 2713
Hello , i'm newbie here :D .
Just a simple question , is there a relation between sampling frequency and quantization ?
I implement a quantization script under MATLAB 7.0.14 for quantizating signals.
Theorically the quantized signal must be like stairs , not a line !
These are my results :
For fs(frequency (...)
Digital Signal Processing :: 05.02.2010 11:39 :: papriko :: Replies: 7 :: Views: 1552
I think you need some basic understanding of ADC. First sampling and quantization then switch to concrete ADC architecture
Analog IC Design and Layout :: 06.03.2011 12:58 :: wanghs1986 :: Replies: 14 :: Views: 1243
FPGA story just starts after sampling. It means you supposed to have a digital data stream that has been already sampled (e.g. by ADC). In FPGA you are about processing parts (Filtering, Mixing, ...).
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.08.2012 15:45 :: Zerox100 :: Replies: 36 :: Views: 1339
Hi,
I hope you are not looking for DIRECT digital down conversion.
I had used digital downconversion for a GPS receiver. It is fairly easy. you follow in digital all the process of analog. However you need to be careful about sampling and quantization levels.
B R
Madhukar
RF, Microwave, Antennas and Optics :: 26.01.2005 08:33 :: brmadhukar :: Replies: 2 :: Views: 599
Hi all,
I am wondering for a 12-bit resolution ADC, how big of a sampling capacitor at the front end should be in order to surpress the kT/C noise and opamp thermal noise from the later stages?
Peoples used 6pf before, I think it is way too big. Any ideas?
Analog IC Design and Layout :: 09.03.2006 12:12 :: Analogworld :: Replies: 3 :: Views: 899
You have to do sampling first, because remember that sampling has the time reference, that is the sampling period.
quantization is just mapping a set ot measured voltages, to a set of predefined discrete voltajes, that are in turn mapped to a set of binary digital values by ADC.
So in order to do this, you have to (...)
Electronic Elementary Questions :: 10.09.2006 19:37 :: jetset :: Replies: 16 :: Views: 2998
Hi,
I am engaged in a project which need to process digital IF signal. The passband sampling theory shows that when we sample a signal based on the theory, we can get the signal in the base band. But when I read some references , they show me that the digtal down converter prevail against the passband (...)
Digital Signal Processing :: 10.11.2006 08:13 :: agump :: Replies: 5 :: Views: 1292
An analog, low-pass filter prior to the input of the ADC eliminates or significantly reduces aliased noise. The corner frequency of the filter must be lower than fsampling/2. Increasing the order of the filter can minimize the noise.
Electronic Elementary Questions :: 13.06.2007 10:06 :: svicent :: Replies: 13 :: Views: 721
Dear all
I need the following the paper, but i don't access to it, if you can ,pls send it for me.
thanks you for your help.
Chang,H., ?Presampling filtering,sampling and quantization effects on the digital matched filter performance? Proceeding of International telemetering conference,pp.889-915,San (...)
Digital communication :: 31.01.2008 10:08 :: scottxin :: Replies: 1 :: Views: 970
I need mathematical examples about the subjects in image processing:
-filtering in the spatial domain.
-filtering in the frequency domain.
- Histogram equilization.
-Image sampling and quantization.
-Gray Level Transformations.
Anyone can help me in that?
Digital Signal Processing :: 05.01.2009 11:33 :: ahmadaltaan :: Replies: 1 :: Views: 512
Hi all
What is the relationship between "sampling frequency" and "quantization noise" in audio signals?
Digital Signal Processing :: 05.03.2010 10:31 :: meher81 :: Replies: 0 :: Views: 592
Hi amit,
Bit Rate Resolution:
Ok let separate these words like Bit Rate (BR) Resolution just to understand. Bit Rate is defining the rate of bits, Binary Digits 0, 1, 0, 1 (per unit time i,e; Second). Now if we divide the 1 second into 10 and then we divide it into 20, in first case we will have 10 happenings in one second and in seco
Electronic Elementary Questions :: 06.09.2011 07:54 :: Raza :: Replies: 12 :: Views: 850
we r doing project in biomedical.. we r using adc0808 interface with 8051 to measure the signal from piezo-crystal sensor.. in A to D conversion what is thesampling frequency????
You have to provide clock to 0808 ADC, this clock determines the sampling rate in the present case under discussion.
If you can post t
Electronic Elementary Questions :: 17.05.2012 20:51 :: ark5230 :: Replies: 12 :: Views: 349
"the basic phenomena" about ADC are:
- converts continuous voltage(or current) into a set of discrete (discontinuous) values
- time also becomes "granular" since sampling the input analogue voltage is done with a certain clock.(time interval)
It sounds like a loss of information,but actually this is the only way of interfacing analogue and dig
Electronic Elementary Questions :: 25.06.2004 19:58 :: batdin :: Replies: 11 :: Views: 1812
In your system, I assume you have a microphone amplifier preceding the ADC. You can still use the traditional low frequency ADC (a few tens of kHz) to do a nice job, if the Mic amp has a fully differential structure which features in high PSRR. But since the ripple you have on the supply has frequency as high as 10MHz, the Mic Amp may not have suff
Analog Circuit Design :: 20.03.2005 08:48 :: willyboy19 :: Replies: 2 :: Views: 1027
how to design a over-sampling filter to reduce quantium noise in the process of DA converting for audio playback???can you tell me the general theory about it??and what useful book i can refer to ????
Digital Signal Processing :: 26.11.2005 12:54 :: ls000rhb :: Replies: 1 :: Views: 466
Hi
Process gain is defined as improvement in signal to quantization ratio when using oversampling.
PG = 10 * log10(fs / (2 * BW))
BW = output BW after decimation.
To calculate PG you need to know BW, so specify the output BW or decimation ratio then i can help you.
Regards
Analog IC Design and Layout :: 13.12.2005 08:33 :: Circuit_seller :: Replies: 4 :: Views: 483
The behaviout of your PLL seems quite 'normal'. It is pretty common that the inband phase noise is worsened when you enable the Fractional part (ie. using an input ≠ 0).
The inband noise is a combination of many differents contribution within the fractional pll.
One is from the fact that the sampling instance in the phase-detector (...)
Analog IC Design and Layout :: 06.05.2006 22:04 :: rfasic :: Replies: 3 :: Views: 1307
quantization error in a duty-cycle modulated signal:
When a pulse train as depicted below is sampled it will result in another pulse train which represents the error. Assuming the area under the error pulses is An, then the error should be in between ?Ts and +Ts where Ts is the sampling frequency. In the paper ?Analog-to-Digital (...)
Analog Circuit Design :: 06.06.2006 18:14 :: svensl :: Replies: 2 :: Views: 582
Can DSPs replace most of Analogue Circuits of the past times ?? What are the constraints ?? No of bits used to represent 1 sample ?? sampling rate ??
Electronic Elementary Questions :: 13.07.2006 18:08 :: starfish :: Replies: 11 :: Views: 833
A discrete signal or discrete-time signal is a time series, perhaps a signal that has been sampled from a continuous-time signal. Unlike a continuous-time signal, a discrete-time signal is not a function of a continuous-time argument, but is a sequence of quantities, that is, a function over a domain of discrete integers. Each value in the sequence
Electronic Elementary Questions :: 19.08.2006 04:08 :: bauer :: Replies: 4 :: Views: 12675
Digital signal processing (DSP) is the study of signals in a digital representation and the processing methods of these signals. DSP and analog signal processing are subfields of signal processing. DSP has at least three major subfields: audio signal processing, digital image processing and speech processing.
Since the goal of DSP is (...)
Microcontrollers :: 19.08.2006 03:55 :: bauer :: Replies: 16 :: Views: 23161
u can use the wavread command to read the file
and wavplay to play the wav file
note in the above two methods u can change the bits/sample and sampling frequency. but i suggest u to use a wav file which is sampled at 8k si that u can get a nice output.
as a wave file is a digitized oneu cannot quantize it again u can (...)
Digital Signal Processing :: 25.01.2007 12:52 :: rsrinivas :: Replies: 2 :: Views: 1373
Hi, all
I noticed for some SD ADC designs, ppl use CDS to decrease integrator leakage and flicker noise. For those of designs that circuit noises are the dominant noise sources (i.e. quantization noise is not so obvious), how can I model flicker noise and white noise properly if CDS is employed? thanks.
-TiwstedNeurons
Analog IC Design and Layout :: 05.03.2007 22:36 :: TiwstedNeurons :: Replies: 5 :: Views: 1895
you should choose anathor sampling frequency.
for example, fs=64MHz.
as to your said,fin/fs=Mc/M. however, Mc must be integer.right? you should check it. I found your choose is wrong.:)
if it's still wrong, you can upload the results image. let us discuss it.
Analog Circuit Design :: 08.03.2007 08:34 :: renwl :: Replies: 14 :: Views: 8594
oversampling reduces the quantization noise density.
Digital Signal Processing :: 11.06.2007 13:14 :: brmadhukar :: Replies: 10 :: Views: 6217
In 2001, Abidi published a paper of "A 6-b 1.3-Gsample/s A/D Converter in 0.35-um CMOS".
Only 6-bit resolution is required, however, Abidi and Michael Choi added 1pF as input sampling capacitor. The thermal noise due to KT/C is only about 2mV, which is much lower than LSB quantization noise. Why they put so much capacitance there (...)
Analog IC Design and Layout :: 10.07.2007 16:37 :: neoflash :: Replies: 0 :: Views: 399
I want to know the relation of spur and non-linearity in ADC and
what is the difference between harmonic and spur?
in ADC because of non-linearity, input driving and s\h circuit
at output we see that harmonics of input signal appear at ADC
spectrum.
The ideal ADC has the quantization noise (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.09.2007 13:21 :: fanisani :: Replies: 0 :: Views: 347
I want to know the relation of spur and non-linearity in ADC and
what is the difference between harmonic and spur?
in ADC because of non-linearity, input driving and s\h circuit
at output we see that harmonics of input signal appear at ADC
spectrum.
The ideal ADC has the quantization noise (...)
Analog Circuit Design :: 05.09.2007 13:23 :: fanisani :: Replies: 9 :: Views: 2007
I also would suggest that you look at the IEEE Proceedings special issue on GPS. There was a very good paper which discussed the trade off between sampling rate and the number of bits ...
Hope this helps.
RF, Microwave, Antennas and Optics :: 23.09.2007 17:10 :: brmadhukar :: Replies: 9 :: Views: 2409
actually the 2nd case is the one which is to be used... take a signal and if you sample it at twice the frequency and if the sampling point falls on the zero crossing of the signal being sample then all the samples will be zero... what sense can u make of the samples....
so if the sampling freq is slightly higher than the (...)
Analog IC Design and Layout :: 05.01.2008 14:37 :: A.Anand Srinivasan :: Replies: 4 :: Views: 613
hi avi
FIR filters offer several advantages over IIR filters
* They can easily be designed to be "linear phase" (and usually are). Put simply, linear-phase filters delay the input signal, but don?t distort its phase.
* They are simple to implement. On most DSP microprocessors, the FIR calculation can be done by looping a single ins
Electronic Elementary Questions :: 26.03.2008 15:26 :: joe1986 :: Replies: 4 :: Views: 2279
After sampling the discrete signal has to be rounded to its nearer digital value. hence we go for quantization.
Digital communication :: 26.05.2008 13:14 :: sanforu.salem :: Replies: 4 :: Views: 2131
Dear zxasqw123,
Of course the linearity of the front-end S/H stage is very important, since it directly affects the linearity of the input signal to the ADC. However, if the well-known Flip-Around structure is utilized as the S/H, the unity gain is almost independent of the capacitor mismatch, since the same capacitor is used for both sampling a
Analog Circuit Design :: 03.03.2009 15:08 :: ezt :: Replies: 12 :: Views: 1008
Hi!
What type of resolution:
* in amplitude, in phase, in frequency, etc.?
Normally you should know at least:
* the signal sampling factor (SSF) N = Fdigitalization /F signal
* the number of the accurate bits n
* the moment (angle) of the first sample
* the total number of bits
* the frequency band of the signal...
BR
Digital Signal Processing :: 08.09.2009 09:04 :: Petre Petrov :: Replies: 4 :: Views: 430
hi one query
for 10bit Nyquist Rate ADC .
i am giving 1k signal input and sampling frequency is 4MHz.
then what snr i expect therotically.
snr = 6.02N+1.76 ==> 61.96dB
but i have seen the snr equation is SNR=6.02N+1.76+10log(OSR)
here i am applying the input fin=1k and fsamp= 4M
so the OSR = fsamp/2*fin = 4M/2K = 2000
hence total (...)
Analog IC Design and Layout :: 13.08.2010 06:35 :: manissri :: Replies: 5 :: Views: 946
JoannesPaulus: what information can i get from the dft of the output? what output are you talking about? because i'm runinng the comparator and simply get a digital signal that is change. are you referring to this? what are you meant in "looking at the error of the modulo-time plot"?I am referring to the output of the
Analog IC Design and Layout :: 07.10.2010 14:01 :: JoannesPaulus :: Replies: 14 :: Views: 933
If you do not use "coherent sampling" you need to apply a window function to your signal before the fft, see below.nsignal=4096;
fs=44100;
f=1001*fs/nsignal; % coherent sampling i.e. integer number of cycles (1001) in nsignal samples
%f=1000; %non-coherent sampling. Use hann window below
t=/fs;
y=1*sin(2*pi*f*t);
w=ones(nsignal,
Analog Circuit Design :: 04.11.2010 21:49 :: JoannesPaulus :: Replies: 1 :: Views: 1052
Hello,
I am trying to implement a behavioral model of a delta modulator in Matlab, consisting of an ideal comparator and a summing unit in the feedback path. Unfortunately the spectrum is not flat as expected and I get peaks at odd harmonics of the signal frequency (cf. attachment).
Does this behavior occur because the quantization noise (...)
Digital communication :: 03.05.2011 17:27 :: Matata :: Replies: 0 :: Views: 328
Look into jitter analysis of ADC's, Phase modulation, and DDS systems. Each can be helpful.
the uncertainty generates sidelobes for the same reason phase modulation does. The equivalent index is low, so you probably will only see one sidelobe. The effects become more pronounced for high-speed ADC's sampling signals above Fs/2 (bandpass (...)
Digital Signal Processing :: 04.06.2011 03:03 :: permute :: Replies: 2 :: Views: 326
sampling at 2x the maximum frequency does not guarantee signal reconstruction. At best it will detect the presence of the maximum frequency Fourier component , but the amplitude estimation is not guaranteed. It can vary from zero to the actual amplitude of the fmax Fourier component. (depends on the sampling phase, sampling at less than 2x (...)
Digital Signal Processing :: 23.01.2012 20:06 :: klystron :: Replies: 9 :: Views: 707
Runge Kutta is for solving differential equations, which is a completely different problem than calculating the integral of a sampled waveform. Provided that the requirements of the sampling theorem are fulfilled (no spectral components of the signal higher than 1/2 of sampling frequency), the time-discrete signal processing operations can be exact
Electronic Elementary Questions :: 28.02.2012 17:24 :: FvM :: Replies: 9 :: Views: 720
i have code matlab of this compression but i have a probleme in the party of lloyd max ? i need for ur help plz
i put only the party of max lloyd quantification
% Lloyd-max algorithm using signal values
% Signal : Signal Vector
% tol : Tolerance
% Initial : sampling levels
% dist : distortion
% qua
Digital Signal Processing :: 10.05.2012 20:25 :: ms13 :: Replies: 0 :: Views: 258
1) To get an 8 bit output we need to count the highs on the itstream for 255 clock periods.
2) It does not matter where in the bitstream we start counting.
That's basically correct, the '1' density is representing the input voltage. In contrast to a simple counter, a first order CIC decimator is working as an accumalator for fracti
Digital Signal Processing :: 19.05.2012 14:16 :: FvM :: Replies: 13 :: Views: 464
Dear all,
I am having problem with getting data from my ADC... please see the following
I am giving 125Mhz sampling clock to1 Mhz Sine wave signal. The image attached is the response that I am getting.
What are these Sudden Jerks or Instant rise or Falls... Is it because of sampling frequency bei
In actual I have to give different si
Analog Circuit Design :: 15.07.2012 09:34 :: syedshan :: Replies: 18 :: Views: 559
Principles of Digital Communications I provides an introduction to the theory and practice behind many of today's communications systems,
covering data compression, scalar and vector quantization, sampling and aliasing, the Nyquist criteri
Digital communication :: 23.10.2012 16:36 :: seouldavid :: Replies: 0 :: Views: 125
I don't see how. The IIR feedback path has to be closed with 1 clock cycle delay.
If you double all the registers in the IIR filter then you can organize the pipelining.
But you get two filter channels, and a single filter cycle increases in two clock cycles,
and due to the pipelining the clock cycle can be decreased u
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.12.2012 21:06 :: Aser :: Replies: 14 :: Views: 290
designing digital pid...
well,are u familaiar with Digital Signal Processing?
if no,u can learn it very fast specially i recommend u to read the well known book writen by Alan V.oppenheim:Discrete-Time Signal Processing
designing a digital copy of an analog system like filters and controllers with feed back is described in this book chapter seve
PC Programming and Interfacing :: 30.12.2002 20:57 :: goodboy_pl :: Replies: 14 :: Views: 9413
In general some should look at the dynamic range of the signal to be quantized. For instance if some assume a sensor with signal of 1 mVrms and noise of 10 nVrms over the sensor signal bandwidth, the dynamic range is 10^5. For an ADC to accuratelly quntize such signal, the ADC quantization noise (Q/SqRt(12)) RTI should be at least three (...)
RF, Microwave, Antennas and Optics :: 13.02.2003 09:00 :: RegUser_2 :: Replies: 8 :: Views: 1664
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