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75 Threads found on edaboard.com: **Sampling And Quantization**

i have one doubt.
when A **and** B system are cascade, then if the system is linear time invariant system even A **and** B are interchanged, no change in result.
quantizer is a nonlinear system. but even the **sampling** **and** **quantization** is interchanged the entire result is unchanged **and** same result (...)

Analog Circuit Design :: 13.08.2013 11:04 :: rameshbalan :: Replies: **3** :: Views: **230**

When you sample a continous signal (a continous signal is something like sin(w*t), you can find its value for any time t), the signal exists only at the **sampling** instant (like t=1s, 2s, 3s, ...). Else the signal is not zero, but doesnt exist.
The signal can be quantized, which means that the signal is now restricted to have a few voltage level

Digital communication :: 17.08.2007 01:09 :: bulx :: Replies: **2** :: Views: **3043**

There are a few problems with your code...
The best way to define a sinewave is:
A=1;
n=7;
N=2^n; % simulation length
fs=1e2; % **sampling** frequency
t=(0:N-1)/fs; % time (**sampling** points)
f=3*fs/N; % sinewave frequency
x=A*sin(2*pi*f*t); % cw sinewave
r=10; % number of bits of resolution
R=2^R; % number of **quantization** levels
q=fl

Digital Signal Processing :: 05.02.2010 14:27 :: JoannesPaulus :: Replies: **7** :: Views: **1911**

I think you need some basic underst**and**ing of ADC. First **sampling** **and** **quantization** then switch to concrete ADC architecture

Analog IC Design and Layout :: 06.03.2011 06:58 :: wanghs1986 :: Replies: **14** :: Views: **1544**

Hi,
I hope you are not looking for DIRECT digital down conversion.
I had used digital downconversion for a GPS receiver. It is fairly easy. you follow in digital all the process of analog. However you need to be careful about **sampling** **and** **quantization** levels.
B R
Madhukar

RF, Microwave, Antennas and Optics :: 26.01.2005 02:33 :: brmadhukar :: Replies: **2** :: Views: **699**

Hi all,
I am wondering for a 12-bit resolution ADC, how big of a **sampling** capacitor at the front end should be in order to surpress the kT/C noise **and** opamp thermal noise from the later stages?
Peoples used 6pf before, I think it is way too big. Any ideas?

Analog IC Design and Layout :: 09.03.2006 06:12 :: Analogworld :: Replies: **3** :: Views: **1324**

To convert an analog signal into digital signal two steps are required
1. **sampling**
2. **quantization**
We can perform these operations in any order to get a digital output.But why it is common to do **sampling** first?
Looking forward for reply.
Thanx in advance.

Electronic Elementary Questions :: 10.03.2006 11:34 :: sheraz.pervaiz :: Replies: **16** :: Views: **4106**

Dear all
I need the following the paper, but i don't access to it, if you can ,pls send it for me.
thanks you for your help.
Chang,H., ?Pre**sampling** filtering,**sampling** **and** **quantization** effects on the digital matched filter performance? Proceeding of International telemetering conference,pp.889-915,San (...)

Digital communication :: 31.01.2008 04:08 :: scottxin :: Replies: **1** :: Views: **1190**

I need mathematical examples about the subjects in image processing:
-filtering in the spatial domain.
-filtering in the frequency domain.
- Histogram equilization.
-Image **sampling** **and** **quantization**.
-Gray Level Transformations.
Anyone can help me in that?

Digital Signal Processing :: 05.01.2009 05:33 :: ahmadaltaan :: Replies: **1** :: Views: **597**

Hi all
What is the relationship between "**sampling** frequency" **and** "**quantization** noise" in audio signals?

Digital Signal Processing :: 05.03.2010 04:31 :: meher81 :: Replies: **0** :: Views: **728**

how to design a over-**sampling** filter to reduce quantium noise in the process of DA converting for audio playback???can you tell me the general theory about it??**and** what useful book i can refer to ????

Digital Signal Processing :: 26.11.2005 06:54 :: ls000rhb :: Replies: **1** :: Views: **553**

Hi
Process gain is defined as improvement in signal to **quantization** ratio when using over**sampling**.
PG = 10 * log10(fs / (2 * BW))
BW = output BW after decimation.
To calculate PG you need to know BW, so specify the output BW or decimation ratio then i can help you.
Regards

Analog IC Design and Layout :: 13.12.2005 02:33 :: Circuit_seller :: Replies: **4** :: Views: **594**

Analog Circuit Design :: 06.06.2006 12:14 :: svensl :: Replies: **2** :: Views: **759**

u can use the wavread comm**and** to read the file
**and** wavplay to play the wav file
note in the above two methods u can change the bits/sample **and** **sampling** frequency. but i suggest u to use a wav file which is sampled at 8k si that u can get a nice output.
as a wave file is a digitized oneu cannot quantize it again u can (...)

Digital Signal Processing :: 25.01.2007 06:52 :: rsrinivas :: Replies: **2** :: Views: **2241**

Hi, all
I noticed for some SD ADC designs, ppl use CDS to decrease integrator leakage **and** flicker noise. For those of designs that circuit noises are the dominant noise sources (i.e. **quantization** noise is not so obvious), how can I model flicker noise **and** white noise properly if CDS is employed? thanks.
-TiwstedNeurons

Analog IC Design and Layout :: 05.03.2007 16:36 :: TiwstedNeurons :: Replies: **5** :: Views: **2436**

you should choose anathor **sampling** frequency.
for example, fs=64MHz.
as to your said,fin/fs=Mc/M. however, Mc must be integer.right? you should check it. I found your choose is wrong.:)
if it's still wrong, you can upload the results image. let us discuss it.

Analog Circuit Design :: 08.03.2007 02:34 :: renwl :: Replies: **14** :: Views: **10123**

Hi all,
I have been searching about **sampling** rate setting of an ADC.
What is the main criteria (or criterias) of its operating rate? Clock frequency, equipment's time delays, or what?
Please, would you like to explain how does manufacturer set this **and** how user use it?
Thanks, best regards
Added after 12 minutes

Digital Signal Processing :: 08.06.2007 05:21 :: haydaa :: Replies: **10** :: Views: **8194**

An analog, low-pass filter prior to the input of the ADC eliminates or significantly reduces aliased noise. The corner frequency of the filter must be lower than f**sampling**/2. Increasing the order of the filter can minimize the noise.

Electronic Elementary Questions :: 13.06.2007 04:06 :: svicent :: Replies: **13** :: Views: **847**

In 2001, Abidi published a paper of "A 6-b 1.3-Gsample/s A/D Converter in 0.35-um CMOS".
Only 6-bit resolution is required, however, Abidi **and** Michael Choi added 1pF as input **sampling** capacitor. The thermal noise due to KT/C is only about 2mV, which is much lower than LSB **quantization** noise. Why they put so much capacitance there (...)

Analog IC Design and Layout :: 10.07.2007 10:37 :: neoflash :: Replies: **0** :: Views: **513**

I want to know the relation of spur **and** non-linearity in ADC **and**
what is the difference between harmonic **and** spur?
in ADC because of non-linearity, input driving **and** s\h circuit
at output we see that harmonics of input signal appear at ADC
spectrum.
The ideal ADC has the **quantization** noise (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 05.09.2007 07:21 :: fanisani :: Replies: **0** :: Views: **488**

I want to know the relation of spur **and** non-linearity in ADC **and**
what is the difference between harmonic **and** spur?
in ADC because of non-linearity, input driving **and** s\h circuit
at output we see that harmonics of input signal appear at ADC
spectrum.
The ideal ADC has the **quantization** noise (...)

Analog Circuit Design :: 05.09.2007 07:23 :: fanisani :: Replies: **9** :: Views: **2918**

After **sampling** the discrete signal has to be rounded to its nearer digital value. hence we go for **quantization**.

Digital communication :: 26.05.2008 07:14 :: sanforu.salem :: Replies: **4** :: Views: **3111**

Hi!
What type of resolution:
* in amplitude, in phase, in frequency, etc.?
Normally you should know at least:
* the signal **sampling** factor (SSF) N = Fdigitalization /F signal
* the number of the accurate bits n
* the moment (angle) of the first sample
* the total number of bits
* the frequency b**and** of the signal...
BR

Digital Signal Processing :: 08.09.2009 03:04 :: Petre Petrov :: Replies: **4** :: Views: **531**

hi one query
for 10bit Nyquist Rate ADC .
i am giving 1k signal input **and** **sampling** frequency is 4MHz.
then what snr i expect therotically.
snr = 6.02N+1.76 ==> 61.96dB
but i have seen the snr equation is SNR=6.02N+1.76+10log(OSR)
here i am applying the input fin=1k **and** fsamp= 4M
so the OSR = fsamp/2*fin = 4M/2K = 2000
hence total (...)

Analog IC Design and Layout :: 13.08.2010 00:35 :: manissri :: Replies: **5** :: Views: **1066**

If you do not use "coherent **sampling**" you need to apply a window function to your signal before the fft, see below.nsignal=4096;
fs=44100;
f=1001*fs/nsignal; % coherent **sampling** i.e. integer number of cycles (1001) in nsignal samples
%f=1000; %non-coherent **sampling**. Use hann window below
t=/fs;
y=1*sin(2*pi*f*t);
w=ones(nsignal,

Analog Circuit Design :: 04.11.2010 16:49 :: JoannesPaulus :: Replies: **1** :: Views: **1493**

Hello,
I am trying to implement a behavioral model of a delta modulator in Matlab, consisting of an ideal comparator **and** a summing unit in the feedback path. Unfortunately the spectrum is not flat as expected **and** I get peaks at odd harmonics of the signal frequency (cf. attachment).
Does this behavior occur because the **quantization** noise (...)

Digital communication :: 03.05.2011 11:27 :: Matata :: Replies: **0** :: Views: **459**

Look into jitter analysis of ADC's, Phase modulation, **and** DDS systems. Each can be helpful.
the uncertainty generates sidelobes for the same reason phase modulation does. The equivalent index is low, so you probably will only see one sidelobe. The effects become more pronounced for high-speed ADC's **sampling** signals above Fs/2 (b**and**pass (...)

Digital Signal Processing :: 03.06.2011 21:03 :: permute :: Replies: **2** :: Views: **413**

Hi,
i have some doubts regarding following questions:
how increase in **sampling** rate reduces resolution?
how dithering helps in sigma delta adc?
what actually noise shaping is?
any help would be greatly appreciated **and** thanks in advance.

Electronic Elementary Questions :: 05.09.2011 11:20 :: amit.31 :: Replies: **12** :: Views: **1408**

Runge Kutta is for solving differential equations, which is a completely different problem than calculating the integral of a sampled waveform. Provided that the requirements of the **sampling** theorem are fulfilled (no spectral components of the signal higher than 1/2 of **sampling** frequency), the time-discrete signal processing operations can be exact

Electronic Elementary Questions :: 28.02.2012 11:24 :: FvM :: Replies: **9** :: Views: **1150**

i have code matlab of this compression but i have a probleme in the party of lloyd max ? i need for ur help plz
i put only the party of max lloyd quantification
% Lloyd-max algorithm using signal values
% Signal : Signal Vector
% tol : Tolerance
% Initial : **sampling** levels
% dist : distortion
% qua

Digital Signal Processing :: 10.05.2012 14:25 :: ms13 :: Replies: **0** :: Views: **410**

Came across these on a website, no answers though..
Guess it would be benificial to everyone if we can answer these!
1. What are the factors you consider for the selection of ADC ?
3. How do you determine the number of bits of ADC is required for you ?
4. Which factor determines the number of iterations in SAR done to approximate the input

Analog IC Design and Layout :: 11.06.2013 14:46 :: blackdragon12 :: Replies: **1** :: Views: **418**

designing digital pid...
well,are u familaiar with Digital Signal Processing?
if no,u can learn it very fast specially i recommend u to read the well known book writen by Alan V.oppenheim:Discrete-Time Signal Processing
designing a digital copy of an analog system like filters **and** controllers with feed back is described in this book chapter seve

PC Programming and Interfacing :: 30.12.2002 14:57 :: goodboy_pl :: Replies: **14** :: Views: **10326**

In general some should look at the dynamic range of the signal to be quantized. For instance if some assume a sensor with signal of 1 mVrms **and** noise of 10 nVrms over the sensor signal b**and**width, the dynamic range is 10^5. For an ADC to accuratelly quntize such signal, the ADC **quantization** noise (Q/SqRt(12)) RTI should be at least three (...)

RF, Microwave, Antennas and Optics :: 13.02.2003 03:00 :: RegUser_2 :: Replies: **8** :: Views: **1852**

Hi,
Noise in pass b**and** is mainly due to
1) Amplification of thermal noise in the b**and** of interest. Remember that most of the times thae gains will be around 100dB or more in RF systems.
2) Intermodulation products, Harmonics of clocks, etc contribute more noise.
3) **quantization** noise during **sampling** if any (...)

RF, Microwave, Antennas and Optics :: 13.03.2003 06:34 :: brmadhukar :: Replies: **3** :: Views: **2542**

Hi,
SDM increases the **sampling** rate **and** using a Delta modulator kind of structre reduces the **quantization** noise. However this comes with a price. You need to use more number of bits for representation. It is very expensive for communication receivers. I hope you have considered this.
B R
Madhukar

Digital Signal Processing :: 20.01.2005 01:50 :: brmadhukar :: Replies: **5** :: Views: **2263**

I need you advice in choosing a precise DSP filter.
I need an DSP chip. IC.
I like to use it this filter as notch Filter to block certain frequency range but not limited of being flexible as an application may want.
Frequency range to block is 0.5Hz to 2Hz, or 0.5-1Hz.
The signal passing this filter will be a sinusiod from 0.1Hz to 10H

Digital Signal Processing :: 12.01.2004 21:04 :: djalli :: Replies: **6** :: Views: **1865**

Well, it really depends on what 'order' of SD adc you have.
The SNR is related to the resolution of the convertor **and** the amount of **quantization** noise.
Here's the way of calculating it:
I was always told in university that whenever you double the samping frequency, its like adding another bit **and** a half to the resolution.
But thats (...)

Digital Signal Processing :: 25.06.2004 01:53 :: Buriedcode :: Replies: **5** :: Views: **2511**

The **quantization** noise is spread across the frequency range from 0 to the **sampling** frequency. If you sample twice as much, the qunatization noise density is half. It is to your advantage to sample much higher than the Nyquist frequency. If you do not want to carry the high data rate further in the system, you can low pass filter using more bits

Analog Circuit Design :: 01.07.2004 23:21 :: flatulent :: Replies: **10** :: Views: **6241**

What is your DAC sample rate? I'm guessing it's slower than 24MHz. As brmadhukar suggests, you need a low pass filter after the DAC to reject **sampling** images (they look like stair steps on an oscilloscope). Design a filter that passes the frequencies you want, **and** strongly attenuates the sample rate **and** higher.

Microcontrollers :: 31.08.2004 17:43 :: echo47 :: Replies: **4** :: Views: **965**

Hi,
I am desiging a sigma-delta modulator in 0.35um technology having 5-bit coarse **quantization**. For the switch capacitor integrator, I have chosen 32 **sampling** capacitor (Cs) of value 0.3pF each. **and** the value of integrating capacitor (Ci) is 32*0.3=9.6pf.
Please suggest me some good layout technique for capacitor of this much large (...)

Analog IC Design and Layout :: 15.05.2005 01:56 :: meghna :: Replies: **8** :: Views: **1268**

Hi Kris,
on the fly I can answer question 2. You have a 10 bit resolution that means 2 in the power of 9 ( binary: 2x1+2x2+2x4+....+2x512=1023 ==>1111111111 max value) or 1024 different combinations. That means that 1 bit represents the analog value of 5V /1024= 0.02441 V is your sensitivity. so if you now measure 0.2 the output will be 0.2/0.024

Electronic Elementary Questions :: 02.06.2005 10:39 :: dkace :: Replies: **3** :: Views: **1487**

SNR is in the desired b**and**width. If you oversample, the **quantization** noise is spread over a wider frequency range **and** the noise in your desired signal b**and**width goes down. You have to LPF the DAC output because it makes signals at large multiples of the **sampling** frequency plus **and** minus (...)

Analog Circuit Design :: 09.06.2005 00:35 :: flatulent :: Replies: **6** :: Views: **2363**

i think your question is not so clear...
basically, to convert an analog signal to digital:
**sampling** then quatization.

Professional Hardware and Electronics Design :: 02.07.2005 12:19 :: banh :: Replies: **5** :: Views: **1438**

I has these IEEE papers about NOISE FOLDING **and** could upload them:
1. An approach to tackle **quantization** noise folding in double-**sampling** /spl Sigma//spl Delta/ modulation A/D converters
Rombouts, P.; Raman, J.; Weyten, L.;
Circuits **and** Systems II: Analog **and** Digital Signal Processing, IEEE (...)

RF, Microwave, Antennas and Optics :: 21.12.2005 16:15 :: aho1363 :: Replies: **1** :: Views: **1484**

what is the resolution in ur design?
if the resolution is small then how much is the **quantization** noise level? if big then how about the thermal noise in the sc? how about the dc gain of ur opamp?
if everything ok, then you have to increase the # of points in fft **and** meantime you have to use coherent **sampling**,that is u have to make sure (...)

Analog Circuit Design :: 23.03.2006 12:57 :: arsenal :: Replies: **3** :: Views: **1075**

In audio signal compression, people would like the **quantization** to be white **and** independent of the signal. To this end, the characteristic function of the signal should be "b**and**limited". Dither is like antialiasing filter in **sampling** theory to limit the "b**and**" of the signal's characteristic function when (...)

Digital Signal Processing :: 15.08.2006 07:19 :: carrierhit :: Replies: **8** :: Views: **2863**

Hi
I can give some ideas about how to caculate needed SNR at the input to the ADC. Obviously this is heavily dependent on ADC dynamic range, SFDR, **sampling** rate **and** more ....
I think that the best solution is to study a complete datasheet of an ADC. is a very great source. Also texas instruments provides valuable info.

Digital Signal Processing :: 12.06.2006 11:28 :: mami_hacky :: Replies: **2** :: Views: **650**

I am designing a 10bit pipeline ADC. The schematic simulation shows that the odd harmonics are too large(especially,the third harmonic is 55dB).
Can anybody give me some suggestion on how to find the reason?
Thanks.
**sampling** swith
opamp (settling time)
reference (settling time)

Analog Circuit Design :: 20.09.2006 04:27 :: wdd :: Replies: **8** :: Views: **1432**

I think Fin **and** Fsample shoudl satisfy:
fIN / fSAMPLE = NWINDOW / NRECORD,
fIN: Periodic input signal
fSAMPLE: **sampling**/clock frequency of the ADC under test
NWINDOW: Integer number of cycles1 within the **sampling** window, prime number
NRECORD: Number of data points in the **sampling** window or FFT

Analog Circuit Design :: 21.11.2006 19:30 :: benchen :: Replies: **4** :: Views: **747**

Thesis: A Superconducting B**and**pass Delta-Sigma Modulator for Direct Analog-to-Digital Conversion of Microwave Radio
by John Francis Bulzacchelli
Massachusetts Institute of Technology,2003
This thesis examines the potential of superconducting technology for realizing RF analogto-digital converters (ADCs) with improved performance. A b**and**pass

Analog Circuit Design :: 29.11.2006 23:34 :: flysnows :: Replies: **0** :: Views: **672**

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square graph | settle time | uart 18f4550 | matlab netlist | 1db compression point mixer | coupled inductors | orcad dxf files | microcontroller mp3 player | photodiode receiver circuit | split radix