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133 Threads found on Sdram Data
I did a design using the DLP3000 with its controller. I based my design on the evaluation board just with less sdram (128MB instead of 256MB) and no FPGA. The functionality of the FPGA was to provide video data to the DLP controller. So put a video decoder down with BT656 digital output. The board functionality is controlled by a AVR32 cpu. Ever
I am using DE1-SoC to start bare-metal programming for dual-core Cortex-A9 ARM hard processor, Cyclone V. I'm trying to read data from sdram to FPGA using FPGA-to-HPS sdram Bridge. I configured FPGA-to-HPS sdram interface in qsys to use avalon-MM Read only, 32 width. I exported FPGA-to-HPS sdram (...)
Hi I want to read data from a ddr3 sdram. I'm using vivado. my memory model is M471B2873FHS which is not mentioned in the "xilinx memory interface generator". what should I do? thanks. ( I apologize for my bad English ).
Hi! I want to use a Raspberry Pi to read/write data to DDR3 sdram. JEDEC DDR3 standard: sdram have 240 pins (most are GND, VCC). 64 data
1) Yes, you could use sdram for buffering, but the FIFO is MUCH easier. The FIFO will tell you when it's got data available, when it's empty, when it's full, etc. The sdram won't. 2) I don't know about Quartus, but I don't believe you'll find a UART core with built in FIFO, you'll need two separate cores, but it's not really a big deal. 3) (...)
Hi, I have a Nios system with Qsys components such as Interval timer, UART, sdram and some PIOs. My system specifications are DE0 Nano, Quartus 12.1 sp1, Altera monitor program. Nios II system are interfacing with several VHDL blocks. I am able to read data from FPGA to Nios processor, then transmit this data to Uart component
Hi. I'm trying to use MIG Tool for transferring data on DDR3 SDRM. My component is MT41j64M16JT , with 16bit data bus and DDR3 clock rate of 400MHz. I simulated the example design of MIG to measure transfer rate. It seems to be approximately 1050MB/s for write or read. I want to know is that maximum rate? How can I increase this rate? so
Hello, everybody! I have some misunderstanding about VIH(ac)\VIL(ac) SSTL levels. Timing specification for DDR3-1066 sdram normalized by this levels, for example data setup time tDS is 25ps@AC175 and 90ps@AC135. Which one of all levels I should use in my timing budget calculation? Levels are determined by configuring the controller? or they ar
Hello, i'm working with LPC1788 and i have working LPC1788 development board, in that development board 2 sdram use for LCD data One sdram for D0 to D15 and other for D16 to D31, all control lines and adress lines are common for both sdram. this board work fine. sdram use: 4M X 16 bit X 4 banks Part (...)
Hi all, I am working with a pcb with 4 sdram chips (TSSOP package) .data, address ,control and and clock are connected to all the 4 sdram chips. What is the routing strategy that i should follow.What should be the length of the signals. Thanks in advance
Hi everyBody, I implement an xps system by using the Bus PLB. My IP core is added to the system using Create or Import Peripheral... I want to know how can Microblaze write several data to DDR2 sdram and how the IP core read all the data from this memory, modify it and write it back to DDR2 sdram via the PLB Bus (...)
Hey guys I am working on implementing the algorithm of 2D DCT on Nexy2 from Digilent, which is based on Xilinx Spartan 3E. My main concern is data precision and its implications on the memory. The board has 16MB sdram (which I am planning to use for this calculation) and 16MB Flash Memory (which i'm only planning to use to fetch constant da
Hi, I want to obtain a 128 word burst transfer of data from sdram to BRAM in Nexys 2 board. I have gone throught the nexys 2 reference manual and sample code given at their product page. But that is asynchronous mode read. I want to obtain a burst mode transfer. Also i want to know about the burst transfer to the BRAM from the sdram. I am (...)
hay!! i cant figure out the size of block in this specific DDR in vertex 4, can anyone tell me what is the block size this DDR Vertex 4 contains 64 MB of DDR sdram using two Infineon HYB25D256160BT-7 (or compatible) chips (U4 and U5). Each chip is 16 bits wide and together form a 32-bit data bus capable of running up to 266 MHz.
Hi I have problem about to write sdram. Column address 256, row address 4096, bank 4. When i get image data from camerasensor, the data size is 2592. But sdram's row address is only 256. The image data coming through 2592 to sdram but when i use full page mode, It's need to (...)
Hi I have a problems about how can i get data from camera data to sdram. sdram is HY57V281620ETP-6 and camera's data is 8bits And resolution is 2592x1944. So i want to know what is best way to write to sdram? Pull page? Burst 1,2,4,8? I can't decide about this way. Please help me.
Hello, i'm using Texas Stellaris LM3S9B96. First I am designing the board, so I have to do all the wires between all components and the microcontroller, so when software will be developed everything will be ok. I would like to use a sdram and a CPLD at the same time. The idea is to use address/data bus for both these components, in order to save
hello, i am trying to transfer the data to ddr2 memory using stratix3 board.I am using the ddr2 sdram high performance Mega function.I am using the transcend (1G ddr2 memory) but in memory presets no option for Transcend.Can we use any others standards mentioned in that memory presets?
Can a memory controller support ECC if the sdram used has a width of x16? - - - Updated - - - And is it possible to use 5 of the x16 chips to create a 72 bit width data bus, and still use ECC? Thanks a lot!
hello, I'm doing something about the sdram which controled by XILINX, but I haven't know regard to the sdram. I research something about sdram to you, so can you send some resource to me of sdram or reference code to help me complete my program. I'm great to wait your repeating.
Here is an RGB solution But not a very useful or practical one.
how to store a .wav file in sdram of nexys 2 board of spartan 3E?
Kindly go thru the link sdram is same as like DDR,ensure thet all address line should be connected to the same I/O bank and data lines to be the same I/O Bank
The term ?DDR? stands for Double data Rate RAM. This term came into use at the turn of the century when the first Double data Rate RAM modules arrived. Double data Rate RAM was capable of two data transfers per clock cycle, giving it twice the theoretical peak bandwidth of previous sdram while running at the (...)
Aside from a bad sdram, there might be a timing issue. Did you do a timing simulation or just a functional simulation? Or, your FPGA might be writing to the RAM when you don't intend to. You might also look at your PCB trace lengths, if there is significant differencs in length, and you're running at high speeds, there might be a skew problem.
when im working my project . it raises a problem : how to read a image file from memory . so , i should use sdram , Sram , Sdcard for easier (don't use nios) .. i also want to ask : how to convert .png file to .HEX file ?
Hi all, I am interfacing DDR2 sdram Controller in FPGA and I don't understand how can to read and write data to memory device using Microblaze processor and DDR2 sdram controller?. I'm studying about this controller and I don't know the operation of DQS signal in transferring data and the mechanism of delay DQS. who can (...)
Hi, Can anyone help me in understanding the below two sentences especially the second sentence: The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 sdram consists of a single 8n-bit wide, four clock data transfer (...)
Hello Friends, In High-speed layout, all the address and data busses nets are connected parallel with multiple DDR-sdram, What is the preferred routing topology Thanks, Jay
I am using ODDR and IDDR at Xilinx for DDR2 sdram controller. ASIC library has the data rate (DDR) register similar to ODDR/IDDR ?
Before to use mig you need to choose witch memory do you want to use. For example DDR2 by micron and look at the data sheet about DQ an DQS. Dq is the data and DQs is strobe associed to this data. more info at: XAPP858 - High-Performance DDR2 sdram Interface data Capt
I'm starting a new design that requires the quick transfer of a few megabytes of data between a FPGA and a microcontroller. The FPGA is the Altium Cyclone IV processor (EP4CE15F17I8L), and the microcontroller is the AT91SAM9RL64-CU microcontroller, which is an ARM9 chip with external EBI bus. Attached to the FPGA is a SDR sdram from Micron (M
Hello, You don't have to use specific pins for SDR sdram (except for the memory clock where you'll use a pll output pin).
hi sunny, you can get the idea from altera forum. How to load a picture to sdram? - Altera Forums or the reference design from
the 9260 has 8 KBytes data Cache, 8 KBytes Instruction Cache, MMU • Memories – 32-bit External Bus Interface supporting 4-bank sdram/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC – Two 4-kbyte internal SRAM, single-cycle access at system speed – One 32-kbyte internal ROM, embedding bootstrap routine
Hi, Now, In my design, there are 16 ADCs and an FPGA, the FPGA controls the ADCs and receives the data from these ADCs. Besides the FPGA, there are other digital circuits(DSP, sdram), in other words, the digital section is very noisy. Also, there RF amplifier and RF switch on the analog section. I plan to isolate the ADCs from Digital section
dear all i am using ise 12.1 (ip core-> memory interfacing generator) i read about this tools and i know that it is {tool generates DDR sdram interfaces Spartan-3E. The tool takes inputs such as the memory interface type, FPGA family, FPGA devices, frequencies, data width, memory mode register values, and so forth, from the user through a grap
Check Xilinx web site and you find lots of app notes and tutorial on how to use the DDR controller. If you have access to EDK, then things will be much easier. Otherwise you have to make some tricks to get things to work properly. This is from the DDR access on Spartan 3E 500 Starter Kit
Hello, I am trying to send data between 2 devices, non of them is a PC. The first one read data from DDR2 sdram memory. I want to send this data to the second device using an Ethernet connectivity. (The hardware is implemented on FPGA development board.) My question is: Can we directly send the (...)
The manual says: A 256 Mbit sdram provides volatile data storage accessible by the FPGA. Which means 32 Mega words x 16 bits = 256Megabits The sdram used on this board is Samsung K4S561632Edatasheet can be foun
Hi friends i have write the vhdl code for sdram in that i have write the array of data in the data bus during each clock bus but when i read the data from sdram i get the last byte of the array during the all the read cycles.
Hello. I am trying to set up a DDR sdram controller in my SOPC build in Quartus and am confused about a couple of things. The memory I am trying to create the controller for is a 512M Qimonda IC, 32Mx16: One problem is the column width. As I understand it:
hi guys, i want to interface sdram IS42S16160B with vertix 5 FPGA. we want to write data on sdram and then read it back, but we are facing some problem. Here is a part of code which we have written. we need some help. Regards Talha INIT: begin (...)
hi all... i'm new to the field of FPGA... and i'm using XSA 50 board, i wanted to know how can i access the sdram attached to the board to store and retrieve data... i'm using verilog ... any idea's....
I have my lpc2478 to display bitmap to color tft lcd , as my bitmap is 3517KB and keil c show me no data space is available . I have made sdram config as follows: //sdram config #define sdram_BASE_ADDR 0xA0000000 #define sdram_SIZE 0x04000000 //64MB what method am I missing ????
If I understand correctly that testbench is made by Micron for the purpose of verification, right? As in not for the purpose of synthesis. If so, then I would not be surprised if it doesn't do what you want when synthesized. To interface the spartan3 to sdram you need some sdram controller IP from xilinx, or from places like [url=opencore
Hello everyone and I hope, for my first post, this is the proper place for this topic. I used to work with a company that used only RAM memory allocation for all daily server data, leading to that they had a massive UPS running all the time and a very fast "hard disk" I/O management as they did not per say have a hard disk. I was toying with
Either, sdram may give you a higher data bandwidth. Is the FPGA clocked of the same clock from which the processor bus timings are derived? If not (data inputs to the FPGA are asynchronous to it's clock) then you'll have to synchronize the inputs to prevent metastability problems (pass them through a couple of d flops clocked by the fpga (...)
what is the significance of data strobe and data mask in DDR sdram" Regards kil
Memory Initialization can be summarized as follows: 1. Memory Controllers Setting 2. Copying RW data to sdram 3. Copying RO data and Code to ROM 4. Initializing Stack -- Amr Ali