47 Threads found on edaboard.com: Sequence Detector
so easy problem....
search 'sequence detector' in google.
ASIC Design Methodologies and Tools (Digital) :: 23.01.2004 06:25 :: bigrice :: Replies: 5 :: Views: 3391
iam doing vlsi diploma in scl. iam getting lot of douts on fsm specially sequence detector like 100010110 for this type and also 1100xx10 with overlapping and nonoverlapping can any one explain how to draw state diagram for this type of problems
Electronic Elementary Questions :: 18.09.2005 08:31 :: ravimalladi :: Replies: 4 :: Views: 5756
any one have a good material about the ML sequence detector and symbol-by-symbol MAP detector, specially the mathmatics and the probability to be very clear and easy to understand, i.e.: step by step explanation.
of cource other than Praokis's book.
Digital communication :: 22.06.2007 21:49 :: saeddawoud :: Replies: 3 :: Views: 875
I need detailed information regarding sequence detector.Can any one send me
where can i get this?
Thanks in advance
ASIC Design Methodologies and Tools (Digital) :: 30.09.2007 08:21 :: Preddy :: Replies: 3 :: Views: 793
if i remember correctly, then Prof. Srinivasan in this lecture, implements
twice this sequence detector... The one of the two implementations he talks
about is the one you are interested in... I believe that it should be best for you
if you carefully watch this presentation and then come up with a solution.
We will hel
ASIC Design Methodologies and Tools (Digital) :: 13.11.2008 04:21 :: pmat :: Replies: 3 :: Views: 6364
I am new to verilog, and need to simulate a 4-bit pattern/sequence detector into modelsim and then Xylinx for the spartan 3 board.
The pattern that needs to be dected is 1101.
Any help would be greatly appreciated!
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.04.2010 14:19 :: VerilogNoob07 :: Replies: 0 :: Views: 1485
Can any one tell about the VHDL code for an asynchronous sequence detector(i.e. without any clock input and only data input).Output should change as soon as input changes.(For 2 bit or 3 bit input)
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.04.2010 15:08 :: jaybarot :: Replies: 0 :: Views: 1039
Here the code for a 11010 sequence
parameter st0 = 3'b000,
st1 = 3'b001,
st2 = 3'b010,
st3 = 3'b011,
st4 = 3'b100
ASIC Design Methodologies and Tools (Digital) :: 06.02.2007 09:17 :: rakesh_aadhimoolam :: Replies: 2 :: Views: 2286
Use the state machine approach. When the first bit (MSB here) occurs, move to the next state. If the second bit matches, move to the third state and so on till the required sequence is achieved. If, the sequence breaks in any intermediate state go back to initial state. If the sequence matches, in the last state (match state) assert the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.07.2009 13:13 :: thiagu_comp :: Replies: 5 :: Views: 3631
For a sequence of 1010 i.e. 4 bit number , you require 4 states . After detecting all 4 bits correctly , output will be 1. You can use mealey or moore techniques.
Lecture 7 - Sequentional Circuits Design - YouTube
Analog Circuit Design :: 13.02.2012 11:57 :: jeet_asic :: Replies: 1 :: Views: 1026
See the ''11011'' sequence detector as an example.
---------- Post added at 10:57 ---------- Previous post was at 10:53 ----------
Example how to implement 1011 sequence detector circuit in VHDL:
ASIC Design Methodologies and Tools (Digital) :: 13.04.2012 03:57 :: mister_rf :: Replies: 2 :: Views: 491
I want to design a circuit that will detect a very long sequence, A2 F3 D2 F1 E4 17 AB 56 76 A2 C4 B2 FF 00 12 34 AA BB B3 A4 6E 1F 4D 1E, where all numbers are hexadecimal and hence every pair forms a 8 bit pattern ( ie 1E = 00011110 ), it also needs to set a flag bit high if one number (e.g A ) is detected, and another flag bit high if the entire
PLD, SPLD, GAL, CPLD, FPGA Design :: 07.10.2012 19:01 :: KillaKem :: Replies: 10 :: Views: 728
I need to synchronize an inverter to the power grid. So far I can easily track 3-phase voltages with high immunity to noise and other power failures. I am using a abc->dq conversion (3phase to 2phase, rotating frame) and with this I can easily track the phase, the sequence and peak voltage.
I need to track now single phase signals. I h
Analog Circuit Design :: 07.06.2004 17:37 :: mfilippa :: Replies: 0 :: Views: 922
You should use the following sequence: wire antenna, broad band RF amplifier, diode detector, indicating method.
A simpler method which is not as sensitive is the wire, diode, oscilloscope.
Hobby Circuits and Small Projects Problems :: 13.11.2004 14:15 :: flatulent :: Replies: 8 :: Views: 5211
i would like to know how can i make a phase sequence using microcontroller and how can define the phases ( r s t ) and ( r t s )
Professional Hardware and Electronics Design :: 01.04.2005 15:32 :: bluethunder7000 :: Replies: 2 :: Views: 2319
A finite state machine has a limited or finite no. of possible is mainly used as a development tool for solving problems. For example in DIgital electronics a sequence detector problem- which has to detect a particular pattern only and provide output only for the required pattern. A infinite state machine can be conceived but it is not pr
Electronic Elementary Questions :: 18.06.2005 02:57 :: rajavel :: Replies: 2 :: Views: 2580
It's maybe for sequence detection.
The register previous is to store input streem.
ASIC Design Methodologies and Tools (Digital) :: 08.12.2005 03:13 :: zhangpengyu :: Replies: 5 :: Views: 985
The hint given by you is good. I work it and find the answer.
I have another Question
1.How to detect a sequence of "1101" arriving serially from a single line?
2.How to detect if two 8-bit signals are same?
Draw a state diagram for a sequence detector (overlaping or non-overlaping). The
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.11.2006 01:45 :: xstal :: Replies: 10 :: Views: 1475
I have started a short project about color lighting RGB Led is sequence to strike their light onto the object i want to detect, then LDR will get the reflected light from the object and make the voltage drop on the circuit(voltage devider).the voltage drop will get digitized by the ADC0831 to microproccessor(AT89S51) which pro
Hobby Circuits and Small Projects Problems :: 19.03.2007 11:42 :: ghasia :: Replies: 3 :: Views: 2099
we can detect a modulation technique with memory by using either ML sequence detector or symbol-by-symbol MAP detector. this is explained in "Digital Communication" Proakis, but it is very hard to understand.
Any one have a good resources for this material and the original papers.
Digital communication :: 19.06.2007 04:51 :: saeddawoud :: Replies: 1 :: Views: 890
Hi, I need to design a 0110/1001 sequence detector which produces a 1 output if the current input and the previous three inputs correspond to either the sequence 0110 or 1001. The output 1 is to occur at the time of the forth input of the recognized sequence.
Anyone can draw the state transition diagram? I'm not sure the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.04.2008 05:49 :: kingmaker :: Replies: 9 :: Views: 3259
plz send me materials or links related to design a vhdl code for mealy and moore finite state machines for overlapping and non-overlapping binary sequence detector and its state diagrams.
thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.04.2008 05:11 :: vijayganesh :: Replies: 2 :: Views: 1498
need a circuit for a phase sequence/phase failure detector in a three phase ac power supply
Professional Hardware and Electronics Design :: 31.10.2008 03:10 :: Hafsat :: Replies: 2 :: Views: 3414
To detect all cases of failure, a professional voltage monitoring relay measures three interphase voltages, optionally the star point voltage against neutral and possibly phase sequence. Depending on the equipment to be protected by the voltage monitor, the said effort may be required to prevent damage caused by voltage failure.
Microcontrollers :: 27.03.2010 07:11 :: FvM :: Replies: 4 :: Views: 4700
this is my assignment that due this sunday.
anyone can help me? or give me any direction for this?
thank you :)
1. sequence detector to design (150)
Lee's student ID number of each of their four remaining divided by the sequence to recognize a pattern to design the sequence detector. (For (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.06.2010 04:18 :: gadguy :: Replies: 0 :: Views: 819
You have to re-phrase you question if you expect relevant answer ..
If you are after 3-phase sequence detector/indicator ? here is an example of one such a gadget:
3 PHASE sequence INDICATOR
Power Electronics :: 03.12.2010 22:48 :: IanP :: Replies: 3 :: Views: 819
you can use 2 dffs serialy connected, and use a counter at the same time; of cource the counter bits, u need to watch the i/p sequence firstly;
after reset and the stop signal is unenable, the initial 2DFFS are:00,then begin to capture the reading in bit from i/p sequence serialy,
u just need to dectect and judge the posedge edge 10 (that 2DFFS
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.02.2011 03:29 :: sunjianhuigou :: Replies: 25 :: Views: 5233
I need to design a pulse detector system which senses the input pulses and outputs a BCD digit,1. The input to the system is a pattern of pulse sequence with 60 msec ON followed immediately by 40 msec OFF. (Used in old telephone pulse dialing systems). The system counts such continuous pulses to detect a dialed number.
How to generate tha
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.10.2011 12:08 :: shiva20587 :: Replies: 1 :: Views: 717
Draw a synchronous sequential circuit with a single input line x and a single output line z ,so as to produce an output z=1 whenever a input sygnal completes a sequence of 4 identical bits,the out is 0 otherwise.Please write the boolean function expression
Electronic Elementary Questions :: 25.02.2012 04:49 :: ricoseeds :: Replies: 1 :: Views: 214
first mistake is that if it is a sequence detector input must b of one bit only with one bit coming in on in every clock cycle.
u have to make a state machine first. i think it will have 12 stages hence 4 flip flops must be used to control state vectors. Make a state machine and do the verilog coding for the same.
ASIC Design Methodologies and Tools (Digital) :: 04.03.2012 23:54 :: nisshith :: Replies: 5 :: Views: 616
Actually, in my code the process1 contains the sequence detector i.e. when the sequence is detected then the pulse is generated which is assigned to 'a' and in process2 when there is rising_edge(clk) and sequence is detected then c <= d. I cannot enable c with b since b is sequence detector (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.06.2013 10:41 :: indu15 :: Replies: 4 :: Views: 210
I have generated 0.5 Mhz clock from 50Mhz incoming clock by using synchronous counter clock enable and detecting the 00110001 pattern on the din input data and outputting (sync_detected) pulse once the last bit in the pattern is detected. When I implemented the code that is mentioned below I am able to generate the waveform in the image (I have zoo
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.07.2013 11:03 :: indu15 :: Replies: 7 :: Views: 557
You need a car detector and a simple up / down counter. The car detector can be made of two sensor. I will describe them below. The sequence of pulses from 2 sesors can tell whether a car is entering or leaving (maybe you have 2 gates for entry and exit in which case it would be even easier) the parking lot. A simple microcontroller can (...)
Professional Hardware and Electronics Design :: 10.03.2003 22:25 :: techie :: Replies: 7 :: Views: 2155
hi...can i use "push acc" to continuously store data into RAM?in a loop application.fist i assign the wanted RAM location into stack pointer,then store data in sequence by using push acc..but never pop them it k by doing that?
Digital Signal Processing :: 16.08.2004 04:04 :: louislu :: Replies: 6 :: Views: 1148
If there is only one signal path,I mean the only signal source I get is the +/-1 sequence.
Is there any solution for that?
Digital Signal Processing :: 25.01.2005 20:09 :: boeysue :: Replies: 3 :: Views: 972
I'm currently trying to build a preamble detector for my OFDM
transceiver which i have built in Simulink for the purpose of frame
synchronization. This is kinda a lenghty post, but i hope
those who can help me please take some time and take a look at it.
This is what i have done so far. This is autocorre
Digital Signal Processing :: 02.01.2006 21:56 :: Antonio_Magma :: Replies: 0 :: Views: 966
It is a little tricky!
The problem is that theinitial state is very important. I know only to get either positive or negative phase domains in a single simulation. If you want to have a phase resolution of
you need to take a frequency difference of 1/256. Because the phase frequency detector signal is integrated with the help of t
Analog Circuit Design :: 13.02.2006 18:04 :: rfsystem :: Replies: 2 :: Views: 936
Try the following sequence:
Analog Circuit Design :: 29.08.2006 06:28 :: IanP :: Replies: 1 :: Views: 987
you need a knite rider type sequencial flasher using a cmos chip
let me show you an archive of this type of circuit
alternatly i happen to know
that most big 20mm type flashing leds when connected by a common power supply cable will flash in sequence anyway so dispensing with
Electronic Elementary Questions :: 07.03.2007 10:54 :: VSMVDD :: Replies: 1 :: Views: 2417
The first error is that you are using the same variance for H as the noise. so that your received sequence will be a total noise and it is obvious that the BER is 1/2. you should normalize H matrix to have variance equal to one so that it won't affect the SNR. H=sqrt(1/2)*(randn.....)
Also you should change your detector accordingly but I didn't u
Digital communication :: 04.02.2009 03:30 :: farzad_m :: Replies: 2 :: Views: 2926
I want to design a BER Tester for measuting the sensitivity of the RF receiver. I divided the instrument design in a Pulse Pattern Generator and an Error detector. The Pulse Pattern Generator genarates a pseudo-random sequence that is sended to the modulation input of RF signal generator connected to the receiver under test. The receiver demod
Digital Signal Processing :: 09.06.2009 03:29 :: josipb :: Replies: 0 :: Views: 632
Use phase control at the required brightness level in normal circumstances and use a PIR motion detector to detect a movement and trigger full phase angle for full brightness for a predetermined time. Write a program with the said sequence an dprogram the PIC. But its quite easy to do this even without any microcontroller. Just use a standared fan
Microcontrollers :: 02.07.2010 10:38 :: pranam77 :: Replies: 3 :: Views: 1189
sir thank you for the reply.i really appreciate it coz i have idea now..
i have questions on the parts of the block diagram u mentioned i hope u will give me a chance to answer it sir..
what is the purpose of the carrier generator?and is it an oscillator?
bitstream,u mean the data sequence which is the switches that makes 1's and 0's state?
Digital Signal Processing :: 26.01.2011 03:49 :: andromeda30 :: Replies: 2 :: Views: 868
don't use location 0x00 in eeprom. Start @ 0x10.
During periods of low VCC, the EEPROM data can be corrupted because the
supply voltage is too low for the CPU and the EEPROM to operate properly.
These issues are the same as for board level systems using EEPROM, and the
same design solutions should be applied.
An EEPROM data corruptio
Microcontrollers :: 17.03.2011 15:26 :: ctownsend :: Replies: 2 :: Views: 1167
Hi People! :-)
I've had an idea for a monochrome light microphone, which I have rendered as a drawing, attached.
The detector consists of a monochrome source (l.e.d.), a reflective membrane (gold leaf) some distance from the source, a static reflective element, and several randomly-placed detectors, 3 of which are shown.
The idea is that as the
Hobby Circuits and Small Projects Problems :: 14.05.2011 07:11 :: poor mystic :: Replies: 2 :: Views: 930
I am trying to make a model of Least Square Estimator for a GSM network in Matlab for eliminating the ISI using MLSE detector. So far it looks that my model is right except that I don't know if my results are right. The logic of my code is the following:
I am generating a GSM Burst of 148 Bits which is divided into Data1 [a vector of 6
Digital communication :: 11.11.2011 09:01 :: g.hadzhiyanev :: Replies: 1 :: Views: 498
In sleep mode you can't do UART transmission (PIC oscillator is in shut down mode). To preserve power, PIC MCU should be in sleep mode and to use watch dog timer to generate periodically wake-up events. When PIC MCU is active, transmit your sequence via UART and go back to sleep mode.
Microcontrollers :: 29.02.2012 06:34 :: cristianp :: Replies: 5 :: Views: 543