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47 Threads found on Sequence Detector
so easy problem.... search 'sequence detector' in google.
hi iam doing vlsi diploma in scl. iam getting lot of douts on fsm specially sequence detector like 100010110 for this type and also 1100xx10 with overlapping and nonoverlapping can any one explain how to draw state diagram for this type of problems
hello any one have a good material about the ML sequence detector and symbol-by-symbol MAP detector, specially the mathmatics and the probability to be very clear and easy to understand, i.e.: step by step explanation. of cource other than Praokis's book. Regards
it involves the detection of a particular sequence and has many ways of implementation and are generally resolved using state diagram.... can you be little more specific in what you are actually looking for,.,,,,
Hi, if i remember correctly, then Prof. Srinivasan in this lecture, implements twice this sequence detector... The one of the two implementations he talks about is the one you are interested in... I believe that it should be best for you if you carefully watch this presentation and then come up with a solution. We will hel
I am new to verilog, and need to simulate a 4-bit pattern/sequence detector into modelsim and then Xylinx for the spartan 3 board. The pattern that needs to be dected is 1101. Any help would be greatly appreciated!
Can any one tell about the VHDL code for an asynchronous sequence detector(i.e. without any clock input and only data input).Output should change as soon as input changes.(For 2 bit or 3 bit input)
Here the code for a 11010 sequence ------------------------------------------------------------------------------------------ module seqdet_11010(clk,reset,in,out); input clk,reset,in; output out; reg out; parameter st0 = 3'b000, st1 = 3'b001, st2 = 3'b010, st3 = 3'b011, st4 = 3'b100
Use the state machine approach. When the first bit (MSB here) occurs, move to the next state. If the second bit matches, move to the third state and so on till the required sequence is achieved. If, the sequence breaks in any intermediate state go back to initial state. If the sequence matches, in the last state (match state) assert the (...)
For a sequence of 1010 i.e. 4 bit number , you require 4 states . After detecting all 4 bits correctly , output will be 1. You can use mealey or moore techniques. Lecture 7 - Sequentional Circuits Design - YouTube
See the ''11011'' sequence detector as an example. ---------- Post added at 10:57 ---------- Previous post was at 10:53 ---------- Example how to implement 1011 sequence detector circuit in VHDL:
I want to design a circuit that will detect a very long sequence, A2 F3 D2 F1 E4 17 AB 56 76 A2 C4 B2 FF 00 12 34 AA BB B3 A4 6E 1F 4D 1E, where all numbers are hexadecimal and hence every pair forms a 8 bit pattern ( ie 1E = 00011110 ), it also needs to set a flag bit high if one number (e.g A ) is detected, and another flag bit high if the entire
Hello, I need to synchronize an inverter to the power grid. So far I can easily track 3-phase voltages with high immunity to noise and other power failures. I am using a abc->dq conversion (3phase to 2phase, rotating frame) and with this I can easily track the phase, the sequence and peak voltage. I need to track now single phase signals. I h
You should use the following sequence: wire antenna, broad band RF amplifier, diode detector, indicating method. A simpler method which is not as sensitive is the wire, diode, oscilloscope.
hi i would like to know how can i make a phase sequence using microcontroller and how can define the phases ( r s t ) and ( r t s ) thanks
A finite state machine has a limited or finite no. of possible is mainly used as a development tool for solving problems. For example in DIgital electronics a sequence detector problem- which has to detect a particular pattern only and provide output only for the required pattern. A infinite state machine can be conceived but it is not pr
It's maybe for sequence detection. The register previous is to store input streem.
Hi The hint given by you is good. I work it and find the answer. I have another Question 1.How to detect a sequence of "1101" arriving serially from a single line? 2.How to detect if two 8-bit signals are same? Regards... Draw a state diagram for a sequence detector (overlaping or non-overlaping). The
Hi guys. I have started a short project about color lighting RGB Led is sequence to strike their light onto the object i want to detect, then LDR will get the reflected light from the object and make the voltage drop on the circuit(voltage devider).the voltage drop will get digitized by the ADC0831 to microproccessor(AT89S51) which pro
hello we can detect a modulation technique with memory by using either ML sequence detector or symbol-by-symbol MAP detector. this is explained in "Digital Communication" Proakis, but it is very hard to understand. Any one have a good resources for this material and the original papers. Regards
Hi, I need to design a 0110/1001 sequence detector which produces a 1 output if the current input and the previous three inputs correspond to either the sequence 0110 or 1001. The output 1 is to occur at the time of the forth input of the recognized sequence. Anyone can draw the state transition diagram? I'm not sure the (...)
hi friends, plz send me materials or links related to design a vhdl code for mealy and moore finite state machines for overlapping and non-overlapping binary sequence detector and its state diagrams. thanks in advance
need a circuit for a phase sequence/phase failure detector in a three phase ac power supply
To detect all cases of failure, a professional voltage monitoring relay measures three interphase voltages, optionally the star point voltage against neutral and possibly phase sequence. Depending on the equipment to be protected by the voltage monitor, the said effort may be required to prevent damage caused by voltage failure. www.tele-o
this is my assignment that due this sunday. anyone can help me? or give me any direction for this? thank you :) 1. sequence detector to design (150) Lee's student ID number of each of their four remaining divided by the sequence to recognize a pattern to design the sequence detector. (For (...)
You have to re-phrase you question if you expect relevant answer .. If you are after 3-phase sequence detector/indicator ? here is an example of one such a gadget: 3 PHASE sequence INDICATOR IanP :wink:
you can use 2 dffs serialy connected, and use a counter at the same time; of cource the counter bits, u need to watch the i/p sequence firstly; after reset and the stop signal is unenable, the initial 2DFFS are:00,then begin to capture the reading in bit from i/p sequence serialy, u just need to dectect and judge the posedge edge 10 (that 2DFFS
Hi,, I need to design a pulse detector system which senses the input pulses and outputs a BCD digit,1. The input to the system is a pattern of pulse sequence with 60 msec ON followed immediately by 40 msec OFF. (Used in old telephone pulse dialing systems). The system counts such continuous pulses to detect a dialed number. How to generate tha
Draw a synchronous sequential circuit with a single input line x and a single output line z ,so as to produce an output z=1 whenever a input sygnal completes a sequence of 4 identical bits,the out is 0 otherwise.Please write the boolean function expression
first mistake is that if it is a sequence detector input must b of one bit only with one bit coming in on in every clock cycle. u have to make a state machine first. i think it will have 12 stages hence 4 flip flops must be used to control state vectors. Make a state machine and do the verilog coding for the same.
Actually, in my code the process1 contains the sequence detector i.e. when the sequence is detected then the pulse is generated which is assigned to 'a' and in process2 when there is rising_edge(clk) and sequence is detected then c <= d. I cannot enable c with b since b is sequence detector (...)
I have generated 0.5 Mhz clock from 50Mhz incoming clock by using synchronous counter clock enable and detecting the 00110001 pattern on the din input data and outputting (sync_detected) pulse once the last bit in the pattern is detected. When I implemented the code that is mentioned below I am able to generate the waveform in the image (I have zoo
You need a car detector and a simple up / down counter. The car detector can be made of two sensor. I will describe them below. The sequence of pulses from 2 sesors can tell whether a car is entering or leaving (maybe you have 2 gates for entry and exit in which case it would be even easier) the parking lot. A simple microcontroller can (...)
hi...can i use "push acc" to continuously store data into RAM?in a loop application.fist i assign the wanted RAM location into stack pointer,then store data in sequence by using push acc..but never pop them it k by doing that?
mmmm... If there is only one signal path,I mean the only signal source I get is the +/-1 sequence. Is there any solution for that?
Season's greetings! I'm currently trying to build a preamble detector for my OFDM transceiver which i have built in Simulink for the purpose of frame synchronization. This is kinda a lenghty post, but i hope those who can help me please take some time and take a look at it. Appreciate it! This is what i have done so far. This is autocorre
It is a little tricky! The problem is that theinitial state is very important. I know only to get either positive or negative phase domains in a single simulation. If you want to have a phase resolution of 2*pi/256 you need to take a frequency difference of 1/256. Because the phase frequency detector signal is integrated with the help of t
Try the following sequence: 1kΩ 5kΩ 1kΩ Regards, IanP
yes you need a knite rider type sequencial flasher using a cmos chip let me show you an archive of this type of circuit alternatly i happen to know that most big 20mm type flashing leds when connected by a common power supply cable will flash in sequence anyway so dispensing with
The first error is that you are using the same variance for H as the noise. so that your received sequence will be a total noise and it is obvious that the BER is 1/2. you should normalize H matrix to have variance equal to one so that it won't affect the SNR. H=sqrt(1/2)*(randn.....) Also you should change your detector accordingly but I didn't u
Hi! I want to design a BER Tester for measuting the sensitivity of the RF receiver. I divided the instrument design in a Pulse Pattern Generator and an Error detector. The Pulse Pattern Generator genarates a pseudo-random sequence that is sended to the modulation input of RF signal generator connected to the receiver under test. The receiver demod
Use phase control at the required brightness level in normal circumstances and use a PIR motion detector to detect a movement and trigger full phase angle for full brightness for a predetermined time. Write a program with the said sequence an dprogram the PIC. But its quite easy to do this even without any microcontroller. Just use a standared fan
sir thank you for the reply.i really appreciate it coz i have idea now.. i have questions on the parts of the block diagram u mentioned i hope u will give me a chance to answer it sir.. what is the purpose of the carrier generator?and is it an oscillator? bitstream,u mean the data sequence which is the switches that makes 1's and 0's state? b
don't use location 0x00 in eeprom. Start @ 0x10. During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruptio
Hi People! :-) I've had an idea for a monochrome light microphone, which I have rendered as a drawing, attached. The detector consists of a monochrome source (l.e.d.), a reflective membrane (gold leaf) some distance from the source, a static reflective element, and several randomly-placed detectors, 3 of which are shown. The idea is that as the
Hello, I am trying to make a model of Least Square Estimator for a GSM network in Matlab for eliminating the ISI using MLSE detector. So far it looks that my model is right except that I don't know if my results are right. The logic of my code is the following: I am generating a GSM Burst of 148 Bits which is divided into Data1 [a vector of 6
In sleep mode you can't do UART transmission (PIC oscillator is in shut down mode). To preserve power, PIC MCU should be in sleep mode and to use watch dog timer to generate periodically wake-up events. When PIC MCU is active, transmit your sequence via UART and go back to sleep mode.