1000 Threads found on edaboard.com: Sequence Detector
so easy problem....
search 'sequence detector' in google.
ASIC Design Methodologies and Tools (Digital) :: 01-23-2004 06:25 :: bigrice :: Replies: 5 :: Views: 3449
iam doing vlsi diploma in scl. iam getting lot of douts on fsm specially sequence detector like 100010110 for this type and also 1100xx10 with overlapping and nonoverlapping can any one explain how to draw state diagram for this type of problems
Electronic Elementary Questions :: 09-18-2005 08:31 :: ravimalladi :: Replies: 4 :: Views: 5810
any one have a good material about the ML sequence detector and symbol-by-symbol MAP detector, specially the mathmatics and the probability to be very clear and easy to understand, i.e.: step by step explanation.
of cource other than Praokis's book.
Digital communication :: 06-22-2007 21:49 :: saeddawoud :: Replies: 3 :: Views: 895
it involves the detection of a particular sequence and has many ways of implementation and are generally resolved using state diagram....
can you be little more specific in what you are actually looking for,.,,,,
ASIC Design Methodologies and Tools (Digital) :: 10-01-2007 07:37 :: A.Anand Srinivasan :: Replies: 3 :: Views: 808
if i remember correctly, then Prof. Srinivasan in this lecture, implements
twice this sequence detector... The one of the two implementations he talks
about is the one you are interested in... I believe that it should be best for you
if you carefully watch this presentation and then come up with a solution.
We will hel
ASIC Design Methodologies and Tools (Digital) :: 11-13-2008 04:21 :: pmat :: Replies: 3 :: Views: 6445
I am new to verilog, and need to simulate a 4-bit pattern/sequence detector into modelsim and then Xylinx for the spartan 3 board.
The pattern that needs to be dected is 1101.
Any help would be greatly appreciated!
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-16-2010 14:19 :: VerilogNoob07 :: Replies: 0 :: Views: 1507
Can any one tell about the VHDL code for an asynchronous sequence detector(i.e. without any clock input and only data input).Output should change as soon as input changes.(For 2 bit or 3 bit input)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-17-2010 15:08 :: jaybarot :: Replies: 0 :: Views: 1101
Hi, I am developing VHDL code for 0101 sequence detector. When i simulate, i get 0 output no matter what the sequence is. I have used JK flipflop to implement the design. In my code, im calling JK ff through component port-map. JK ff works fine individually but in the top-level module, its output is always zero.
there's some warning when i (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-25-2013 16:16 :: Pradeepbp :: Replies: 2 :: Views: 545
As you are designing non-overlapping sequence detector, if circuit is in E state and it gets input 0, it will go to state A with output being 0. You will write it as 0/0.
Do you need any other help with state machines?
All the best!
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-20-2014 12:50 :: Rohitchampion :: Replies: 3 :: Views: 507
Here the code for a 11010 sequence
parameter st0 = 3'b000,
st1 = 3'b001,
st2 = 3'b010,
st3 = 3'b011,
st4 = 3'b100
ASIC Design Methodologies and Tools (Digital) :: 02-06-2007 09:17 :: rakesh_aadhimoolam :: Replies: 2 :: Views: 2388
Use the state machine approach. When the first bit (MSB here) occurs, move to the next state. If the second bit matches, move to the third state and so on till the required sequence is achieved. If, the sequence breaks in any intermediate state go back to initial state. If the sequence matches, in the last state (match state) assert the (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-19-2009 13:13 :: thiagu_comp :: Replies: 5 :: Views: 3740
For a sequence of 1010 i.e. 4 bit number , you require 4 states . After detecting all 4 bits correctly , output will be 1. You can use mealey or moore techniques.
Lecture 7 - Sequentional Circuits Design - YouTube
Analog Circuit Design :: 02-13-2012 11:57 :: jeet_asic :: Replies: 1 :: Views: 1061
See the ''11011'' sequence detector as an example.
---------- Post added at 10:57 ---------- Previous post was at 10:53 ----------
Example how to implement 1011 sequence detector circuit in VHDL:
ASIC Design Methodologies and Tools (Digital) :: 04-13-2012 03:57 :: mister_rf :: Replies: 2 :: Views: 513
I want to design a circuit that will detect a very long sequence, A2 F3 D2 F1 E4 17 AB 56 76 A2 C4 B2 FF 00 12 34 AA BB B3 A4 6E 1F 4D 1E, where all numbers are hexadecimal and hence every pair forms a 8 bit pattern ( ie 1E = 00011110 ), it also needs to set a flag bit high if one number (e.g A ) is detected, and another flag bit high if the entire
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-07-2012 19:01 :: KillaKem :: Replies: 10 :: Views: 760
Can anybody post mealy -state machine for detecting bit sequence 01010 from input of length 15 bits
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-15-2014 13:31 :: Ashishmko :: Replies: 5 :: Views: 352
A finite state machine has a limited or finite no. of possible is mainly used as a development tool for solving problems. For example in DIgital electronics a sequence detector problem- which has to detect a particular pattern only and provide output only for the required pattern. A infinite state machine can be conceived but it is not pr
Electronic Elementary Questions :: 06-18-2005 02:57 :: rajavel :: Replies: 2 :: Views: 2640
It's maybe for sequence detection.
The register previous is to store input streem.
ASIC Design Methodologies and Tools (Digital) :: 12-08-2005 03:13 :: zhangpengyu :: Replies: 5 :: Views: 1007
The hint given by you is good. I work it and find the answer.
I have another Question
1.How to detect a sequence of "1101" arriving serially from a single line?
2.How to detect if two 8-bit signals are same?
Draw a state diagram for a sequence detector (overlaping or non-overlaping). The
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-16-2006 01:45 :: xstal :: Replies: 10 :: Views: 1521
we can detect a modulation technique with memory by using either ML sequence detector or symbol-by-symbol MAP detector. this is explained in "Digital Communication" Proakis, but it is very hard to understand.
Any one have a good resources for this material and the original papers.
Digital communication :: 06-19-2007 04:51 :: saeddawoud :: Replies: 1 :: Views: 909
I think the following diagram is valid if overlapping sequences is permitted
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-20-2008 06:42 :: svicent :: Replies: 9 :: Views: 3350
plz send me materials or links related to design a vhdl code for mealy and moore finite state machines for overlapping and non-overlapping binary sequence detector and its state diagrams.
thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-21-2008 05:11 :: vijayganesh :: Replies: 2 :: Views: 1522
this is my assignment that due this sunday.
anyone can help me? or give me any direction for this?
thank you :)
1. sequence detector to design (150)
Lee's student ID number of each of their four remaining divided by the sequence to recognize a pattern to design the sequence detector. (For (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-19-2010 04:18 :: gadguy :: Replies: 0 :: Views: 829
You have to re-phrase you question if you expect relevant answer ..
If you are after 3-phase sequence detector/indicator ? here is an example of one such a gadget:
3 PHASE sequence INDICATOR
Power Electronics :: 12-03-2010 22:48 :: IanP :: Replies: 3 :: Views: 839
first mistake is that if it is a sequence detector input must b of one bit only with one bit coming in on in every clock cycle.
u have to make a state machine first. i think it will have 12 stages hence 4 flip flops must be used to control state vectors. Make a state machine and do the verilog coding for the same.
ASIC Design Methodologies and Tools (Digital) :: 03-04-2012 23:54 :: nisshith :: Replies: 5 :: Views: 656
Actually, in my code the process1 contains the sequence detector i.e. when the sequence is detected then the pulse is generated which is assigned to 'a' and in process2 when there is rising_edge(clk) and sequence is detected then c <= d. I cannot enable c with b since b is sequence detector (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-10-2013 10:41 :: indu15 :: Replies: 4 :: Views: 219
I have generated 0.5 Mhz clock from 50Mhz incoming clock by using synchronous counter clock enable and detecting the 00110001 pattern on the din input data and outputting (sync_detected) pulse once the last bit in the pattern is detected. When I implemented the code that is mentioned below I am able to generate the waveform in the image (I have zoo
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-10-2013 11:03 :: indu15 :: Replies: 7 :: Views: 589
I recently read abt registerd FSM outputs i.e Registered Moore outputs and Registered Mealy Outputs , Can anybody explain wat is FSM output registered ?
I did verilog coding for 1011 sequence detector for both moore and Mealy machine and I got the output like in the Image there is one clock dealy in the moore is it correct ??
Can anybody explai
Electronic Elementary Questions :: 12-26-2013 11:25 :: sunidrak :: Replies: 0 :: Views: 311
need a circuit for a phase sequence/phase failure detector in a three phase ac power supply
Professional Hardware and Electronics Design :: 10-31-2008 03:10 :: Hafsat :: Replies: 2 :: Views: 3465
You should use the following sequence: wire antenna, broad band RF amplifier, diode detector, indicating method.
A simpler method which is not as sensitive is the wire, diode, oscilloscope.
Hobby Circuits and Small Projects Problems :: 11-13-2004 14:15 :: flatulent :: Replies: 8 :: Views: 5254
i would like to know how can i make a phase sequence using microcontroller and how can define the phases ( r s t ) and ( r t s )
Professional Hardware and Electronics Design :: 04-01-2005 15:32 :: bluethunder7000 :: Replies: 2 :: Views: 2365
I have started a short project about color lighting RGB Led is sequence to strike their light onto the object i want to detect, then LDR will get the reflected light from the object and make the voltage drop on the circuit(voltage devider).the voltage drop will get digitized by the ADC0831 to microproccessor(AT89S51) which pro
Hobby Circuits and Small Projects Problems :: 03-19-2007 11:42 :: ghasia :: Replies: 3 :: Views: 2145
you can use 2 dffs serialy connected, and use a counter at the same time; of cource the counter bits, u need to watch the i/p sequence firstly;
after reset and the stop signal is unenable, the initial 2DFFS are:00,then begin to capture the reading in bit from i/p sequence serialy,
u just need to dectect and judge the posedge edge 10 (that 2DFFS
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-11-2011 03:29 :: sunjianhuigou :: Replies: 25 :: Views: 5516
I need to design a pulse detector system which senses the input pulses and outputs a BCD digit,1. The input to the system is a pattern of pulse sequence with 60 msec ON followed immediately by 40 msec OFF. (Used in old telephone pulse dialing systems). The system counts such continuous pulses to detect a dialed number.
How to generate tha
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-27-2011 12:08 :: shiva20587 :: Replies: 1 :: Views: 738
I am looking for metal detector's shematic based on microcontroller. I'm especially interrest by the tesoro's metal detector shematics. If someone could help me.
Professional Hardware and Electronics Design :: 12-13-2001 01:51 :: elektroda :: Replies: 4 :: Views: 2442
to anyone with an interest
here are the coils dimetion and a picture
here is the coil calc i used
the dimentions are this
center coil 44T .51 7 cm sides equal sided triangle
second coil out is
round 10 cm dia 33 T .71
is triangle equal sides so 25 T .51 mm
fourth is round
Professional Hardware and Electronics Design :: 12-13-2001 12:12 :: THE BORG :: Replies: 10 :: Views: 8996
I'm looking for any schematic, pcb etc about metal detector. Only thing I need is a WORKING CIRCUIT.
I anybody know where to find it, please tell to me.
I´m looking metal detector schematics, pcb's theory, or any related thing, specially any circuit easy to make it.
Professional Hardware and Electronics Design :: 05-05-2002 05:41 :: deadlock :: Replies: 3 :: Views: 2343
For example, RFMD's RF5117 and Intersil's ISL3984
Does Somebody know how to design the peak detector(or power detector) for WLAN HBT power amplifier?
Other Design :: 05-13-2002 11:16 :: cwcwecan :: Replies: 1 :: Views: 2346
For example, RFMD's RF5117 and Intersil's ISL3984
Does Somebody know how to design the peak detector(or power detector) for WLAN HBT power amplifier?
Other Design :: 05-13-2002 11:17 :: cwcwecan :: Replies: 1 :: Views: 1448
Can anyone help me to find resources about RF/ID detector design?
Other Design :: 07-17-2002 10:11 :: Free_Will :: Replies: 18 :: Views: 25393
Are there anybody can share the Pyro-IR detector LHI958 (by HEIMANN) Datasheet or Appliction Note with me?
RF, Microwave, Antennas and Optics :: 01-10-2003 20:53 :: jinboqiu :: Replies: 3 :: Views: 2726
Does anyone know a manufacturer of this kind of systems? (I'm looking for a simple one, just needs to send an impulse when he detects a car, not a complex one, like 3M, with time-stamping etc.....)
Thanks in advance
P.S: it should be able to detect both stoped and moving vehicles.
Professional Hardware and Electronics Design :: 01-11-2003 16:10 :: mrseven2 :: Replies: 2 :: Views: 1158
I am looking for the schematics of LPG gas detector using Figaro's LPG gas sensor TGS 2610, I have the sensor application note but the sample schematics doesnot work properly, please any one out there help me out
Professional Hardware and Electronics Design :: 01-15-2003 09:33 :: hynix :: Replies: 5 :: Views: 3102
AVR based metal dedector.
Hobby Circuits and Small Projects Problems :: 01-21-2003 19:05 :: ebenni :: Replies: 2 :: Views: 7214
I´m nedding schematics of pico ammeter to use in a gas cromatography.
Professional Hardware and Electronics Design :: 02-17-2003 15:15 :: aco.junior :: Replies: 2 :: Views: 1316
i'm working on a MPC860 boot code software.
I'd like to know the correct initialisation sequence. The one I planned is
=> Set IMMR and MSR
=> Invalidate MMU and cache
=> Set SIU clocks et timers
=> Set memory mapping (load UPM and init Chip Select Bank)
=> Configure MMU
=> activate cache and MMU
=> sonfigure cpm et UART on SM
Microcontrollers :: 03-05-2003 04:33 :: ze_dib :: Replies: 4 :: Views: 1469
You need a car detector and a simple up / down counter. The car detector can be made of two sensor. I will describe them below. The sequence of pulses from 2 sesors can tell whether a car is entering or leaving (maybe you have 2 gates for entry and exit in which case it would be even easier) the parking lot. A simple microcontroller can (...)
Professional Hardware and Electronics Design :: 03-10-2003 22:25 :: techie :: Replies: 7 :: Views: 2177
I want to design a simple heart beat detector which will be 3V power
supply. Please give me some tips.Thanks anyway!
Hobby Circuits and Small Projects Problems :: 04-11-2003 12:50 :: dudleyzty :: Replies: 5 :: Views: 2626
I'm looking for a phase detector that works from DC to 500MHz. Already search the forum and did'n find nothing. Also search Google but no conclusive material found. No experience with PLL or DPLL. Can any one help me.
Professional Hardware and Electronics Design :: 06-10-2003 18:12 :: Elavionic :: Replies: 4 :: Views: 1328
sequence ports EDA tools to Linux
By Richard Goering, EE Times
Jun 17, 2003 (10:55 AM)
SANTA CRUZ, Calif. ? sequence Design this week (June 17) is announcing that it is porting all of its EDA tools to Linux. The company also claims to be experiencing significant run-time speed ups with th
Linux Software :: 06-17-2003 23:41 :: seeya :: Replies: 3 :: Views: 1463
June 17, 2003 (1:55 p.m. EST)
SANTA CRUZ, Calif. ? sequence Design this week (June 17) is announcing that it is porting all of its EDA tools to Linux. The company also claims to be experiencing significant run-time speed ups with the open-source operating system.
According to sequence, internal tests reveal that the PowerThe
PC Programming and Interfacing :: 06-22-2003 11:55 :: seeya :: Replies: 0 :: Views: 753