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11 Threads found on edaboard.com: Serdes Cdr
Dear Friends, I am new to hardware design. I am designing a burst mode cdr. I have 8 phase input clock. I am sampling the input data with this clock. I am preparing an algorithm for detecting the phase which sample the data at mid point. Typically my clock should lock to the incoming data in no time. There are scripts available which describes
Dear Friends, I am newbie to hardware design. I have a task to design a burst mode cdr. Typically it should have very fast frequency acquisition time. In my system, I have a 8 phase clock input. I am sampling my data with this clock. Now I am searching for an algorithm to detect the phase at the mid point of the data (thereby locks in no time). I
My query is where should be placement of ac coupling capacitor in sgmii interface on PCB??? What should be the value of ac coupling capacitor???
I recently know after RX equalizor, there is residual deterministic jitter of about 30 ps. Will this 30ps residual ISI be further rejected by cdr jitter transfer function? Since this 30ps is large, it will eat up a lot of jitter budget to pass the cdr jitter tolerance test. Many thank.
Hi all, I've been working on cdr basics study. cdr is supposed to b useful because clock can b embeded. In fact however, many serdes rx uses external ref clock generated in tx. I think that ext clk incorporated with phase interpolation may help to deserialize less jittery manner relatively. But downside would b apparently one diff (...)
Hi, I am currently designing a serdes chip including the multiplexer, PLL; demultiplexer, cdr. But I am not sure about how to determine the component parameters according to the BER requirement. Here is my idea: First, the serdes needs satisfy the BER requirement, for example, smaller than 10^(-12). Then, through the erfc function, we (...)
Hi All I am doing my master thesis research in high speed digital I/Os (serdes). Any high speed digital I/Os is consisting from four main blocks (RX,TX,cdr and PLL). I am trying to find a research topic in this area. I would appreciate your help and suggestions. Thanks Haytham
Dear All, I need any references on high speed serdes design. Thanks, BR
so an UART falls under serdes catergory?
Dear all, There seems almost every high speed serdes got 8B/10B encoder in high speed link or optical link, so the parallel data got the 10 bit buswidth. I just wander why there is no particular paper mentioning about the 10-phase sub-rate phase detector instead of 2^n sub-rate phase detector? It really put me in puzzle. Why not adopt th
I need something about clock & data recovery for serdes, like USB2.0, SATA, and Giga Fiber.