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## Sigma Delta Adc Simulation |

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64 Threads found on edaboard.com: **Sigma Delta Adc Simulation**

Hello,
I've read around extensively about FFT setup for a **sigma** **delta** **adc** and I'm not sure if I'm not setting it up properly .
my current setup for a first order **sigma** **delta** **adc**
sampling frequency : 38.4 kHz (for the **adc** and FFT setup)
FFT bins : 65536
input (...)

Analog Circuit Design :: 06-28-2016 07:48 :: irascible :: Replies: **0** :: Views: **502**

The op amp with the ideal vcvs in the CMFB circuit still affects the **sigma** **delta** **adc** performance greatly!!
Could you show how you connected the vcvs-CMFB to your opAmp?

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-07-2015 12:24 :: erikl :: Replies: **18** :: Views: **1108**

Okay, here's the deal:
1) Learn about coherent sampling. You should use sampling frequencies and input frequencies that are coherent. Meaning that the input frequency should always be exactly on a bin that is computed by FFT to get the most accurate performance measurement. There's more to it but this is an intuitive explanation. If you get this p

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-10-2015 21:09 :: kemiyun :: Replies: **5** :: Views: **664**

Hello
I have some queries about **delta**-**sigma** DAC.
1) basically, it is same with **delta**-**sigma** **adc**, but it consists of digital blocks, such as accumulators. However, how to synchronize the clock with PCM signals from a DSP? Does it need serial communication circuits?
2) I tried to find Simulink (...)

Analog Circuit Design :: 04-04-2015 05:38 :: CHL :: Replies: **0** :: Views: **871**

Hi All,
This is my first **adc** and verifying it is proving to be more difficult then actually designing the subblock.
I have been able to do a transient **simulation** in cadence (spectre) and have successfully imported the data into matlab.
This is where I'm encountering most of my headache.
1) I'm new at matlab
2)All of the fft examples I've

Analog Circuit Design :: 04-03-2015 18:41 :: Souljah44 :: Replies: **0** :: Views: **879**

Hi, I'm working on a project about audio **sigma** . There are some spurious components in audio band(20Hz~20KHz) when the **adc** is stimulated with no signal or small amplitude signal such as 10mVpeak-to-peak 1kHz audio signal while no other analog or digital modules can generates that low frequency (such as 2.3kHz, 10kHz) components on the same chip.

Analog Circuit Design :: 01-30-2015 15:29 :: threekingtiger :: Replies: **3** :: Views: **434**

have anyone done any **simulation** of the DSM . here is my design.. but my output seems to be inverted.. anyone know if im doing anything wrong or can explain to me why my waveform is inverted.
89268
my output bit steam when input at Vmax there should be more 1s at the top however my waveform stated otherwise.
[ATTACH=CO

Analog Circuit Design :: 04-13-2013 05:45 :: dawson :: Replies: **4** :: Views: **805**

I am building **sigma** **delta** **adc**, i want to include the effect of thermal noise in the sustem.. Is there any way to include noise source to represent resistors' thermal noise ?? a random source generator or something ?

Analog Circuit Design :: 03-25-2013 14:59 :: Shady Ahmed :: Replies: **1** :: Views: **665**

first of all u need u understand the modulator portion. it consists of
1. Loop filter which is basically an integrator in discrete time ie z tranform so u need to know about z transfroms and then how to create a filter in z-domain
2. Quantizer which is basically is 1 bit comparator which can be implemented using sign block in Matlab Simulink
3. DA

Analog Circuit Design :: 10-17-2012 07:44 :: micro designer :: Replies: **35** :: Views: **5638**

I want to model an **sigma** **delta** **adc** with VHDL. in this case we ned to have an LowPass RC. and for **simulation** also we need its model.
78976

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-21-2012 10:55 :: Zerox100 :: Replies: **13** :: Views: **2058**

I'm recently working on **delta** **sigma** a new on this,I started from the behavioral **simulation**.
The topological structure is as follows:
70480
the coefficients are 0.2 0.4 0.1 0.1.
However,problem is with ideal component,the PSD is stable.After replacing the ideal component with unideal component,the PSD becomes unstabl

Analog Circuit Design :: 03-08-2012 01:24 :: naxii :: Replies: **0** :: Views: **591**

hi...
im trying to simulate **sigma** **delta** **adc** in cadence at behaviral lvel....
wen i used ideal integrator block in ahdl lib in cadence results came gud
bt wen i try puting opamp based Integrator (used ahdl lib opamp wid Appropriate R & c values) i cudnt get the results at all...some unexpected waveforms
i hope im doing some mistake in (...)

Analog Circuit Design :: 11-15-2011 12:18 :: satyanitt :: Replies: **1** :: Views: **907**

My question is that :
Now that the **adc** is translate a analog input to a digital one,
so the output of the **sigma**-**delta** **adc** should be a lot of digital signals,
Such as 1111101111. not a sine wave.Correct.
By the way, Does the software limit this **simulation** ?No.

Analog Circuit Design :: 11-02-2011 01:53 :: pancho_hideboo :: Replies: **2** :: Views: **932**

when i simulate a **sigma** **delta** **adc** in cadence a time it is perfect another time it got bad and it is the same circuit does any one say to me why?????????????????????????????????????????????????????

ASIC Design Methodologies and Tools (Digital) :: 06-23-2011 01:29 :: hoka_89 :: Replies: **0** :: Views: **552**

Digital Signal Processing :: 12-26-2010 13:40 :: pankaj jha :: Replies: **0** :: Views: **1688**

I am trying to simulate the ∑Δ **adc** in simulink... on running it thr following error messages are prompted... can anybody help me how to do away with the errors..
1) Only 'double' signals are accepted by block type Integrator. The signals at the ports of '**sigma**_**delta**_**adc**/Integrator' are of data type 'boolean'.
2) (...)

Digital communication :: 12-26-2010 07:11 :: pankaj jha :: Replies: **0** :: Views: **867**

HI GUYS
i am working in mentor garphics DAIC tool for modelling the switched capacitor resonator LDI Loop for **sigma** **delta** **adc**. actually i want to estimate the opamp specifications for my design using a macro block present in the mentor graphics....actually my problem is while simulating i am getting some error. due to which tool do not (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-26-2010 08:43 :: ASHUTOSH RANE :: Replies: **1** :: Views: **1207**

Hi everyone
I met a question in the designing the mash **sigma****delta** **adc**.
In my design, it is a 2-1-1 mash, every stage has 1-bit flash. I use the scaling factor as in book(cascade **sigma** **delta** **adc** for sensor and telecom).
I have finished the schematic, and is doing the spectre (...)

Analog Circuit Design :: 07-20-2010 13:34 :: gdhp :: Replies: **4** :: Views: **1591**

hi all,
i have design a **sigma** **delta** **adc**.
the fft results of both "matlab" and "veriloga" and "veriloga_sw & mos_amp" is fine.
if the veriloga sw be changed to cmos-sw,
the dc noise peak arise, & independent of fft point number.
the 1/R_sw/C_s ~= 6*(2*pi*f_sample).
my english is very poor,
thanks for your help!!
Add

Analog Circuit Design :: 04-01-2010 03:10 :: macron :: Replies: **0** :: Views: **824**

Hi, all:
I added dynamic dither into my **adc** to eliminate spurs due to offset. It is weird that the SQNR of **adc** with dynamic dither is higher than that without dither. Is there any one can give me an explain or tell me what could be wrong? I do the **simulation** in Matlab. Both are under the same configuration.
Thanks

Analog Circuit Design :: 01-11-2010 09:34 :: jennysheng :: Replies: **0** :: Views: **960**

Hi,
Can any one help in doing in noise **simulation** of SC integrator - part of a incremental **sigma**-**delta** **adc**?
Any good reference or **simulation** type details will help a lot.
Thanks
Sanku

Analog Circuit Design :: 06-26-2009 08:18 :: sankudey :: Replies: **1** :: Views: **1329**

Hi,
I wonder if somebody could please be of help?
I have implemented a latched comparator, which is part of a **delta** **sigma** **adc**. I am currently testing it to validate it's performance. I am running the Cadence ADE environment. So far, I have only done transient analyses to check H->L and L->H transitions.
I have two questions:
1) (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-18-2009 15:41 :: sammyt09 :: Replies: **3** :: Views: **2596**

hi,
I am new to the sigam **delta**.
can you please help me wrt ABCD matrix.
How to get ABCD matrix for 2nd order **sigma** **delta** modulator.
I got the **delta** **sigma** tool box from
For a second order modulator the ABCD state space model is given as
A=;
B=;
C=;
D=

Analog Circuit Design :: 05-20-2009 05:47 :: santi001 :: Replies: **2** :: Views: **1289**

Hi,
I designed a SC **sigma** **delta** **adc** with its different compenents: TG, feedback TG,OTA, Latch Comparator .
But when I analyzed its spectrum to have 14 bits , I obtained these

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-23-2008 08:40 :: joujou :: Replies: **3** :: Views: **2281**

Hello,
I want simulate my first first order **delta** **sigma** **adc**, attached schematic. I can simulate it and I see behind the LP again my input signal.
My problem is I cant see the noise shift to higher frequency. I simulate transient and adjust transient noise (noisefmin noisefmax and noisescale) measure it at the input (DFT) and compare (...)

Analog Circuit Design :: 09-02-2008 09:54 :: olzanin :: Replies: **2** :: Views: **3112**

I am designing a rather high resolution (>15bit) **delta** **sigma** **adc**. I have a design that's working in MATLAB and I am trying to build the same thing in cadence using Verilog A modeling. Every component I have now is ideal and in verilog A code, so that means no transistors, no resistors and no capacitors. I am using the function laplace_nd to (...)

Analog Circuit Design :: 08-22-2008 01:25 :: jowong1 :: Replies: **4** :: Views: **1944**

Hi,
I am designing a decimation filter for **sigma** **delta** **adc**.
I have read some materials, and my design consists of 3-stages.
1 CIC filter, 1 CIC compensator and 1 halfband filter, with
oversampling rate 128, input bitstream (1 bit). The output will be 16bit.
I designed the filter in MATLAB, and with floating point precision, (...)

Analog Circuit Design :: 07-04-2008 18:08 :: gcj :: Replies: **1** :: Views: **3613**

i want to simulate the op's gain ,GBW,etc, but the op's cmfb is sc cmfb, and the op's loads is the next sc integrator. how to caculate the op's loads and how to substitude the sc cmfb circuits in **simulation** circuits?
thanks!

Analog Circuit Design :: 06-05-2008 03:11 :: xyabc :: Replies: **2** :: Views: **815**

hi all. I meet a problem in my project and want to get your help. thks! the THD of the **adc** is about 100dB at the system level. but the **simulation** results show that the THD of the **adc** is about 72dB with the actual circuit. what's the main cause?

Analog Circuit Design :: 05-05-2008 15:12 :: chrisccq :: Replies: **2** :: Views: **900**

The SNR that I had received while calculating in Matlab for a specific NTF is around 80 dB. I realised the same using ideal op amps and the SNR was the same. But the SNR after using nonideal op amps went down to 40 dB. What can be the reasons for the degradation?
Added after 17 minutes:
and also suggest wh

Analog Circuit Design :: 04-17-2008 03:42 :: shringos :: Replies: **3** :: Views: **1101**

Hi all,
Can anyone provide me the methodology for **delta** **sigma** **adc**/DAC SNR measurement in **simulation**?
I used SD Toolbox from Mathwork, but i didn't get the true answers. i'd like to measure SNR for some DC input signals. would you please help me to know the principle of SNR measurement from the time-domain signal to (...)

Analog Circuit Design :: 04-14-2008 19:34 :: farrokhiyan :: Replies: **3** :: Views: **1211**

I am running into a problem when I was trying to simulate my DS**adc** in spectre. The entire system is using ideal components (no transistors, but there are VCVS, R, C) and Verilog models. When I was doing transient sim using "Liberal" setting, for about 60us, it was running fine and giving correct output (noise shaping and all that) but then at about

Analog Circuit Design :: 03-29-2008 19:37 :: jowong1 :: Replies: **0** :: Views: **866**

I am running into a problem when I was trying to simulate my DS**adc** in spectre. The entire system is using ideal components (no transistors, but there are VCVS, R, C) and Verilog models. When I was doing transient sim using "Liberal" setting, for about 60us, it was running fine and giving correct output (noise shaping and all that) but then at about

Software Problems, Hints and Reviews :: 03-29-2008 19:36 :: jowong1 :: Replies: **1** :: Views: **2919**

In the circuit **simulation**, input a sin wave and calculate the snr of the output.But this snr must be ideal, that is SQNR. How to get the real SNR of a **adc**?
Does it need to add a noise in the input or on the supply?and how ?
For a **sigma**-**delta** **adc**, how to get the DR? Except the snr and dr, what else (...)

Analog Circuit Design :: 01-12-2008 02:05 :: xdy83 :: Replies: **3** :: Views: **1187**

Dear all :
I run SDM now, But I use hspice to simulate , it need more time, Does anyone have any good method for SDM simualtion , Thanks

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-29-2007 13:46 :: mitgrace :: Replies: **3** :: Views: **1373**

Hi
Now matlab has a central role in Analog and digital systems **simulation**.
Why not try with matlab:
"**sigma**-**delta** **adc**, From Behavioral Model to Verilog and VHDL "
1. -> t
This includes the following:
bin2sbin.m, elaborated_design.mdl, elaborated_desig

Software Recommendations :: 10-21-2007 21:58 :: jimjim2k :: Replies: **2** :: Views: **255**

Am a bit new to using matlab for **simulation** of **sigma** **delta** **adc**s...have a few doubts:
1)While calculating output power spectrum we take the FFT and plot only single sided spectrum...this is because the spectrum is symmetrical...but isnt the spectrum from -fs/2 to +fs/2??I have seen tht in most codes the 0 to fs interval is (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-13-2007 02:54 :: vrs007 :: Replies: **0** :: Views: **1713**

OK.finally,i give up the demo.i download the toolbox from mathworks.there are two toolboxs,delsig and SDtoolbox.it's easy to use the SDtoolbox by adding the path.but i have trouble in delsig.i type the 'delsig' at the Matlab prompt but it dosen't work.
Added after 1 hours 9 minutes:
maybe t

Analog Circuit Design :: 10-16-2007 08:52 :: shiveshdubey :: Replies: **18** :: Views: **3515**

Understanding **delta**-**sigma** Data Converters
good for newbie
**delta**-**sigma** Data Converters,Theory,Design and **simulation**
you can study more circuit and theory in it

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-01-2007 13:23 :: castrader :: Replies: **4** :: Views: **1690**

Hi,
I'm designing a MASH **sigma** **delta** **adc**. As you know, if transistor-level clock generator is included in the **simulation** netlist, the running time will be long. So I used a behavioral clock generator before, and the **simulation** results show the performance is what I expected.
Unfortunately, when I replace (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-18-2007 07:59 :: joskin :: Replies: **0** :: Views: **1178**

Hi,
I'm designing a MASH **sigma** **delta** **adc**. As you know, if transistor-level clock generator is included in the **simulation** netlist, the running time will be long. So I used a behavioral clock generator before, and the **simulation** results show the performance is what I expected.
Unfortunately, when I replace (...)

Analog Circuit Design :: 05-18-2007 02:41 :: joskin :: Replies: **0** :: Views: **710**

I will design the 18bit **sigma**-**delta** **adc**,How do it!
please upload simulatiom program of MATLAB!!!!!!!!! thank you very much!
what target will be achieved by this **simulation** of MATLAB ????
classical documents please give me!!!

Analog Circuit Design :: 04-29-2007 01:47 :: zouyufeng :: Replies: **1** :: Views: **937**

I will design the 18bit **sigma**-**delta** **adc**,How do it!
please upload simulatiom program of MATLAB!!!!!!!!! thank you very much!
what target will be achieved by this **simulation** of MATLAB ????

Analog Circuit Design :: 04-25-2007 00:21 :: zouyufeng :: Replies: **1** :: Views: **808**

Hi, all
I have designed a 3 order **sigma** **delta** SDM. after the chip come back.
the second order harmolic distortion is -70db, and the noise floor is about -100db,
How can I to reduce the second order harmolic distortion.
Best regards
Crossbow

Analog Circuit Design :: 03-29-2007 04:16 :: crossbow_123 :: Replies: **2** :: Views: **770**

Yes, you should directly measure SNR from FFT instead of transient **simulation** to get INL and DNL. For **sigma**-**delta** >=16-bits, you can hardly get accurate results
from INL/DNL

Analog Circuit Design :: 02-24-2007 18:12 :: hung_wai_ming@hotmail.com :: Replies: **5** :: Views: **1380**

Hi All,
I am building a **delta**-**sigma** **adc** in Cadence, and need to measure its SNDR. For that, I want to import the waveform and then manipulate it in Matlab. According to the course's tutorial, there is a "printvs" function in the calculator. I just can't find it at all. I am using SpectreS for **simulation**.
Could someone (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-11-2006 16:24 :: Crusader370 :: Replies: **1** :: Views: **1806**

Hi,all
Anybody has the continuous time **sigma** **delta** **adc**'s simulink model??
Thans a lot!

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-18-2006 05:16 :: caosl :: Replies: **2** :: Views: **1267**

yellow book by schreier "**delta** **sigma** data converters theory, design and **simulation**". and in fact google it can help you much.

Digital Signal Processing :: 06-23-2006 01:33 :: wwfhm2002 :: Replies: **2** :: Views: **1272**

Hello,
I am working on a semester project of 1bit 1st order **sigma** **delta** **adc**. Can anyone explain me the steps to simulate it in Matlab and also the SNR calculation. Any example code would be very helpful...
Thanks

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-26-2006 21:34 :: socware :: Replies: **3** :: Views: **1845**

hi,all
I am doing a **sigma** **delta** **adc**.Now I have made a simulink model,but I have no idea on how to simulate it properly.
Thanks for help.
Regards
glacier

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-28-2006 01:12 :: glacieryy :: Replies: **7** :: Views: **2018**

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