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## Simulation Delta Sigma |

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166 Threads found on edaboard.com: **Simulation Delta Sigma**

Hello,
I've read around extensively about FFT setup for a **sigma** **delta** ADC and I'm not sure if I'm not setting it up properly .
my current setup for a first order **sigma** **delta** ADC
sampling frequency : 38.4 kHz (for the ADC and FFT setup)
FFT bins : 65536
input signal : (31*38400)/65536 = 18.1640625 Hz
I'm using (...)

Analog Circuit Design :: 06-28-2016 07:48 :: irascible :: Replies: **0** :: Views: **667**

This might be a typical university exercise.
I remember in our 1st year our professor had given us the assignment to develop a VHDL model of a **sigma**-**delta** converter. It was required just to work in **simulation**, no synthesis. I don't remember anything further after so many years. ;-)

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-19-2015 22:58 :: dpaul :: Replies: **3** :: Views: **1060**

Hi everybody,
I have a couple of questions about power spectral density **simulation** of the **sigma**-**delta** modulators. I want to see the harmonics inside the output bit-stream of the modulated signal.
The details of what I did are provided at this link:
I will be so thankful if you answer these questions:
1- How lo

Analog Circuit Design :: 12-07-2015 02:06 :: mmnavidi :: Replies: **1** :: Views: **424**

Hi All,
I'm simulating a transistor level, continuous first order **delta** **sigma** modulator and need some clarification on the my gm-c filter.
**simulation** is all in Cadence.
The input frequency of the DSM is 10hkz so what should the 3-db cutoff frequency (not my unity gain frequency) of my gm-c be?
I was thinking that my f_3db should at (...)

Analog Circuit Design :: 12-07-2015 04:58 :: Souljah44 :: Replies: **0** :: Views: **373**

You should be able to see in a **simulation** which real OP parameters have the greatest impact. I guess, low gain will be a problem.

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-22-2015 12:41 :: FvM :: Replies: **18** :: Views: **1158**

I am designing a 3rd order **sigma** **delta** ADC, with 1.5 bit comparator, i modeled the system using ideal components and the system worked as expected.
Now, i inserted the comparator i designed (CMOS Comparator), while simulating , i got confusing results
When i simulate and calculate the FFT (or DFT) using 4096 points, the output is as follows yie

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-10-2015 13:18 :: Shady Ahmed :: Replies: **5** :: Views: **735**

Hello
I have some queries about **delta**-**sigma** DAC.
1) basically, it is same with **delta**-**sigma** ADC, but it consists of digital blocks, such as accumulators. However, how to synchronize the clock with PCM signals from a DSP? Does it need serial communication circuits?
2) I tried to find Simulink (...)

Analog Circuit Design :: 04-04-2015 05:38 :: CHL :: Replies: **0** :: Views: **965**

Hi All,
This is my first ADC and verifying it is proving to be more difficult then actually designing the subblock.
I have been able to do a transient **simulation** in cadence (spectre) and have successfully imported the data into matlab.
This is where I'm encountering most of my headache.
1) I'm new at matlab
2)All of the fft examples I've

Analog Circuit Design :: 04-03-2015 18:41 :: Souljah44 :: Replies: **0** :: Views: **981**

Limit cycles and and some spurios compnents are generated by design and can be reproduced in a **simulation** with ideal circuit elements, other interferences are caused by non-ideal hardware properties. You should be able to sort out which kind of interferences shows in your case.

Analog Circuit Design :: 01-31-2015 12:31 :: FvM :: Replies: **3** :: Views: **474**

3rd order **sigma**-**delta** has various configurations. please study following texts:
"A Third-Order **sigma**-**delta** Modulator with Extended Dynamic Range" by:Williams
"Continuous-Time **sigma**-**delta** AD Conversion" By:Ortmanns
"Understanding **delta**-**sigma** Data Converters" (...)

Digital Signal Processing :: 08-18-2014 07:48 :: kappa_am :: Replies: **2** :: Views: **1004**

Regarding bit true **simulation** using matlab: is there an "easy" way to model fixed point multiplication that will work transparantly with existing toolkits? Case in point: I recently used the **delta** **sigma** Toolbox (delsig), and it would be nice if you could run the **simulation** with fixed point multiply accumulate. And same (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-23-2014 12:14 :: mrflibble :: Replies: **4** :: Views: **2049**

I would suggest you extend the transient **simulation** time so you have at least 2^16 samples of BS. Export the BS and do an FFT. For example with a 2 MHz clock for 2^16 you need a **simulation** time of aprox. 32.8 ms.
BR Jerry

Analog Circuit Design :: 05-09-2014 10:20 :: helpmejerry :: Replies: **1** :: Views: **475**

There are different sources of non-linearity in a SD-modulator. The assumption, that you mainly see odd harmonics is of course based on prerequisites, generally speaking no even terms present in the polynomials describing the transfer characteristics of individual building blocks.
There's a paragraph about distortion in the **simulation** chapter o

Analog Circuit Design :: 03-06-2014 18:54 :: FvM :: Replies: **2** :: Views: **793**

i've done some **simulation**s on **sigma** **delta** ADC. but i think my output is not so correct..anyone can help me out attacedh are my design and waveforms
mainly the decimation design im not sure of.
matlab simulink
1st order **sigma** **delta** adc
input: 2V Fb=1kHz , OSR=16 times88922
the 1 bit DAC simply is (...)

Digital Signal Processing :: 04-06-2013 18:54 :: dawson :: Replies: **6** :: Views: **1140**

have anyone done any **simulation** of the DSM . here is my design.. but my output seems to be inverted.. anyone know if im doing anything wrong or can explain to me why my waveform is inverted.
89268
my output bit steam when input at Vmax there should be more 1s at the top however my waveform stated otherwise.
[ATTACH=CO

Analog Circuit Design :: 04-13-2013 05:45 :: dawson :: Replies: **4** :: Views: **882**

Hi,
Because i have obtained with Malab simulink **simulation** the same signal ouput as in the input.
I need to design decimation filter in VHDl code for this simulink **sigma**-**delta** anlog to digital converter.
osr=64 = 16 * 4
Fs=10.24MHz
fb=80Khz
nb=8bits
here i design the decimation with two sinus cardinal "comb?filter" (decimation of (...)

Digital Signal Processing :: 03-30-2013 17:21 :: fasto2008 :: Replies: **0** :: Views: **801**

In the standard noise **simulation**, ideal resistor noise (calculated from its resistance value) is included (there may be an option to select/deselect it). Same is true for all the devices, if their models include the corresponding parameters.

Analog Circuit Design :: 03-25-2013 20:21 :: erikl :: Replies: **1** :: Views: **712**

hi anyone around can help me with my digital portion.. i've been stuck for 2 week unable to get my decimation filter up .. need advice and guidance and examples if any of u have.. really appreciate8527185272
**simulation** stop time = 0.03
input sine signal = Amp= 12, Freq=2*pi*60
C

Analog Circuit Design :: 01-11-2013 11:30 :: pYrana13 :: Replies: **35** :: Views: **6080**

I am looking for "rc low pass filter" model for **simulation** in vhdl. Is there any link or guide?

PLD, SPLD, GAL, CPLD, FPGA Design :: 08-21-2012 10:24 :: Zerox100 :: Replies: **13** :: Views: **2224**

hi all
I design **sigma** **delta** modelator by matlab and hspice
but output of noise shaping not correct in hspice!!!
there are images of noise shaping outputs.
can help me?
[img

Professional Hardware and Electronics Design :: 08-13-2012 10:44 :: hasanalmasi :: Replies: **0** :: Views: **610**

Hello
I trying to learn **sigma** **delta** modulator design.
I have very little experience on matlab and simulink
I have downloaded and installed Richard Schreier s **sigma** **delta** toolbox and was able to work out few examples from his book
After running the toolbox (order = 1, OSR = 64, 2 level quantiser, CIFB architecture) i (...)

Analog Circuit Design :: 06-07-2012 16:04 :: edinburghtech :: Replies: **3** :: Views: **972**

The methods is discussed in SD literature, e.g chapter 4 of **delta**-**sigma** Data Converters - Theory, Design and **simulation** by Schreier et al.
You can refer to impulse-invariant transformation from s to z domain, in this case choose the CT parameters to get the same impulse response as the calculated DT modulator at sampling times.

Analog Circuit Design :: 06-03-2012 12:13 :: FvM :: Replies: **2** :: Views: **793**

We r working on second order **sigma** **delta** modulators. We have created a model using simulink. But we r getting error with sampling time parameter in each blocks. we are not understanding where to change the sampling frequency in the model. also can anyone suggest how to plot logarithmic PSD in will be really greatful if you help us.
Th

Digital communication :: 03-29-2012 09:19 :: sumeet nesarikar :: Replies: **0** :: Views: **1663**

I'm recently working on **delta** **sigma** a new on this,I started from the behavioral **simulation**.
The topological structure is as follows:
70480
the coefficients are 0.2 0.4 0.1 0.1.
However,problem is with ideal component,the PSD is stable.After replacing the ideal component with unideal component,the PSD becomes unstabl

Analog Circuit Design :: 03-08-2012 01:24 :: naxii :: Replies: **0** :: Views: **634**

Hi, all..i'm new in **sigma** **delta** Modulator.
I try to built SDM for my final project.
I simulate for 1st order SDM which can see in attachment.
I simulate it using Circuit Maker.
I need suggestion about it.
And i have question about how to design high order (> 1) SDM.
I read some paper, and for high order SDM you can replace integrator (which

Professional Hardware and Electronics Design :: 02-08-2012 15:19 :: surz90 :: Replies: **1** :: Views: **1441**

hi...
im trying to simulate **sigma** **delta** adc in cadence at behaviral lvel....
wen i used ideal integrator block in ahdl lib in cadence results came gud
bt wen i try puting opamp based Integrator (used ahdl lib opamp wid Appropriate R & c values) i cudnt get the results at all...some unexpected waveforms
i hope im doing some mistake in using ahdl

Analog Circuit Design :: 11-15-2011 12:18 :: satyanitt :: Replies: **1** :: Views: **940**

My question is that :
Now that the ADC is translate a analog input to a digital one,
so the output of the **sigma**-**delta** ADC should be a lot of digital signals,
Such as 1111101111. not a sine wave.Correct.
By the way, Does the software limit this **simulation** ?No.

Analog Circuit Design :: 11-02-2011 01:53 :: pancho_hideboo :: Replies: **2** :: Views: **956**

Hello to everyone,
It is the first time that I am designing a **sigma** **delta** modulator. I have started with the example (verilogA) of the 1st odrer **sigma** **delta** modulator provided by cadence in ahdl Library.
I have performed a transient analysis (the input signal is 100KHz and is sampled with a clock 10MHz) and the modulator (...)

Analog Circuit Design :: 09-23-2011 09:24 :: laoud :: Replies: **1** :: Views: **1298**

when i simulate a **sigma** **delta** adc in cadence a time it is perfect another time it got bad and it is the same circuit does any one say to me why?????????????????????????????????????????????????????

ASIC Design Methodologies and Tools (Digital) :: 06-23-2011 01:29 :: hoka_89 :: Replies: **0** :: Views: **577**

i am trying to design a decimator for **sigma** **delta** converter . my decimation factor is 48. from material i found i decided on a CIC filter for first stage (decimation of 24) and a CIC filter as second(decimation of 2).
sampling freq =3840 KHZ
Fin = fin = 0-80khz
stop band attenuation = 100 dB
About the SINK filter according to Hogenauer's

Digital Signal Processing :: 04-24-2011 18:35 :: fasto2008 :: Replies: **0** :: Views: **1435**

Digital Signal Processing :: 12-26-2010 13:40 :: pankaj jha :: Replies: **0** :: Views: **1757**

I am trying to simulate the ∑Δ adc in simulink... on running it thr following error messages are prompted... can anybody help me how to do away with the errors..
1) Only 'double' signals are accepted by block type Integrator. The signals at the ports of '**sigma**_**delta**_adc/Integrator' are of data type 'boolean'.
2) An error occurred while

Digital communication :: 12-26-2010 07:11 :: pankaj jha :: Replies: **0** :: Views: **888**

HI GUYS
i am working in mentor garphics DAIC tool for modelling the switched capacitor resonator LDI Loop for **sigma** **delta** adc. actually i want to estimate the opamp specifications for my design using a macro block present in the mentor graphics....actually my problem is while simulating i am getting some error. due to which tool do not invoke EZ

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-26-2010 08:43 :: ASHUTOSH RANE :: Replies: **1** :: Views: **1234**

Hi, Folks!
I am looking for the tutorial paper "Oversampling Methods for A/D and D/A Conversion."
It is the first paper in the book "Oversampling **delta**-**sigma** Data Converters - Theory, Design and **simulation**."
Can anyone direct me as to where to find this material on internet?
Thank you very much.

Analog Circuit Design :: 08-23-2010 04:22 :: fhchen2002 :: Replies: **4** :: Views: **1130**

Hi, i need the spectre netlist of " device noise **simulation** of **sigma** **delta** modulators "
From here, , the matlab script will be got. but the spectre netlist is missed.
i want to re-simulate the 2nd order **sigma** **delta** converter using specterRF simulator. so i need the netlist.
please give me a copy !
Than

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-10-2010 08:03 :: dongzz201 :: Replies: **0** :: Views: **606**

Hi everyone
I met a question in the designing the mash **sigma****delta** adc.
In my design, it is a 2-1-1 mash, every stage has 1-bit flash. I use the scaling factor as in book(cascade **sigma** **delta** adc for sensor and telecom).
I have finished the schematic, and is doing the spectre **simulation** for (...)

Analog Circuit Design :: 07-20-2010 13:34 :: gdhp :: Replies: **4** :: Views: **1667**

Hi,
I try to match model of first order **sigma** **delta** to spectre **simulation** results, but they disagree!
First figure attached is first order **sigma**-**delta** model (comparator shown as a summing node and noise source N(s)). Can solve to get:
Y = N/(1+H) + H*X/(1+H) where H=K/s
So if K/s >> 1, then: (...)

Analog Circuit Design :: 07-16-2010 22:18 :: ansu_s :: Replies: **1** :: Views: **1117**

hi every one
I want to design and **simulation** a decimation filter for a **sigma** **delta** loop in hspice.
I need information about this filter and several type of this filter circuit.
tanx

Elementary Electronic Questions :: 07-06-2010 09:09 :: alitajari :: Replies: **0** :: Views: **947**

Hi all,
Can someone help me with a **simulation** in Matlab for the two modulations (**delta** and **sigma**-**delta**), i need it for a project.
Thanks.

Digital communication :: 06-27-2010 09:46 :: geo2007 :: Replies: **0** :: Views: **1701**

Can anybody please help me simulate a **sigma** **delta** modulator in LTspice?

Digital communication :: 05-29-2010 09:28 :: devidayalsoman :: Replies: **0** :: Views: **2760**

Hi
I'm designing a 3rd order digital modulator, using 1.5 bit quantization for a 3 level output audio Class D amplifier. The SD modulator uses a CIFF structure using coefficients calculated by Schreier's Matlab Toolbox.
Simulated with a 1kHz sinusoid, 13 bit resolution. **simulation** results seem OK, integrator's never overflow.
The problem i

Analog Circuit Design :: 05-03-2010 18:18 :: fcfusion :: Replies: **0** :: Views: **1019**

Hi all:
The attached graph is the measurement result of designed 2nd 1bit **sigma**-**delta** modulator, It looks that many harmonic tones in the low frequency.
(**simulation** is 16bit, measurement is almost 10.5bit)
Please help to analystic what's design errors may causing this result.
Thanks a lot.

Analog Circuit Design :: 04-07-2010 07:52 :: twteng :: Replies: **1** :: Views: **1057**

hi all,
i have design a **sigma** **delta** adc.
the fft results of both "matlab" and "veriloga" and "veriloga_sw & mos_amp" is fine.
if the veriloga sw be changed to cmos-sw,
the dc noise peak arise, & independent of fft point number.
the 1/R_sw/C_s ~= 6*(2*pi*f_sample).
my english is very poor,
thanks for your help!!
Add

Analog Circuit Design :: 04-01-2010 03:10 :: macron :: Replies: **0** :: Views: **847**

Hi All,
I'm simulating 1-st order continious time **delta**-**sigma** modulator with 2-bit quantizer, but i found out its SNR is only 1 dB better than the 1-bit quantizer:
1-bit SNR=70.3dB @ OSR=256;
2-bit SNR=71.3dB @ OSR=256;
3-bit SNR=80.1dB @ OSR=256.
What's wrong with it?
I use 'calcSNR' function from SDtoolbox to calculate SNR.
Could you p

Analog Circuit Design :: 03-23-2010 14:32 :: VitaMT :: Replies: **0** :: Views: **830**

im using MATLAB **sigma**l **delta** toolbox to implement a **sigma** **delta** bandpass structure. (Center frequency is 1MHz, sampling frequency is 25MHz, bandwidth is 100kHz). Now i have the **simulation** result of a 8-order bandpass structure (the ABCD Matrix).
my questions are:
1:is this stucture with the coefficient (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 01-26-2010 14:47 :: skyrivers :: Replies: **0** :: Views: **726**

im using MATLAB **sigma**l **delta** toolbox to implement a **sigma** **delta** bandpass structure. (Center frequency is 1MHz, sampling frequency is 25MHz, bandwidth is 100kHz). Now i have the **simulation** result of a 8-order bandpass structure (the ABCD Matrix).
my questions are:
1:is this stucture with the coefficient (...)

Analog Circuit Design :: 01-26-2010 11:56 :: skyrivers :: Replies: **0** :: Views: **733**

Hi, all:
I added dynamic dither into my ADC to eliminate spurs due to offset. It is weird that the SQNR of ADC with dynamic dither is higher than that without dither. Is there any one can give me an explain or tell me what could be wrong? I do the **simulation** in Matlab. Both are under the same configuration.
Thanks

Analog Circuit Design :: 01-11-2010 09:34 :: jennysheng :: Replies: **0** :: Views: **981**

Pls tell the way you simulated. Is the spur you got from the closed loop pll **simulation** or the sdm itself?
and what is your fractional number? The spur depends on your input fractional number!

Analog Circuit Design :: 09-24-2009 06:53 :: mengcy :: Replies: **5** :: Views: **1650**

I am a new comer to **sigma**-**delta** Modulator.
Now I working on a two order SDM, ENOB=13bit
Fist I do ideal **simulation** in Matlab, and find the output swing of integrator is -3v~+3v
But 3.3v transistors are used in our design, does this means the design in Matlab is improper, I have to choose a another set of coefficients?
Another (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-14-2009 08:25 :: finerain22 :: Replies: **3** :: Views: **2192**

Hi,all.
I followed the method of kundert and constructed a pll time domain model to simulate the total phase noise.The model can work correctly,but when I extended it to **sigma**-**delta** fractional pll,the output phase noise seems unreasonable.The **sigma**-**delta** modulator is a MASH1-1-1 one.I wanted to see the output phase (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-10-2009 08:57 :: hhq414 :: Replies: **4** :: Views: **1576**

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