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48 Threads found on Simulation Timing Check
I have finished synthesizing my circuit in design compiler. Now I want to do a gate level simulation in Modelsim in order to get the power consumption. The gate level simulation works correctly, but generates "xxx" when annotated with the SDF generated by design compiler. I've tried to reduce the clock frequency but still get the same result. I sho
The simulator runs as fast as your computer lets it. The simulation times are accurate but not real-time as mdorian stated. To check the program simulation running time, use 'Debugger/Stopwatch' from the menu bar. Make sure you reset it if you are timing the delay between different parts of the program. It is very useful (...)
When doing gate-level simulation with SDF annotated, we can use options to tell simulator use minimum, typical or maximum values specified in file.sdf be annotated on the design. My question is, does this option effect which value (min/typ/max) should be used for timing check in SDF? For example, if there are below two lines in SDF: (...)
Sir, I have generated netlist for a 16 bit counter using Encounter RTL the synthesis I set the clock as define_clock -period 3500 -name clk and in the timing report generated a have a positive slack - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk) capture
HI actually its not possible to post code....... Why not, I'm primarily interested in the testbench and the portion of the design that distributes the clock that drives the first register that gets data. If my theory is correct you've got data that is captured on the same edge it transitions. e.g. [FONT=Co
STA does not check any functionality. Gate simulation with timing of the scan, will confirm that the model used for analog-pad... are correct, and the timing checked during STA is also align.
The simulation problem is caused by 1 ms "Minimum Trigger Time" of Display model. I didn't check if the display timing is suitable for real hardware.
I don't really understood your response. 1- first we run simulation at RTL level to check the functionality 2- LEC is used to garantee the functionality is the same between the RTL and all netlists generated during the backend flow. 3- the gate simulation is done to check the timing (ovelap with STA) LEC is (...)
We are doing simulations without timing to check that the pattern generated is properly working or not.... with timing simulation purpose is to check that SDF is proper or not means timing closure is working well or not... After fabrication, design is working in serially so (...)
Hello, I've been trying to calculate average power with PrimeTime PX. I designed a simple FF in Verilog and synthesized it with DesignCompiler Topographical mode. After synthesis, when I simulate the netlist with SDF annotation, I've got following warnings. ================================================================================
Well for simulation, the verilog RAM model are usually quite simple to understand and to check versus the data sheet. Could you clarify which RAM verilog model you used for synthesis? the synthesis tool need a liberty file, no? And the liberty file is also "quite" simple. A liberty describe timing arc between i/o which also available on (...)
The simulation in post #1 is missing one input signal. Also the exact timing relation of clock and input matters. It can't be seen from the waveform, we need to see the textbench code. It would be much clearer if you change the input data not exactly at the clock edge.
Please check the simulation setup is not pessimistic compared to synthesis setup. Other way to ask you Is simulation setup matching with synthesis setup.
Hi, I am simulating the pattern generated by tetramax in ncverilog. I have used no timing check off. This is just a basic scan chain shift test. My chain is failing right from the start ...with the below message : Netlist : {dc generated} >> Error during scan pattern 1 (detected from unload of pattern 0) >>> At T=637315.00 ns, V=6374,
I have seen couple of posts on this forum as well as where people have suggested disabling timing check during gate level timing simulation. My point is what is the use of gate level timing simulation, if you disable timing check? It is true (...)
Are you seeing Expect Simulate X? ? If yes, do you have timing violation messages during simulation? Any timing violations result in the FF output being set to ?X?. Fix these violations. You can use ATPG tool that will simulate your pattern and shows the expected value which you can compare with your actual value and track back (...)
Someone said that the SDF gate simulation will check the false path is correctly setting in the timing constraint(.pt). But I think it's not reasonable because in the test bench, the clock generation is different with the clock setting(synchronous or asynchronous) in the timing constraint. So the gate (...)
I tried report timing -to > timing.rpt, but in the timing.rpt, I still got one critical path timing. Actually, I want to know every gate load capacitance the RTL complier used for a big circuit. Then I can check the accuracy of NLDM w.r.t. spice/spectre simulation. is there any (...)
Hey Sun_ray, During Static timing Analysis (STA), design functionality is "NOT" checked, only timing is checked to see if it meets the timing specification. That is why gate level simulation is done with timing to see if functionality is correct with (...)
gate level simulation is done mainly to check for timing. The main tool for timing is static analysis. gate level takes very long time to run and usually comes as a second measure covering partially of the timing. So one gains confidence in the STA assorted assertions he made as well as of the synthesis (...)
Hi terry8, The verilog which modelise the flop contains some time check (hold/setup). The sdf back attonate the verilog to indicate what are the margins and delay... During your simulation post-layout with timing, the simulator will check that all this time check are respected, like hold time on D pin (...)
Hi, Now I meet a post-simulation issue. My RTL code is verilog code. After per-simulation, I did synthesis by using Design Complier and did place and route by using encounter. When I did place and route, I fixed some hold violations by using optimization of encounter. Then, no setup, hold, max_capacitance, max_transition and max_fanout violati
Handling the cross async. clock domain's gate-level sim, I usually modify the sdf file's timing check part to avoid the "X" in simulation.
HI I want to do gate-level simulation for the synthesised netlist without annotating the sdf file. I just want to verify the function of the netlist not timing. I use ncverilog to simulate the netlist with the following command: ncverilog mydesign.v -v tsmc18.v -v RA1SHD_1024x32.v +notimingcheck +delay_mode_zero (...)
When I do gat-level simulation, I use two SDF, "max" which is outputed by SignalStrom and "SI" which is outputed by Celtic, to generate one SDF using PrimeTime. When runing simulation in NC-SIM, some path cannot be annotated... Such as: ncelab: *W,SDFNET: Failed Attempt to annotate to non-existent timing check (HOLD (...)
Hi holysaint There might be lots of possibilities . Maybe the memory model is not correct . Maybe the simulation options are not set correctly. I will go check the spot where fail_h go high . If the memory output is X , there might be timing violations .
i am trying to do a simulation with a pre-CTS sdf, so i am forced to hack the clock tree cell delay and interconnect delay to 0, but it will cause hold timing violation on DFF, so, how can i turn off "hold" timing check in ncverilog? i know, i can make sdf annotator ignore hold time annotation, but the verilog library still (...)
Can any one explain me in detail what is FF(best case)/SS (worst case) corner timing simulation ?
I use VCS to run post-simulation, but I don't know how to disable timing check in the simulation. Anyone can tell me? Thanks
I dont get the question. usually you just develope your general design with VHDL or verilog and then you can use synthesis and simulation tools to check wether a specific device is suitable or not(regarding resource usage, timing specs and financial issues...). buying the FPGA is the last step.
The timing of s/h is no-overlap? There is a large harmonic in your circuit. check the harmonic frequency. The do .tran simulation, check the SC-op settling.
I receive the message below when i run post-layout simulation with back annotation in VCS: "SDF error: cannot find timing check" Can anyone tell me how to solve this problem?
I verified my design in RTL using VCS. And its function is ok. After I synthesized my design, it failed in netlist simulation. Now, what should I check and how? Thank you!
Hi, I am working Netlist simulation on .13um TSMC library. While loading the design modelsim say that "negative check specify delay to zero" How will I inform the tool to annotate negative delays. I am not using +no_ngchk option. So unless otherwise we specify, it should annotate negative delays aswell. In library I found "`ifdef NTC" what is
It is said as static because the timing information is obtain through calculation, not by simulation STA analysis the delay of all paths register to register, input to register, register to output and check if there is a violation if the delay of one path is too large, there will be setup violation. the target register will sample the old (...)
Have you checked the timing by using the sign-off tool such as primetime or other vender tool. If you did it and you confirmed your timing check script is well, I suggest you check your simulation vectors, maybe they are too ideal. If you vectors are well, maybe you need modify your (...)
the diff between gate level and RTL level is only gate level need check timing. You can firstly pass netlist with STA and Formality check and then run a case, but for many design gate level simulation is not necessary after STA and Formal verification.
Recently,i do STA for FPGA design by using PT. Our design is to implement a MCU in FPGA, which is prototype simulation for soc. I am the first time to do such work, but i found PT is not the best tool for FPGA. i will list the reason beneath 1. When i check the a sdf file in pt shell, i found a lots of missing in timing delay (...)
Hi all could anybody tell me that what is the difference between RTL simulation and Gate level simulation. cause behind the result mismaches between both. Thanks
hi, When i sythesis a design and then do a simulation. I found some warning in log when simulating. Whe warning is like below: Warning: timing violation:................. There are thounds of the warning. Why ? Did i use the comand "write_sdf" wrong in synthesis scripts? In the scripts" write_sdf -force_caculation -edges noedge -int
If my simulation includes only PFD, CP and the loop filter components, what simulations do I have to run to make sure my PFD/CP is working ok? I've run phase sweep between 2 identical frequencies going into the PFD, and plotted average integrated CP output current vs. phase difference to check to dead zone. Assuming the DC analysis for CP (...)
hi,guys, i encounter a problem with gate-level simulation, run in modelsim,it appear the following : ------------------------------------------------------------ r: ../../libs/modelsim_asic/fsc0g_d_sc.v(18445): $setup( negedge D &&& ~SEL:2841 ps, posedge CK:3 ns, 267 ps ); Time: 3 ns Iteration: 5 Instance: /../../../../../reg_coeff_data_reg
Hello aji_vlsi. If we disable the timing checks , is it going to make the post simulation less accurate ? Some eda simulation tools , rounded off negative timing checks for certain fab. Is it allowable , lets say for .35um ? Does it affect the accuracy of the timing info ? (...)
there is no need to do once ur design passes max and min simulations. max simulation will give all possible setup violations and min simulation will give all hold violation. If the design passes these two, ur design will work. but why typ case fails?. If u increase the speed beyond ur min case passing speed, u will fail as far as hold (...)
1. glitch(cannot found in FPGA) 2. timing(simulation/AE testing not complete , logic/model error ... ) 3. leak current , floating signal , power consumption not as expected.
Hi!!! Could anyone tell me how to run synthesized simulation (simulation tools is Cadence's nc-sim & compiler tools is Synopsys's DC)?? Which files to need??? *.sdf or *.v??? Could anyone to provide method for me ?? If you have any suggestion please let me more clear...
Formal and STA can't replace the gate simulation(pre-simulation and post-simulation). 1). Formal tools only check the function of the design. It compare design between the different levels, and don't care the timing. 2). STA tools will check the timing of path which (...)
Without the accurate model, the timing check is rough. Also PAD timing need be considered in synthesis constrain, i.e. input_delay... In final we check function and timing in simulation with SDF files. I faced this problem too.Because I didnt have plenty of time to inspect this , (...)