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How can calculate the sine and consine function by using fpga or VHDL code? For synopsys users: If you have the DesignWare Foundation Library (dw_2) licensed, you can use the DW02_sincos model. see attached file.
Hello friends!, I'm using xilinx fpga. I need to multiply two input sine waves(from ADC) of same frequency and amplitude inorder to cancel the phase shifts and get double of it's frequency.(If you product 2 sine of same freq,it's freq inputs are 14-bit from ADC(unsigned integer from 0 to 16383)and output is to a 14-bit DAC. I tried mult
Hi guys, how to implement sine inverse in fpga.. please help me in doing this....
Hi, I am generating 25MHz sine wave using DDS core. Simulation is working perfectly but hardware is not working. I am implementing simple DDS core. Can you please tell me what can be the possible reason?
OK! sine and cosine generation is an old problem, usually solved using look up tables, specially when the frequency of sine and cosine waves are fixed. if the frequency is variable and you should compute a different sine or cosine value each time, then you should compute it and as our (...)
I am required to implement a sine wave generator and frequence range is 0.005hz to 5000hz. Given the clock is 100mhz, the problem is whether DDS can generator this frequence range sine wave. If it can, how many bits have the phase acc as well as how long sine table(a whole period) Is there someone tell me how to computate these (...)
Try these..
Hi, I created a RRC filter for an fpga using ONEoverT from Tyder. The VHDL was created fine as well as all the test data and modelsim compile macro. However, when I simulate the design, I expect to see a sine wave at the output, but I don't. I see output values however, but the it is not in an analog format. The documents with the software s
You might also google 'magic sinewaves"
Hi all I am trying to make an fpga produce from its IO pins pulses with duty cycle 50%. The frequency of the pulse must be able to change it from 1 Hz to 10-15 Mhz with a step 1 Hz. I have used accumulators to accomplish that. (Idea taken from DDS). I dont care to make the pulse waveform to a sine one so i dont use DAC or memory to write
i have to implement math functions in fpga. one way is to express sine function in term of its maclauran series. since in maclauran series we have to compute factorial,divide, add,subtract arithmatics to find sine function which is very lenthy. please tell me any other method to implement this. use edatools coregen li
I'm a newbie with fpga and looking for some help in my project. I have a signal which is a number of pulses of 100 kHz sine sampled at 1 MHz. The problem is that it is shadowed in a number (up to 10) of interfering continues wave signals at frequencies in 50-200 kHz band, and I want to suppress them. I decided to use a bank of 2nd order IIR no
Hi, I'm currently in the process of developing a control scheme for a custom power device using fpga. The control scheme processes the error voltage through a PI controller whose output (PI output) is used to phase modulate the sinusoidal waveform (50 Hz). The phase modulated waveform is then compared against a triangular carrier wave to generate
Hi guys,I am new to Verilog and am writing a code for DDS .I want to know if there are code in Xilinx fpga Verilog for DDS.I wrote a very very simple code based on the Xilinx Coregen sine LookUpTable.I want to know if there is any other code using Advanced Interpolation Techniques.Here is the simple code I wrote module dds(CLK,WCLK,
I agree with FvM, You can create a simple lookup table for 1/4th of your sinewave, then repeate it 4 times up and down to get the correct sinus output values. The size of the lookup table depends on your frequency. Take a look at this Xilinx App-note for some ideas on how to do it:
hi to all. i have a project in which I have to demodulate a fsk-modulated signal that comes from a adc which samples at 5mHzin fpga. to do that, I have to design two bandpass filters at 690 kHz and 710 kHz. Now I am trying to simulate it in matlab to make sure it works. this is my code: close all; %clear; % find the period of the transmitted sin
The below wiki link has some Matlab code: Gabor filter - Wikipedia, the free encyclopedia Not sure whether its the complete code. Possible difficulties during the VHDL implementation are: 1)Fixed point operation handling. 2) Calculating sine and cosine values, exponential values. 3)Large memory nee
I want to implement FFT on fpga.. i am using the approach of Microblaze processor... A to D converter will give the sine function in digital form to the fpga kit then this sine wave will be sent for FFT and after FFT the result ll be sent to LCD for display. all this management ll be done by Microblaze processor... is the
you can use ad9851 for sine wave generator and you can generate sine and triangle with that
The frequency of your sinewave depends on 2 things, the first is the number of sample your VHDL is generating for each cycle and the second one is the frequency of the clock that writes to the DAC. Say, you have 256 steps for your sine wave, and your clock frequency is 25.6 MHz, you will get a sinewave signals that is 100 KHz.
Why don't you sent a pn sequence? May be an option, the original poster should clarify the requirements. I was already wondering what's the purpose of a "combination of three sine waves". I guess it's a small band (e.g. US) transducer, having a sine burst as impulse response anyway. And the intention is to achieve a time resoluti
I want to implement BPSK modulator and demodulator in verilog on spartan 3 kit. If anyone has done that on any fpga, i request your guidance... I know the concept that for transmitting '0', we send the sinusoid as it is and for '1' we add 180 phase shift to the sinusoid. I request guidance on following points - BPSK modulator, demodulator b
Hi, Is it (if is then how) possible to generate sine wave with frequency lets say 15kHz and 20kHz having only CLK of 48kHz ? Im asking because I wanted to generate this type of a signal and send it through I2S to the AC97 codec on my board and connect it to PC and see signal and its spectrum in SpectraLAB (or any other program which has FFT opti
Hi, I was asked to figure this out at work and I need some help! I have a LVDT (Linear Variable Differential Tranformer) that spits out sine waves at 2 KHz, and I want to sample those sine waves 20 times per cycle (sample rate = 40 KHz?). Eventually those sampled rms values will be used for calculating addition, subtraction, divisions and CRCs
hi dear all... I have a vector consist of sine and cosine valus (A complex exponential) in MATLAB. How to generate a look-up table with this values in verilog? I know that should be use a block-RAM, but I don't know how to write verilog code. please help me. the values placed in a 4096×1 vector in MATLAB. I think a 4K RAM should be used, is it
Instead using Cordic generate sin wave with DDS. Then during input signal change change the phase of the sine wave by reading from different location. This works. I've done this. vhdl4u gmail com
but I have to produce the phase difference between two sine waves oscillating at 1-3 GHz. The signal is analog So why do you think to use digital logic ICs? Also, you said I/O delay of any pin would provide the delay, so how can I use this feature of a digital IC. I said it's a multiple - and it will be very inacc
for a simple square wave, it like a clock. You need just a counter in your vhdl code. But for sine wave i think you need A/D Hardware.
For sine and cosine you only need a quarter of full function period. Just look at sine wave period and you can get it why. This is also why you don't need separate tables for sine and cosine. Also tangent is sin(x)/cos(x), but i don't know wheter this can be useful. Also you don't need that many points in (...)
Sir I made a Variable Frequency sine Wave Generator that can vary frequency from 90 to 150Hz, its running fine, but the problem is that the noise in sine wave gets pronounced in between the certain frequency band as can be seen in screen # 4, below & above that band there is less distortion, what I should do to suppress that noise??? [ATTACH
I am working on a final project for graduate school. I need to be able to calculate cos (x) and sin (x) in VHDL code. My professor tells me I should use a look up table for cos and sin values. I have never worked with look up tables in VHDL and I am a bit confused on how to do this in VHDL. Any suggestions? Example: cos (2) = -0.4161 (I n
I had used Taylor series expansion to generate sine & cosine waves. You can select the no. of terms to give a accurate looking waveform in the simulator!
I am an electrical engineering student and working on the speed control of PMSM motor using fpga kit SPARTAN 3E. I need sine wave generator code for 2-3 phase converter application ia = sin θ. iq ib = sin (θ-2Π/3). iq ic = sin (θ+ 2Π/3). iq iq= 8 bit input and θ is also a 8 bit input ia,ib,ic are all 8 bit
those equation alone enough to design nco in verilog??? I guess, you are referring to the description of NCO operation in IP core manual? A NCO is comprised of a phase accumulator, a sine table respectively generator algorithm and optionally modulation means. These are essentially simple operations and can be coded from the scr
Hi to all, I need to generate in the fpga a very precise sine wave. The frequency of the sinewave is constant while the Amplitude and the Phase change. The aim is not to utilize the sinewave to drive a DAC but instead to use it for signal processing inside the fpga. Now... an example: I have a 2.5 (...)
hi, with my fpga altera i've to generate a pwm signal for a 40-180Hz sine wave. I've started from this application note and i've used the vhdl of ddfs to generate the wave. I've modified the parameter in order to obtain an out frequency of 1Hz for Freq_Data=1 and a 243HZ for Freq_Data=255. So For
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments.... For fpga design, what I have used synthesis tools(only to synthesis VHDL code): Synplicity Synplify > Synopsys fpga Compiler II > Mentor Leonardo Exemplar It is only my personal opinion...
In the next months i have to migrate a fpga VirtexII VHDL design (near to million gates) to ASIC. In the original design i use a classic fpga flow using as main tools Synplify+Amplfy+Modelsim, but i think boundary conditions,timing constraints and layout (even synthesis) in ASIC will be very different and other flow and considerations will be us
Hi friendz, Here is a very good link of publications on various fpga Technologies by Dr.Jonathan Rose.Njoy the great stuff..... Regards - satya ======================================= "Talent does what it can; genius does what it must." - Edward George Bulwer-Lytton (1803-1873) ==
Hi fpga CPU Links 1. -> t tnx
The practical Xilinx Designer Lab book by "Dave Van den Bout" from prentice hall is a very good starting point for beginners in fpga field. In this book two proto boards from XESS Corporation are described with schematics etc. - XS40 board for Xilinx fpga XC4005XL and XS95 for Xilinx XC95108 CPLD. The s/w for this boards are free and can be downed
Hi, I want to built a test evulation board for fpga from xilinx the idea is to built this simple JTAG Programmer in a test board and use IMpact software to download the code . IMpact software are integ
How to convert the fpga to asic quickly, smoothly, and efficiently? Thx in advance.
Anybody know of a good application note or enginners note for porting an existing ASIC netlist to xilinx fpga? :o
I am not sure if this link has been posted already, but another fpga and ASIC course can be found
Hi, can anyone give me some good references/links/books for information on designing systems that consist of a CPU core, with functionality implemented around the CPU (such as ethernet controller, hard disc controller), that are implemented on an fpga. I am unsure of the number of macrocells a typical fpga has, and the macrocells required to imp
Already have fpga compiler, why need Design Compiler (DC)? what is differences ?
Hi This tutorial describes the process of creating a working fpga design from VHDL. 1. -> t tnx
Is there any fpga tools that can help me insert scan chain for DFT?
Help! I have just installed fpga Compiler 3.7.0.7408 (2001.08-FC3.7) and loaded up a vhdl file. Problem is, for almost all technologies (Atmel, Cypress, Lattice, etc.) I don't get any timing information after optimization (estimated clock freq. says "no paths", and all clock<->combinatorial delays are N/A, all clock<->clock delays are 0) and my