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88 Threads found on edaboard.com: **Sine Fpga**

How can calculate the **sine** and con**sine** function by using **fpga** or VHDL code?
For synopsys users:
If you have the DesignWare Foundation Library (dw_2) licensed, you can use the DW02_sincos model.
see attached file.

PLD, SPLD, GAL, CPLD, FPGA Design :: 21.02.2003 05:46 :: gnomix :: Replies: **19** :: Views: **11992**

OK! **sine** and co**sine** generation is an old problem, usually solved using look up tables, specially when the frequency of **sine** and co**sine** waves are fixed.
if the frequency is variable and you should compute a different **sine** or co**sine** value each time, then you should compute it and as our (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 02.11.2004 11:44 :: mami_hacky :: Replies: **5** :: Views: **2221**

I am required to implement a **sine** wave generator and frequence range is
0.005hz to 5000hz. Given the clock is 100mhz, the problem is whether DDS can generator this frequence range **sine** wave. If it can, how many bits have the phase acc as well as how long **sine** table(a whole period)
Is there someone tell me how to computate these (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 27.04.2005 21:16 :: skycanny :: Replies: **8** :: Views: **1429**

Hi
DDS souce code.
Best Regards
Architecture DDS_arch of DDS is
subtype WAVE is STD_LOGIC_VECTOR (5 downto 0);
type ROM is array (0 to 63) of WAVE;
constant **sine** : ROM := (
"100000","100011","100110","101000","101011","101110","110001","110011",
"110101","110111","111001","111011","111100","111101","111110","111110",

PLD, SPLD, GAL, CPLD, FPGA Design :: 19.08.2005 04:28 :: yodathegreat :: Replies: **5** :: Views: **2442**

Try these..

Electronic Elementary Questions :: 21.09.2005 03:16 :: dynamicdude :: Replies: **5** :: Views: **1404**

Hi,
I created a RRC filter for an **fpga** using ONEoverT from Tyder. The VHDL was created fine as well as all the test data and modelsim compile macro. However, when I simulate the design, I expect to see a **sine** wave at the output, but I don't.
I see output values however, but the it is not in an analog format.
The documents with the software s

Digital Signal Processing :: 08.11.2006 07:28 :: alanmck :: Replies: **0** :: Views: **632**

You might also google 'magic **sine**waves"

PLD, SPLD, GAL, CPLD, FPGA Design :: 21.04.2007 00:27 :: cherrytart :: Replies: **8** :: Views: **2804**

Hi all
I am trying to make an **fpga** produce from its IO pins pulses with duty cycle 50%.
The frequency of the pulse must be able to change it from 1 Hz to 10-15 Mhz with a
step 1 Hz.
I have used accumulators to accomplish that. (Idea taken from DDS). I dont care to
make the pulse waveform to a **sine** one so i dont use DAC or memory to write

PLD, SPLD, GAL, CPLD, FPGA Design :: 06.06.2007 13:05 :: blitzwing :: Replies: **1** :: Views: **1469**

i have to implement math functions in **fpga**.
one way is to express **sine** function in term of its maclauran series. since in maclauran series we have to compute factorial,divide, add,subtract arithmatics to find **sine** function which is very lenthy.
please tell me any other method to implement this.

ASIC Design Methodologies and Tools (Digital) :: 23.10.2007 06:43 :: rubnawaz :: Replies: **5** :: Views: **991**

I'm a newbie with **fpga** and looking for some help in my project.
I have a signal which is a number of pulses of 100 kHz **sine** sampled at
1 MHz. The problem is that it is shadowed in a number (up to 10) of
interfering continues wave signals at frequencies in 50-200 kHz band,
and I want to suppress them. I decided to use a bank of 2nd order IIR
no

PLD, SPLD, GAL, CPLD, FPGA Design :: 25.10.2007 05:09 :: Unomano :: Replies: **1** :: Views: **701**

Hi everybody,
I got some problems during the implemenation of a simple delay generator on Stratix II. I realized a shift-register ram based with many taps, so I could select the desired delay for the circuit.
After implementation I analyzed the behaviour giving a **sine** wave to adc of the evaluation board (ep2s60) and then viewing the samples sende

PLD, SPLD, GAL, CPLD, FPGA Design :: 20.03.2008 05:53 :: GertDalPozzo :: Replies: **1** :: Views: **1072**

Hi,
I'm currently in the process of developing a control scheme for a custom power device using **fpga**. The control scheme processes the error voltage through a PI controller whose output (PI output) is used to phase modulate the sinusoidal waveform (50 Hz). The phase modulated waveform is then compared against a triangular carrier wave to generate

PLD, SPLD, GAL, CPLD, FPGA Design :: 08.04.2008 03:26 :: rjai_pradha :: Replies: **0** :: Views: **1124**

Hi guys,I am new to Verilog and am writing a code for DDS .I want to know if there are code in Xilinx **fpga** Verilog for DDS.I wrote a very very simple code based on the Xilinx Coregen **sine** LookUpTable.I want to know if there is any other code using Advanced Interpolation Techniques.Here is the simple code I wrote
module dds(CLK,WCLK,

PLD, SPLD, GAL, CPLD, FPGA Design :: 18.05.2008 10:38 :: maheshkuruganti :: Replies: **0** :: Views: **5005**

Hello friends!, I'm using xilinx **fpga**. I need to multiply two input **sine** waves(from ADC) of same frequency and amplitude inorder to cancel the phase shifts and get double of it's frequency.(If you product 2 **sine** of same freq,it's freq inputs are 14-bit from ADC(unsigned integer from 0 to 16383)and output is to a 14-bit DAC. I tried mult

PLD, SPLD, GAL, CPLD, FPGA Design :: 27.11.2008 04:28 :: xtcx :: Replies: **0** :: Views: **1431**

Hi guys,
how to implement **sine** inverse in **fpga**..
please help me in doing this....

PLD, SPLD, GAL, CPLD, FPGA Design :: 29.01.2009 04:21 :: vinodkumar :: Replies: **2** :: Views: **661**

I agree with FvM,
You can create a simple lookup table for 1/4th of your **sine**wave, then repeate it 4 times up and down to get the correct sinus output values.
The size of the lookup table depends on your frequency.
Take a look at this Xilinx App-note for some ideas on how to do it:

PLD, SPLD, GAL, CPLD, FPGA Design :: 28.09.2009 04:04 :: farhada :: Replies: **4** :: Views: **1658**

hi to all. i have a project in which I have to demodulate a fsk-modulated signal that comes from a adc which samples at 5mHzin **fpga**. to do that, I have to design two bandpass filters at 690 kHz and 710 kHz. Now I am trying to simulate it in matlab to make sure it works. this is my code:
close all;
%clear;
% find the period of the transmitted sin

Digital Signal Processing :: 28.12.2009 17:22 :: fena :: Replies: **0** :: Views: **1022**

The below wiki link has some Matlab code:
Gabor filter - Wikipedia, the free encyclopedia
Not sure whether its the complete code.
Possible difficulties during the VHDL implementation are:
1)Fixed point operation handling.
2) Calculating **sine** and co**sine** values, exponential values.
3)Large memory nee

PLD, SPLD, GAL, CPLD, FPGA Design :: 31.03.2011 00:33 :: vipinlal :: Replies: **4** :: Views: **1630**

I want to implement FFT on **fpga**..
i am using the approach of Microblaze processor...
A to D converter will give the **sine** function in digital form to the **fpga** kit then this **sine** wave will be sent for FFT and after FFT the result ll be sent to LCD for display.
all this management ll be done by Microblaze processor...
is the

PLD, SPLD, GAL, CPLD, FPGA Design :: 19.04.2010 01:31 :: kajulkumar :: Replies: **8** :: Views: **2132**

you can use ad9851 for **sine** wave generator and you can generate **sine** and triangle with that

Analog Circuit Design :: 24.05.2010 22:08 :: rajudp :: Replies: **9** :: Views: **3137**

The frequency of your **sine**wave depends on 2 things, the first is the number of sample your VHDL is generating for each cycle and the second one is the frequency of the clock that writes to the DAC.
Say, you have 256 steps for your **sine** wave, and your clock frequency is 25.6 MHz, you will get a **sine**wave signals that is 100 KHz.

PLD, SPLD, GAL, CPLD, FPGA Design :: 18.06.2010 07:50 :: farhada :: Replies: **3** :: Views: **1901**

Why don't you sent a pn sequence?
May be an option, the original poster should clarify the requirements. I was already wondering what's the purpose of a "combination of three **sine** waves".
I guess it's a small band (e.g. US) transducer, having a **sine** burst as impulse response anyway. And the intention is to achieve a time resoluti

Digital Signal Processing :: 11.08.2010 08:44 :: FvM :: Replies: **4** :: Views: **1301**

I'm under the impression, that the DDS IP documentations have good explanations of it's basic operation, it's at least the case for the Altera DDS core.
It's very easy anyway. Simply consider an accumulator of any length, e.g. 32 bit. The frequency value is added each clock cycle, the accumulator is representing the signal phase. An overflow me

PLD, SPLD, GAL, CPLD, FPGA Design :: 06.11.2010 10:58 :: FvM :: Replies: **1** :: Views: **1076**

I want to implement BPSK modulator and demodulator in verilog on spartan 3 kit.
If anyone has done that on any **fpga**, i request your guidance...
I know the concept that for transmitting '0', we send the sinusoid as it is and for '1' we add 180 phase shift to the sinusoid.
I request guidance on following points
- BPSK modulator, demodulator b

PLD, SPLD, GAL, CPLD, FPGA Design :: 09.11.2010 23:28 :: devashishraval :: Replies: **2** :: Views: **2076**

Hi,
Is it (if is then how) possible to generate **sine** wave with frequency lets say 15kHz and 20kHz having only CLK of 48kHz ? Im asking because I wanted to generate this type of a signal and send it through I2S to the AC97 codec on my board and connect it to PC and see signal and its spectrum in SpectraLAB (or any other program which has FFT opti

PLD, SPLD, GAL, CPLD, FPGA Design :: 26.01.2011 17:47 :: Dave_PL :: Replies: **4** :: Views: **1252**

Hi, I was asked to figure this out at work and I need some help!
I have a LVDT (Linear Variable Differential Tranformer) that spits out **sine** waves at 2 KHz, and I want to sample those **sine** waves 20 times per cycle (sample rate = 40 KHz?). Eventually those sampled rms values will be used for calculating addition, subtraction, divisions and CRCs

PLD, SPLD, GAL, CPLD, FPGA Design :: 03.02.2011 11:57 :: Yihan :: Replies: **1** :: Views: **448**

pls help, i m doing my final year project.. which is a (8bit) VHDL model of three phase PWM. i have written vhdl code for the PWM. in the embedded design, i need to write a c-program to generate 3 phase **sine** waves to the port 1 of the TSK51a microprocessor that will communicate with the vHDL model. (also considering an interrupt on port3_3 of the

PLD, SPLD, GAL, CPLD, FPGA Design :: 11.02.2011 19:31 :: ls3ar :: Replies: **0** :: Views: **448**

hi dear all...
I have a vector consist of **sine** and co**sine** valus (A complex exponential) in MATLAB. How to generate a look-up table with this values in verilog?
I know that should be use a block-RAM, but I don't know how to write verilog code. please help me.
the values placed in a 4096×1 vector in MATLAB. I think a 4K RAM should be used, is it

PLD, SPLD, GAL, CPLD, FPGA Design :: 22.02.2011 06:27 :: Amir.B :: Replies: **6** :: Views: **1490**

Instead using Cordic generate sin wave with DDS. Then during input signal change change the phase of the **sine** wave by reading from different location. This works. I've done this. vhdl4u gmail com

Digital Signal Processing :: 20.03.2011 09:16 :: vhdl4u :: Replies: **1** :: Views: **825**

but I have to produce the phase difference between two **sine** waves oscillating at 1-3 GHz. The signal is analog
So why do you think to use digital logic ICs?
Also, you said I/O delay of any pin would provide the delay, so how can I use this feature of a digital IC.
I said it's a multiple - and it will be very inacc

PLD, SPLD, GAL, CPLD, FPGA Design :: 06.08.2011 04:27 :: FvM :: Replies: **12** :: Views: **1419**

for a simple square wave, it like a clock. You need just a counter in your vhdl code. But for **sine** wave i think you need A/D Hardware.

PLD, SPLD, GAL, CPLD, FPGA Design :: 04.09.2011 21:38 :: BuBEE :: Replies: **3** :: Views: **1706**

For **sine** and co**sine** you only need a quarter of full function period. Just look at **sine** wave period and you can get it why. This is also why you don't need separate tables for **sine** and co**sine**. Also tangent is sin(x)/cos(x), but i don't know wheter this can be useful. Also you don't need that many points in (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 01.10.2011 20:11 :: poorchava :: Replies: **6** :: Views: **1598**

It's far from obvious how you achhieved a variable frequency oscillator with a **fpga**. In any case, you should check if the base band signal is a clean **sine**. Apart from modulation signal quality, it may be also a problem introcduced by your PWM modulator. What's the numerical resolution of the PWM setpoint, what's exactly the implemented PWM scheme?

Power Electronics :: 26.11.2011 07:09 :: FvM :: Replies: **10** :: Views: **1229**

There have been various threads about different **sine** generation methods in **fpga**s. Larger look-up tables (LUT) are usually implemented in internal ROM blocks (initialized RAM) as they are provided by most recent **fpga** series. The **sine** function table can be loaded from a file, explicitely coded in a case structure (long winded) (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 01.12.2011 15:40 :: FvM :: Replies: **1** :: Views: **1459**

I had used Taylor series expansion to generate **sine** & co**sine** waves. You can select the no. of terms to give a accurate looking waveform in the simulator!

PLD, SPLD, GAL, CPLD, FPGA Design :: 16.12.2011 08:15 :: dpaul :: Replies: **6** :: Views: **1881**

Hi,
I am generating 25MHz **sine** wave using DDS core. Simulation is working perfectly but hardware is not working. I am implementing simple DDS core. Can you please tell me what can be the possible reason?

PLD, SPLD, GAL, CPLD, FPGA Design :: 28.03.2012 16:22 :: capcas :: Replies: **21** :: Views: **2930**

I am an electrical engineering student and working on the speed control of PMSM motor using **fpga** kit SPARTAN 3E. I need **sine** wave generator code for 2-3 phase converter application
ia = sin θ. iq
ib = sin (θ-2Π/3). iq
ic = sin (θ+ 2Π/3). iq
iq= 8 bit input and θ is also a 8 bit input
ia,ib,ic are all 8 bit

PLD, SPLD, GAL, CPLD, FPGA Design :: 31.03.2012 15:21 :: mohit1108 :: Replies: **1** :: Views: **787**

First of all, you can't produce a 1GHz **sine**wave with a 1 G-SAMPLE/sec DAC. That's SAMPLES/SEC, not CYCLES/SEC.
Second, the waveform you store in RAM doesn't have any 'frequency' associated with it; it's a **sine** wave, that's it.
But , yes, you will get unwanted frequencies in your output. Could you ask a more specific question?
Also, Xilinx

Digital Signal Processing :: 19.07.2012 13:02 :: barry :: Replies: **3** :: Views: **425**

as still I am beginner in Verilog, I found some codes for the trigonometric functions as follows:
function real sin;
input x;
real x;
real x1,y,y2,y3,y5,y7,sum,sign;
begin
sign = 1.0;
x1 = x;
if (x1<0)
begin
x1 = -x1;
sign = -1.0;
end
while (x1 > 3.14159265/2.0)

PLD, SPLD, GAL, CPLD, FPGA Design :: 10.09.2012 16:14 :: Aya2002 :: Replies: **13** :: Views: **1177**

those equation alone enough to design nco in verilog???
I guess, you are referring to the description of NCO operation in IP core manual?
A NCO is comprised of a phase accumulator, a **sine** table respectively generator algorithm and optionally modulation means. These are essentially simple operations and can be coded from the scr

PLD, SPLD, GAL, CPLD, FPGA Design :: 21.12.2012 02:04 :: FvM :: Replies: **9** :: Views: **860**

10 Bit phase and magnitude resolution is a reasonable range for medium quality NCOs, e.g. used with **sine** inverters or active front ends. For test and mesurement 16 bit or better can be appropriate.
The exact relation between phase/magnitude resolution and analog performance, e.g. SFDR (spurious free dynamic range) is a rather complex numerical p

PLD, SPLD, GAL, CPLD, FPGA Design :: 27.01.2013 04:53 :: FvM :: Replies: **6** :: Views: **887**

Hi to all,
I need to generate in the **fpga** a very precise **sine** wave. The frequency of the **sine**wave is constant while the Amplitude and the Phase change.
The aim is not to utilize the **sine**wave to drive a DAC but instead to use it for signal processing inside the **fpga**.
Now... an example: I have a 2.5 (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 16.02.2013 14:59 :: kitepassion :: Replies: **3** :: Views: **374**

At this link:
you will find intersting stuff on cordic and **fpga**.
This is a a doc on " **fpga** Implementation of **sine** and Co**sine** Generators Using the CORDIC..."
Regards,
--rs

Digital Signal Processing :: 12.04.2004 12:10 :: redsk_y :: Replies: **8** :: Views: **5560**

it is easy to understand calculating **sine**, co**sine** and arctan by using cordic,
but how can i calculate square root by using this algrithm
thanks!!!!

ASIC Design Methodologies and Tools (Digital) :: 12.11.2004 11:14 :: JesseKing :: Replies: **1** :: Views: **2259**

In a digital circuit board design, the high speed global clock may be from a TCXO or others. The output of the TCXO is **sine** wave sometimes. we must transform the **sine** wave to a square wave in order to clock some digital device, for example, **fpga** or DSP.
We can use a zero crossing comparator to accomplish the process. With dual supply (...)

Analog Circuit Design :: 01.04.2005 11:33 :: ddt694 :: Replies: **10** :: Views: **3359**

It's too bad that Verilog provides poor support for initializing anything. Both ISE and ModelSim support block RAM initialization, but they use different syntax, so you have to put both formats into your Verilog. And it's ugly syntax!
Here is a 1Kx18 dual-port ROM initialized with a **sine** table. I use both ports so I can read **sine** and (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 25.04.2005 00:42 :: echo47 :: Replies: **5** :: Views: **1026**

LUTs in the **fpga**s can be used only for Digital Computations.
For handling **sine** functions there is a algorithm called CORDIC which stands for CO-ordinate Rotation for Digital Computing.
This algorithm is used in DDFS- Direct Digital Frequency Synthezisers for the generation of sin wave and i have read that it is also used in Calculators for s

PLD, SPLD, GAL, CPLD, FPGA Design :: 16.11.2005 06:09 :: veejaye :: Replies: **1** :: Views: **693**

i am new to vhdl. Is it possible to design fsk, psk modultion and demodulation in MODELSIM( bcoz thats what i have), i dont know how to bring **sine** wave in that..can anyone help me. otherwise anyother simulation tool is available for this???

PLD, SPLD, GAL, CPLD, FPGA Design :: 28.01.2006 05:34 :: brahma :: Replies: **6** :: Views: **2065**

Dear all,
I want to measure my current dac. I have some question.
1.How do I measure my INL and DNL using multimeter?
Because my current dac has 12 bits and 500MHz. Too many points.
How do I measure INL and DNL by using multimeter?
Or if you have some good method , please tell me detail. Thanks.
2.If I want to measure SFDR, how

Analog Circuit Design :: 21.04.2006 04:35 :: yen :: Replies: **3** :: Views: **819**

One chip costs a little more then 1w,I am a beginner of designing with **fpga** .
when design PowerPC,whether in the EDK enviroment can we acommplish it.
This afternoon,I try to double the 100MHz crystal,The output frequecy is 200MHz,But the wave isn't square or like **sine**,The high level is a peak, the low level lasting 80% of the period.can it do fo

PLD, SPLD, GAL, CPLD, FPGA Design :: 30.05.2006 06:54 :: shoufeng_luo :: Replies: **6** :: Views: **752**

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