88 Threads found on edaboard.com: Sine Fpga
How can calculate the sine and consine function by using fpga or VHDL code?
For synopsys users:
If you have the DesignWare Foundation Library (dw_2) licensed, you can use the DW02_sincos model.
see attached file.
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.02.2003 05:46 :: gnomix :: Replies: 19 :: Views: 12004
OK! sine and cosine generation is an old problem, usually solved using look up tables, specially when the frequency of sine and cosine waves are fixed.
if the frequency is variable and you should compute a different sine or cosine value each time, then you should compute it and as our (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.11.2004 11:44 :: mami_hacky :: Replies: 5 :: Views: 2227
I am required to implement a sine wave generator and frequence range is
0.005hz to 5000hz. Given the clock is 100mhz, the problem is whether DDS can generator this frequence range sine wave. If it can, how many bits have the phase acc as well as how long sine table(a whole period)
Is there someone tell me how to computate these (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.04.2005 21:16 :: skycanny :: Replies: 8 :: Views: 1430
DDS souce code.
Architecture DDS_arch of DDS is
subtype WAVE is STD_LOGIC_VECTOR (5 downto 0);
type ROM is array (0 to 63) of WAVE;
constant sine : ROM := (
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.08.2005 04:28 :: yodathegreat :: Replies: 5 :: Views: 2445
Electronic Elementary Questions :: 21.09.2005 03:16 :: dynamicdude :: Replies: 5 :: Views: 1404
I created a RRC filter for an fpga using ONEoverT from Tyder. The VHDL was created fine as well as all the test data and modelsim compile macro. However, when I simulate the design, I expect to see a sine wave at the output, but I don't.
I see output values however, but the it is not in an analog format.
The documents with the software s
Digital Signal Processing :: 08.11.2006 07:28 :: alanmck :: Replies: 0 :: Views: 635
I have to generate a sine wave of 10khz in vhdl and display it on oscilloscope using fpga.
can any body tell me how to do so?
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.04.2007 15:31 :: engrbabarmansoor :: Replies: 8 :: Views: 2809
I am trying to make an fpga produce from its IO pins pulses with duty cycle 50%.
The frequency of the pulse must be able to change it from 1 Hz to 10-15 Mhz with a
step 1 Hz.
I have used accumulators to accomplish that. (Idea taken from DDS). I dont care to
make the pulse waveform to a sine one so i dont use DAC or memory to write
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.06.2007 13:05 :: blitzwing :: Replies: 1 :: Views: 1473
i have to implement math functions in fpga.
one way is to express sine function in term of its maclauran series. since in maclauran series we have to compute factorial,divide, add,subtract arithmatics to find sine function which is very lenthy.
please tell me any other method to implement this.
ASIC Design Methodologies and Tools (Digital) :: 23.10.2007 06:43 :: rubnawaz :: Replies: 5 :: Views: 993
I'm a newbie with fpga and looking for some help in my project.
I have a signal which is a number of pulses of 100 kHz sine sampled at
1 MHz. The problem is that it is shadowed in a number (up to 10) of
interfering continues wave signals at frequencies in 50-200 kHz band,
and I want to suppress them. I decided to use a bank of 2nd order IIR
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.10.2007 05:09 :: Unomano :: Replies: 1 :: Views: 702
I got some problems during the implemenation of a simple delay generator on Stratix II. I realized a shift-register ram based with many taps, so I could select the desired delay for the circuit.
After implementation I analyzed the behaviour giving a sine wave to adc of the evaluation board (ep2s60) and then viewing the samples sende
PLD, SPLD, GAL, CPLD, FPGA Design :: 20.03.2008 05:53 :: GertDalPozzo :: Replies: 1 :: Views: 1075
I'm currently in the process of developing a control scheme for a custom power device using fpga. The control scheme processes the error voltage through a PI controller whose output (PI output) is used to phase modulate the sinusoidal waveform (50 Hz). The phase modulated waveform is then compared against a triangular carrier wave to generate
PLD, SPLD, GAL, CPLD, FPGA Design :: 08.04.2008 03:26 :: rjai_pradha :: Replies: 0 :: Views: 1127
Hi guys,I am new to Verilog and am writing a code for DDS .I want to know if there are code in Xilinx fpga Verilog for DDS.I wrote a very very simple code based on the Xilinx Coregen sine LookUpTable.I want to know if there is any other code using Advanced Interpolation Techniques.Here is the simple code I wrote
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.05.2008 10:38 :: maheshkuruganti :: Replies: 0 :: Views: 5011
Hello friends!, I'm using xilinx fpga. I need to multiply two input sine waves(from ADC) of same frequency and amplitude inorder to cancel the phase shifts and get double of it's frequency.(If you product 2 sine of same freq,it's freq inputs are 14-bit from ADC(unsigned integer from 0 to 16383)and output is to a 14-bit DAC. I tried mult
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.11.2008 04:28 :: xtcx :: Replies: 0 :: Views: 1434
how to implement sine inverse in fpga..
please help me in doing this....
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.01.2009 04:21 :: vinodkumar :: Replies: 2 :: Views: 664
I agree with FvM,
You can create a simple lookup table for 1/4th of your sinewave, then repeate it 4 times up and down to get the correct sinus output values.
The size of the lookup table depends on your frequency.
Take a look at this Xilinx App-note for some ideas on how to do it:
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.09.2009 04:04 :: farhada :: Replies: 4 :: Views: 1659
hi to all. i have a project in which I have to demodulate a fsk-modulated signal that comes from a adc which samples at 5mHzin fpga. to do that, I have to design two bandpass filters at 690 kHz and 710 kHz. Now I am trying to simulate it in matlab to make sure it works. this is my code:
% find the period of the transmitted sin
Digital Signal Processing :: 28.12.2009 17:22 :: fena :: Replies: 0 :: Views: 1027
The below wiki link has some Matlab code:
Gabor filter - Wikipedia, the free encyclopedia
Not sure whether its the complete code.
Possible difficulties during the VHDL implementation are:
1)Fixed point operation handling.
2) Calculating sine and cosine values, exponential values.
3)Large memory nee
PLD, SPLD, GAL, CPLD, FPGA Design :: 31.03.2011 00:33 :: vipinlal :: Replies: 4 :: Views: 1632
I want to implement FFT on fpga..
i am using the approach of Microblaze processor...
A to D converter will give the sine function in digital form to the fpga kit then this sine wave will be sent for FFT and after FFT the result ll be sent to LCD for display.
all this management ll be done by Microblaze processor...
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.04.2010 01:31 :: kajulkumar :: Replies: 8 :: Views: 2135
you can use ad9851 for sine wave generator and you can generate sine and triangle with that
Analog Circuit Design :: 24.05.2010 22:08 :: rajudp :: Replies: 9 :: Views: 3138
The frequency of your sinewave depends on 2 things, the first is the number of sample your VHDL is generating for each cycle and the second one is the frequency of the clock that writes to the DAC.
Say, you have 256 steps for your sine wave, and your clock frequency is 25.6 MHz, you will get a sinewave signals that is 100 KHz.
PLD, SPLD, GAL, CPLD, FPGA Design :: 18.06.2010 07:50 :: farhada :: Replies: 3 :: Views: 1908
Why don't you sent a pn sequence?
May be an option, the original poster should clarify the requirements. I was already wondering what's the purpose of a "combination of three sine waves".
I guess it's a small band (e.g. US) transducer, having a sine burst as impulse response anyway. And the intention is to achieve a time resoluti
Digital Signal Processing :: 11.08.2010 08:44 :: FvM :: Replies: 4 :: Views: 1303
I'm under the impression, that the DDS IP documentations have good explanations of it's basic operation, it's at least the case for the Altera DDS core.
It's very easy anyway. Simply consider an accumulator of any length, e.g. 32 bit. The frequency value is added each clock cycle, the accumulator is representing the signal phase. An overflow me
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.11.2010 10:58 :: FvM :: Replies: 1 :: Views: 1079
I want to implement BPSK modulator and demodulator in verilog on spartan 3 kit.
If anyone has done that on any fpga, i request your guidance...
I know the concept that for transmitting '0', we send the sinusoid as it is and for '1' we add 180 phase shift to the sinusoid.
I request guidance on following points
- BPSK modulator, demodulator b
PLD, SPLD, GAL, CPLD, FPGA Design :: 09.11.2010 23:28 :: devashishraval :: Replies: 2 :: Views: 2076
Is it (if is then how) possible to generate sine wave with frequency lets say 15kHz and 20kHz having only CLK of 48kHz ? Im asking because I wanted to generate this type of a signal and send it through I2S to the AC97 codec on my board and connect it to PC and see signal and its spectrum in SpectraLAB (or any other program which has FFT opti
PLD, SPLD, GAL, CPLD, FPGA Design :: 26.01.2011 17:47 :: Dave_PL :: Replies: 4 :: Views: 1255
Hi, I was asked to figure this out at work and I need some help!
I have a LVDT (Linear Variable Differential Tranformer) that spits out sine waves at 2 KHz, and I want to sample those sine waves 20 times per cycle (sample rate = 40 KHz?). Eventually those sampled rms values will be used for calculating addition, subtraction, divisions and CRCs
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.02.2011 11:57 :: Yihan :: Replies: 1 :: Views: 448
pls help, i m doing my final year project.. which is a (8bit) VHDL model of three phase PWM. i have written vhdl code for the PWM. in the embedded design, i need to write a c-program to generate 3 phase sine waves to the port 1 of the TSK51a microprocessor that will communicate with the vHDL model. (also considering an interrupt on port3_3 of the
PLD, SPLD, GAL, CPLD, FPGA Design :: 11.02.2011 19:31 :: ls3ar :: Replies: 0 :: Views: 450
hi dear all...
I have a vector consist of sine and cosine valus (A complex exponential) in MATLAB. How to generate a look-up table with this values in verilog?
I know that should be use a block-RAM, but I don't know how to write verilog code. please help me.
the values placed in a 4096×1 vector in MATLAB. I think a 4K RAM should be used, is it
PLD, SPLD, GAL, CPLD, FPGA Design :: 22.02.2011 06:27 :: Amir.B :: Replies: 6 :: Views: 1497
I'm doing a project on BPSK and DPCM. I have used LMS algorithm for the predictor and all the values I defined are in real. But I found that computation in real especially multiplication is taking too long. I want to convert real values to fixed point binary in the format for example 110.1011. How do I achieve
Digital Signal Processing :: 15.03.2011 14:51 :: pavankumarl73 :: Replies: 1 :: Views: 827
but are passive LC circuits gonna provide accurate output SUCH HIGH FREQUENCIES? Also, you said I/O delay of any pin would provide the delay, so how can I use this feature of a digital IC.
---------- Post added at 08:39 ---------- Previous post was at 08:38 ----------
Kalyanasv: sorry I did not mention about
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.08.2011 23:09 :: gmish27 :: Replies: 12 :: Views: 1423
for a simple square wave, it like a clock. You need just a counter in your vhdl code. But for sine wave i think you need A/D Hardware.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04.09.2011 21:38 :: BuBEE :: Replies: 3 :: Views: 1715
For sine and cosine you only need a quarter of full function period. Just look at sine wave period and you can get it why. This is also why you don't need separate tables for sine and cosine. Also tangent is sin(x)/cos(x), but i don't know wheter this can be useful. Also you don't need that many points in (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.10.2011 20:11 :: poorchava :: Replies: 6 :: Views: 1609
It's far from obvious how you achhieved a variable frequency oscillator with a fpga. In any case, you should check if the base band signal is a clean sine. Apart from modulation signal quality, it may be also a problem introcduced by your PWM modulator. What's the numerical resolution of the PWM setpoint, what's exactly the implemented PWM scheme?
Power Electronics :: 26.11.2011 07:09 :: FvM :: Replies: 10 :: Views: 1231
There have been various threads about different sine generation methods in fpgas. Larger look-up tables (LUT) are usually implemented in internal ROM blocks (initialized RAM) as they are provided by most recent fpga series. The sine function table can be loaded from a file, explicitely coded in a case structure (long winded) (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 01.12.2011 15:40 :: FvM :: Replies: 1 :: Views: 1463
I had used Taylor series expansion to generate sine & cosine waves. You can select the no. of terms to give a accurate looking waveform in the simulator!
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.12.2011 08:15 :: dpaul :: Replies: 6 :: Views: 1887
I am generating 25MHz sine wave using DDS core. Simulation is working perfectly but hardware is not working. I am implementing simple DDS core. Can you please tell me what can be the possible reason?
PLD, SPLD, GAL, CPLD, FPGA Design :: 28.03.2012 16:22 :: capcas :: Replies: 21 :: Views: 2945
I am an electrical engineering student and working on the speed control of PMSM motor using fpga kit SPARTAN 3E. I need sine wave generator code for 2-3 phase converter application
ia = sin θ. iq
ib = sin (θ-2Π/3). iq
ic = sin (θ+ 2Π/3). iq
iq= 8 bit input and θ is also a 8 bit input
ia,ib,ic are all 8 bit
PLD, SPLD, GAL, CPLD, FPGA Design :: 31.03.2012 15:21 :: mohit1108 :: Replies: 1 :: Views: 790
First of all, you can't produce a 1GHz sinewave with a 1 G-SAMPLE/sec DAC. That's SAMPLES/SEC, not CYCLES/SEC.
Second, the waveform you store in RAM doesn't have any 'frequency' associated with it; it's a sine wave, that's it.
But , yes, you will get unwanted frequencies in your output. Could you ask a more specific question?
Digital Signal Processing :: 19.07.2012 13:02 :: barry :: Replies: 3 :: Views: 431
as still I am beginner in Verilog, I found some codes for the trigonometric functions as follows:
function real sin;
sign = 1.0;
x1 = x;
x1 = -x1;
sign = -1.0;
while (x1 > 3.14159265/2.0)
PLD, SPLD, GAL, CPLD, FPGA Design :: 10.09.2012 16:14 :: Aya2002 :: Replies: 13 :: Views: 1182
those equation alone enough to design nco in verilog???
I guess, you are referring to the description of NCO operation in IP core manual?
A NCO is comprised of a phase accumulator, a sine table respectively generator algorithm and optionally modulation means. These are essentially simple operations and can be coded from the scr
PLD, SPLD, GAL, CPLD, FPGA Design :: 21.12.2012 02:04 :: FvM :: Replies: 9 :: Views: 862
10 Bit phase and magnitude resolution is a reasonable range for medium quality NCOs, e.g. used with sine inverters or active front ends. For test and mesurement 16 bit or better can be appropriate.
The exact relation between phase/magnitude resolution and analog performance, e.g. SFDR (spurious free dynamic range) is a rather complex numerical p
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.01.2013 04:53 :: FvM :: Replies: 6 :: Views: 890
Hi to all,
I need to generate in the fpga a very precise sine wave. The frequency of the sinewave is constant while the Amplitude and the Phase change.
The aim is not to utilize the sinewave to drive a DAC but instead to use it for signal processing inside the fpga.
Now... an example: I have a 2.5 (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.02.2013 14:59 :: kitepassion :: Replies: 3 :: Views: 377
At this link:
you will find intersting stuff on cordic and fpga.
This is a a doc on " fpga Implementation of sine and Cosine Generators Using the CORDIC..."
Digital Signal Processing :: 12.04.2004 12:10 :: redsk_y :: Replies: 8 :: Views: 5565
it is easy to understand calculating sine, cosine and arctan by using cordic,
but how can i calculate square root by using this algrithm
ASIC Design Methodologies and Tools (Digital) :: 12.11.2004 11:14 :: JesseKing :: Replies: 1 :: Views: 2261
In a digital circuit board design, the high speed global clock may be from a TCXO or others. The output of the TCXO is sine wave sometimes. we must transform the sine wave to a square wave in order to clock some digital device, for example, fpga or DSP.
We can use a zero crossing comparator to accomplish the process. With dual supply (...)
Analog Circuit Design :: 01.04.2005 11:33 :: ddt694 :: Replies: 10 :: Views: 3363
It's too bad that Verilog provides poor support for initializing anything. Both ISE and ModelSim support block RAM initialization, but they use different syntax, so you have to put both formats into your Verilog. And it's ugly syntax!
Here is a 1Kx18 dual-port ROM initialized with a sine table. I use both ports so I can read sine and (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 25.04.2005 00:42 :: echo47 :: Replies: 5 :: Views: 1029
LUTs in the fpgas can be used only for Digital Computations.
For handling sine functions there is a algorithm called CORDIC which stands for CO-ordinate Rotation for Digital Computing.
This algorithm is used in DDFS- Direct Digital Frequency Synthezisers for the generation of sin wave and i have read that it is also used in Calculators for s
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.11.2005 06:09 :: veejaye :: Replies: 1 :: Views: 694
i guess that is possible once u use square waves instead of sines. u can obtains PWM... I have done that once..
u need timer circuits to do that.... in case your objectives can be met in that case it was so.
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.01.2006 13:21 :: eda_freak :: Replies: 6 :: Views: 2068
12 bit resolution, which is 4096 points and multimeter?? No way man. You need to actually use a high resolution current meters or else, you can actually use an external amplifier stage of atleast a gain of 4, on the PCB in order to get the effective measured resolution to 10 bits. Then you can use a multimeter.
For SFDR, you need to model a sine
Analog Circuit Design :: 24.04.2006 06:21 :: Vamsi Mocherla :: Replies: 3 :: Views: 820
One chip costs a little more then 1w,I am a beginner of designing with fpga .
when design PowerPC,whether in the EDK enviroment can we acommplish it.
This afternoon,I try to double the 100MHz crystal,The output frequecy is 200MHz,But the wave isn't square or like sine,The high level is a peak, the low level lasting 80% of the period.can it do fo
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.05.2006 06:54 :: shoufeng_luo :: Replies: 6 :: Views: 754