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How can calculate the sine and consine function by using fpga or VHDL code? For synopsys users: If you have the DesignWare Foundation Library (dw_2) licensed, you can use the DW02_sincos model. see attached file.
OK! sine and cosine generation is an old problem, usually solved using look up tables, specially when the frequency of sine and cosine waves are fixed. if the frequency is variable and you should compute a different sine or cosine value each time, then you should compute it and as our (...)
I am required to implement a sine wave generator and frequence range is 0.005hz to 5000hz. Given the clock is 100mhz, the problem is whether DDS can generator this frequence range sine wave. If it can, how many bits have the phase acc as well as how long sine table(a whole period) Is there someone tell me how to computate these (...)
Hi DDS souce code. Best Regards Architecture DDS_arch of DDS is subtype WAVE is STD_LOGIC_VECTOR (5 downto 0); type ROM is array (0 to 63) of WAVE; constant sine : ROM := ( "100000","100011","100110","101000","101011","101110","110001","110011", "110101","110111","111001","111011","111100","111101","111110","111110",
Try these..
Hi, I created a RRC filter for an fpga using ONEoverT from Tyder. The VHDL was created fine as well as all the test data and modelsim compile macro. However, when I simulate the design, I expect to see a sine wave at the output, but I don't. I see output values however, but the it is not in an analog format. The documents with the software s
You might also google 'magic sinewaves"
Hi all I am trying to make an fpga produce from its IO pins pulses with duty cycle 50%. The frequency of the pulse must be able to change it from 1 Hz to 10-15 Mhz with a step 1 Hz. I have used accumulators to accomplish that. (Idea taken from DDS). I dont care to make the pulse waveform to a sine one so i dont use DAC or memory to write
i have to implement math functions in fpga. one way is to express sine function in term of its maclauran series. since in maclauran series we have to compute factorial,divide, add,subtract arithmatics to find sine function which is very lenthy. please tell me any other method to implement this.
I'm a newbie with fpga and looking for some help in my project. I have a signal which is a number of pulses of 100 kHz sine sampled at 1 MHz. The problem is that it is shadowed in a number (up to 10) of interfering continues wave signals at frequencies in 50-200 kHz band, and I want to suppress them. I decided to use a bank of 2nd order IIR no
Hi everybody, I got some problems during the implemenation of a simple delay generator on Stratix II. I realized a shift-register ram based with many taps, so I could select the desired delay for the circuit. After implementation I analyzed the behaviour giving a sine wave to adc of the evaluation board (ep2s60) and then viewing the samples sende
Hi, I'm currently in the process of developing a control scheme for a custom power device using fpga. The control scheme processes the error voltage through a PI controller whose output (PI output) is used to phase modulate the sinusoidal waveform (50 Hz). The phase modulated waveform is then compared against a triangular carrier wave to generate
Hi guys,I am new to Verilog and am writing a code for DDS .I want to know if there are code in Xilinx fpga Verilog for DDS.I wrote a very very simple code based on the Xilinx Coregen sine LookUpTable.I want to know if there is any other code using Advanced Interpolation Techniques.Here is the simple code I wrote module dds(CLK,WCLK,
Hello friends!, I'm using xilinx fpga. I need to multiply two input sine waves(from ADC) of same frequency and amplitude inorder to cancel the phase shifts and get double of it's frequency.(If you product 2 sine of same freq,it's freq inputs are 14-bit from ADC(unsigned integer from 0 to 16383)and output is to a 14-bit DAC. I tried mult
Hi guys, how to implement sine inverse in fpga.. please help me in doing this....
I agree with FvM, You can create a simple lookup table for 1/4th of your sinewave, then repeate it 4 times up and down to get the correct sinus output values. The size of the lookup table depends on your frequency. Take a look at this Xilinx App-note for some ideas on how to do it:
hi to all. i have a project in which I have to demodulate a fsk-modulated signal that comes from a adc which samples at 5mHzin fpga. to do that, I have to design two bandpass filters at 690 kHz and 710 kHz. Now I am trying to simulate it in matlab to make sure it works. this is my code: close all; %clear; % find the period of the transmitted sin
The below wiki link has some Matlab code: Gabor filter - Wikipedia, the free encyclopedia Not sure whether its the complete code. Possible difficulties during the VHDL implementation are: 1)Fixed point operation handling. 2) Calculating sine and cosine values, exponential values. 3)Large memory nee
I want to implement FFT on fpga.. i am using the approach of Microblaze processor... A to D converter will give the sine function in digital form to the fpga kit then this sine wave will be sent for FFT and after FFT the result ll be sent to LCD for display. all this management ll be done by Microblaze processor... is the
you can use ad9851 for sine wave generator and you can generate sine and triangle with that
The frequency of your sinewave depends on 2 things, the first is the number of sample your VHDL is generating for each cycle and the second one is the frequency of the clock that writes to the DAC. Say, you have 256 steps for your sine wave, and your clock frequency is 25.6 MHz, you will get a sinewave signals that is 100 KHz.
Why don't you sent a pn sequence? May be an option, the original poster should clarify the requirements. I was already wondering what's the purpose of a "combination of three sine waves". I guess it's a small band (e.g. US) transducer, having a sine burst as impulse response anyway. And the intention is to achieve a time resoluti
I'm under the impression, that the DDS IP documentations have good explanations of it's basic operation, it's at least the case for the Altera DDS core. It's very easy anyway. Simply consider an accumulator of any length, e.g. 32 bit. The frequency value is added each clock cycle, the accumulator is representing the signal phase. An overflow me
I want to implement BPSK modulator and demodulator in verilog on spartan 3 kit. If anyone has done that on any fpga, i request your guidance... I know the concept that for transmitting '0', we send the sinusoid as it is and for '1' we add 180 phase shift to the sinusoid. I request guidance on following points - BPSK modulator, demodulator b
Hi, Is it (if is then how) possible to generate sine wave with frequency lets say 15kHz and 20kHz having only CLK of 48kHz ? Im asking because I wanted to generate this type of a signal and send it through I2S to the AC97 codec on my board and connect it to PC and see signal and its spectrum in SpectraLAB (or any other program which has FFT opti
Hi, I was asked to figure this out at work and I need some help! I have a LVDT (Linear Variable Differential Tranformer) that spits out sine waves at 2 KHz, and I want to sample those sine waves 20 times per cycle (sample rate = 40 KHz?). Eventually those sampled rms values will be used for calculating addition, subtraction, divisions and CRCs
pls help, i m doing my final year project.. which is a (8bit) VHDL model of three phase PWM. i have written vhdl code for the PWM. in the embedded design, i need to write a c-program to generate 3 phase sine waves to the port 1 of the TSK51a microprocessor that will communicate with the vHDL model. (also considering an interrupt on port3_3 of the
hi dear all... I have a vector consist of sine and cosine valus (A complex exponential) in MATLAB. How to generate a look-up table with this values in verilog? I know that should be use a block-RAM, but I don't know how to write verilog code. please help me. the values placed in a 4096×1 vector in MATLAB. I think a 4K RAM should be used, is it
Hello everyone, I'm doing a project on BPSK and DPCM. I have used LMS algorithm for the predictor and all the values I defined are in real. But I found that computation in real especially multiplication is taking too long. I want to convert real values to fixed point binary in the format for example 110.1011. How do I achieve
but I have to produce the phase difference between two sine waves oscillating at 1-3 GHz. The signal is analog So why do you think to use digital logic ICs? Also, you said I/O delay of any pin would provide the delay, so how can I use this feature of a digital IC. I said it's a multiple - and it will be very inacc
for a simple square wave, it like a clock. You need just a counter in your vhdl code. But for sine wave i think you need A/D Hardware.
For sine and cosine you only need a quarter of full function period. Just look at sine wave period and you can get it why. This is also why you don't need separate tables for sine and cosine. Also tangent is sin(x)/cos(x), but i don't know wheter this can be useful. Also you don't need that many points in (...)
Sir I made a Variable Frequency sine Wave Generator that can vary frequency from 90 to 150Hz, its running fine, but the problem is that the noise in sine wave gets pronounced in between the certain frequency band as can be seen in screen # 4, below & above that band there is less distortion, what I should do to suppress that noise??? [ATTACH
I am working on a final project for graduate school. I need to be able to calculate cos (x) and sin (x) in VHDL code. My professor tells me I should use a look up table for cos and sin values. I have never worked with look up tables in VHDL and I am a bit confused on how to do this in VHDL. Any suggestions? Example: cos (2) = -0.4161 (I n
I am very new to vlsi...... I want to generate a sine wave using vhdl. i stored all the samples in a rom and fetch one by one to generate main aim is to change the phase of the sine wave for 45,90 degrees...pls help
hello, am working on a project waveform generation using fpga , i did sine wave with 1k freq(verilog, vhdl) but now i required sine wave with freq. upto 400khz plz gimmi some tips.
I am an electrical engineering student and working on the speed control of PMSM motor using fpga kit SPARTAN 3E. I need sine wave generator code for 2-3 phase converter application ia = sin θ. iq ib = sin (θ-2Π/3). iq ic = sin (θ+ 2Π/3). iq iq= 8 bit input and θ is also a 8 bit input ia,ib,ic are all 8 bit
First of all, you can't produce a 1GHz sinewave with a 1 G-SAMPLE/sec DAC. That's SAMPLES/SEC, not CYCLES/SEC. Second, the waveform you store in RAM doesn't have any 'frequency' associated with it; it's a sine wave, that's it. But , yes, you will get unwanted frequencies in your output. Could you ask a more specific question? Also, Xilinx
as still I am beginner in Verilog, I found some codes for the trigonometric functions as follows: function real sin; input x; real x; real x1,y,y2,y3,y5,y7,sum,sign; begin sign = 1.0; x1 = x; if (x1<0) begin x1 = -x1; sign = -1.0; end while (x1 > 3.14159265/2.0)
those equation alone enough to design nco in verilog??? I guess, you are referring to the description of NCO operation in IP core manual? A NCO is comprised of a phase accumulator, a sine table respectively generator algorithm and optionally modulation means. These are essentially simple operations and can be coded from the scr
10 Bit phase and magnitude resolution is a reasonable range for medium quality NCOs, e.g. used with sine inverters or active front ends. For test and mesurement 16 bit or better can be appropriate. The exact relation between phase/magnitude resolution and analog performance, e.g. SFDR (spurious free dynamic range) is a rather complex numerical p
Hi to all, I need to generate in the fpga a very precise sine wave. The frequency of the sinewave is constant while the Amplitude and the Phase change. The aim is not to utilize the sinewave to drive a DAC but instead to use it for signal processing inside the fpga. Now... an example: I have a 2.5 (...)
At this link: you will find intersting stuff on cordic and fpga. This is a a doc on " fpga Implementation of sine and Cosine Generators Using the CORDIC..." Regards, --rs
it is easy to understand calculating sine, cosine and arctan by using cordic, but how can i calculate square root by using this algrithm thanks!!!!
In a digital circuit board design, the high speed global clock may be from a TCXO or others. The output of the TCXO is sine wave sometimes. we must transform the sine wave to a square wave in order to clock some digital device, for example, fpga or DSP. We can use a zero crossing comparator to accomplish the process. With dual supply (...)
It's too bad that Verilog provides poor support for initializing anything. Both ISE and ModelSim support block RAM initialization, but they use different syntax, so you have to put both formats into your Verilog. And it's ugly syntax! Here is a 1Kx18 dual-port ROM initialized with a sine table. I use both ports so I can read sine and (...)
LUTs in the fpgas can be used only for Digital Computations. For handling sine functions there is a algorithm called CORDIC which stands for CO-ordinate Rotation for Digital Computing. This algorithm is used in DDFS- Direct Digital Frequency Synthezisers for the generation of sin wave and i have read that it is also used in Calculators for s
i guess that is possible once u use square waves instead of sines. u can obtains PWM... I have done that once.. u need timer circuits to do that.... in case your objectives can be met in that case it was so.
12 bit resolution, which is 4096 points and multimeter?? No way man. You need to actually use a high resolution current meters or else, you can actually use an external amplifier stage of atleast a gain of 4, on the PCB in order to get the effective measured resolution to 10 bits. Then you can use a multimeter. For SFDR, you need to model a sine
One chip costs a little more then 1w,I am a beginner of designing with fpga . when design PowerPC,whether in the EDK enviroment can we acommplish it. This afternoon,I try to double the 100MHz crystal,The output frequecy is 200MHz,But the wave isn't square or like sine,The high level is a peak, the low level lasting 80% of the period.can it do fo