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46 Threads found on Sine Fpga
According to the wave window, the sine frequencies are not 1 MHz and 15 MHz. Apparently you still don't manage to scale ADD3 into FILTER_OUT, respectively to display the data with correct number format.
Hi, I am using altera IP core PLL with the setup shown in the image. 136648 When I check the waveform in the scope, I have got a sine wave of 2 vpp with a DC component of 1.5 v. The issue here is that am using that clock to sync with the Audio codec WM8731 for I2S communication but it seems that the codec is not un
Unless Hulk defines his requirements more clearly, clearly there is no solution. There are many applications that don't need a sine wave with 60 dB SNR or even 40dB for that matter.
Please help me out in resolving the issue with sine wave generation using DDS. How to generate 4 different sinusoidal signals with phase angles 0,90,180 and 270. How phase increment values are related to frequency. am designing my QPSK modulator for a clock frequency of 100 MHz. Do help me in sorting this problem. Thanks in advance
I am new in verilog but am getting used to it. My problem is how to store amplitude values of the sine wave. i am using a 14 bit resolution which means i have 2^14 no of values between 0 to 360 / 90 (doesn't matter) of sine. now the address will be linear but the corresponding sine amplitudes are nonlinear and theu have values like (...)
It may use Lookup tables which have the sine/cosine value in a ROM
How to generate sine waves by using a verilog code? Can anyone please explain in detail? I heard about the look up table but have no clue on how to implement on fpga? Can anyone post a sample code to help ? Thanks in advance
You could use a lookup table with just a quarter of the complete sine, or you could use linear interpolation for the same quarter. for the interpolation, you could save just the "m" and "b" parameters of the "y=mx+b" equation
Hi all! I tryed to calculate a value of sine and cosine functions using cordic algorithm. But it does not work in fixed point system and i wrote it as simple program. Here is a code: module cordic_test0( ); real cordic_iter; real angle; integer i = 0; real xi; real yi; real zi; initial begin cordic_iter = 4
i've tried the pwm methods suggested but they didn't work. Not very specific, I think. Provided you have a pwm code, you can test it with constant duty cycle first then connect the sine signal and check the output. Every step can be verified in functional simulation.
i need verilog code of sine wave generator....i tried with cordic algorithm but i cant able to proceed....plzzz help
Hi All, I got Bazinga'ed by the thing here. After tinkering around for the past 8 days on my fpga+ DAC to generate a sinewave. I am still stuck. Specs: 128 word deep ROM was used by me on VHDL Board: Nexsys2 DAC: LTC1668, 16-bit Data In and differential signal IoutA and IoutB code used: ---------------ROM module-----------
Hi to all, I need to generate in the fpga a very precise sine wave. The frequency of the sinewave is constant while the Amplitude and the Phase change. The aim is not to utilize the sinewave to drive a DAC but instead to use it for signal processing inside the fpga. Now... an example: I have a 2.5 (...)
those equation alone enough to design nco in verilog??? I guess, you are referring to the description of NCO operation in IP core manual? A NCO is comprised of a phase accumulator, a sine table respectively generator algorithm and optionally modulation means. These are essentially simple operations and can be coded from the scr
First of all, you can't produce a 1GHz sinewave with a 1 G-SAMPLE/sec DAC. That's SAMPLES/SEC, not CYCLES/SEC. Second, the waveform you store in RAM doesn't have any 'frequency' associated with it; it's a sine wave, that's it. But , yes, you will get unwanted frequencies in your output. Could you ask a more specific question? Also, Xilinx
I haven't worked on CPLD but I did work on Spartan3 fpga about a year ago. I tried to use Verilog HDL to make a simple sine calculator. I used the sine approximation formula (attached in image) to find out the sine of an angle being given by the user. But I fell into a number of problems regarding the variable type 'real' in (...)
Besides the said IP blocks of major fpga vendors, you'll find many code examples at edaboard. I know, that I posted at least one, demonstrating sine table generation in VHDL. Yes, look-up table (LUT) is the straightforward way, there are also other generation algorithms, particularly interesting for high resolution sine. I guess, that 8 (...)
Hi, I am generating 25MHz sine wave using DDS core. Simulation is working perfectly but hardware is not working. I am implementing simple DDS core. Can you please tell me what can be the possible reason?
There have been various threads about different sine generation methods in fpgas. Larger look-up tables (LUT) are usually implemented in internal ROM blocks (initialized RAM) as they are provided by most recent fpga series. The sine function table can be loaded from a file, explicitely coded in a case structure (long winded) (...)
It's far from obvious how you achhieved a variable frequency oscillator with a fpga. In any case, you should check if the base band signal is a clean sine. Apart from modulation signal quality, it may be also a problem introcduced by your PWM modulator. What's the numerical resolution of the PWM setpoint, what's exactly the implemented PWM scheme?
For sine and cosine you only need a quarter of full function period. Just look at sine wave period and you can get it why. This is also why you don't need separate tables for sine and cosine. Also tangent is sin(x)/cos(x), but i don't know wheter this can be useful. Also you don't need that many points in (...)
for a simple square wave, it like a clock. You need just a counter in your vhdl code. But for sine wave i think you need A/D Hardware.
Instead using Cordic generate sin wave with DDS. Then during input signal change change the phase of the sine wave by reading from different location. This works. I've done this. vhdl4u gmail com
hi dear all... I have a vector consist of sine and cosine valus (A complex exponential) in MATLAB. How to generate a look-up table with this values in verilog? I know that should be use a block-RAM, but I don't know how to write verilog code. please help me. the values placed in a 4096×1 vector in MATLAB. I think a 4K RAM should be used, is it
pls help, i m doing my final year project.. which is a (8bit) VHDL model of three phase PWM. i have written vhdl code for the PWM. in the embedded design, i need to write a c-program to generate 3 phase sine waves to the port 1 of the TSK51a microprocessor that will communicate with the vHDL model. (also considering an interrupt on port3_3 of the
Hi, Is it (if is then how) possible to generate sine wave with frequency lets say 15kHz and 20kHz having only CLK of 48kHz ? Im asking because I wanted to generate this type of a signal and send it through I2S to the AC97 codec on my board and connect it to PC and see signal and its spectrum in SpectraLAB (or any other program which has FFT opti
you can use ad9851 for sine wave generator and you can generate sine and triangle with that
I'm not aware of single chip sine PWM solutions (besides uP/DSP/fpga). Are there any?
make table of values of sine series ... now create a memory inside fpga and store this values to that memory and use where ever you need...
Hi guys, how to implement sine inverse in fpga.. please help me in doing this....
Hello friends!, I'm using xilinx fpga. I need to multiply two input sine waves(from ADC) of same frequency and amplitude inorder to cancel the phase shifts and get double of it's frequency.(If you product 2 sine of same freq,it's freq inputs are 14-bit from ADC(unsigned integer from 0 to 16383)and output is to a 14-bit DAC. I tried mult
I assume, that you'll use a LUT NCO. For full clock rate, you can utilize a dual port ROM to have sine ans cosine in parallel, for reduced clock rate, the ROM can be multiplexed.
Hi guys,I am new to Verilog and am writing a code for DDS .I want to know if there are code in Xilinx fpga Verilog for DDS.I wrote a very very simple code based on the Xilinx Coregen sine LookUpTable.I want to know if there is any other code using Advanced Interpolation Techniques.Here is the simple code I wrote module dds(CLK,WCLK,
Hi, I'm currently in the process of developing a control scheme for a custom power device using fpga. The control scheme processes the error voltage through a PI controller whose output (PI output) is used to phase modulate the sinusoidal waveform (50 Hz). The phase modulated waveform is then compared against a triangular carrier wave to generate
Hi friends!, I have an issue upon demodulating ASK waveform from my ADC...I have attached a pic that best describes all....I transmit the ASK modulated sine wave from DAC of my transmitter and receive it in ADC of my turn this peripherls will be connected to fpga(virtex 4). Here I have succesfull generated ASK and have transmitted and w
i have to implement math functions in fpga. one way is to express sine function in term of its maclauran series. since in maclauran series we have to compute factorial,divide, add,subtract arithmatics to find sine function which is very lenthy. please tell me any other method to implement this. use edatools coregen li
How to generate sine wave of perticular frequency by using Goertzel algorithm. and it's implementation details on fpga. Any body, plz help me. Thanx........
Hi, I created a RRC filter for an fpga using ONEoverT from Tyder. The VHDL was created fine as well as all the test data and modelsim compile macro. However, when I simulate the design, I expect to see a sine wave at the output, but I don't. I see output values however, but the it is not in an analog format. The documents with the software s
hello to all expert, im just a newbie in doing fpga.. i have a high interest on doing fpga project in my final year B(ENG).. Im about to do an Arithmetic operator such as simple DSP processor to filter out noise.. 2 input signal fed into ADC (5volt sine wave or sound + 3volt Noise) then it have one 8 bit adder to sum up 2 signal. (...)
Hi,Can you help me for something? I want to use the fpga interface for the dual-slope A/D converter using TC7109CPL my analog input is sine Wave signal so... How is design vhdl code to read the amplitute of sine signal? can you suggest me? thank you a lot!!
Hi DDS souce code. Best Regards Architecture DDS_arch of DDS is subtype WAVE is STD_LOGIC_VECTOR (5 downto 0); type ROM is array (0 to 63) of WAVE; constant sine : ROM := ( "100000","100011","100110","101000","101011","101110","110001","110011", "110101","110111","111001","111011","111100","111101","111110","111110",
I am required to implement a sine wave generator and frequence range is 0.005hz to 5000hz. Given the clock is 100mhz, the problem is whether DDS can generator this frequence range sine wave. If it can, how many bits have the phase acc as well as how long sine table(a whole period) Is there someone tell me how to computate these (...)
it is easy to understand calculating sine, cosine and arctan by using cordic, but how can i calculate square root by using this algrithm thanks!!!!
OK! sine and cosine generation is an old problem, usually solved using look up tables, specially when the frequency of sine and cosine waves are fixed. if the frequency is variable and you should compute a different sine or cosine value each time, then you should compute it and as our (...)
At this link: you will find intersting stuff on cordic and fpga. This is a a doc on " fpga Implementation of sine and Cosine Generators Using the CORDIC..." Regards, --rs
How can calculate the sine and consine function by using fpga or VHDL code? For synopsys users: If you have the DesignWare Foundation Library (dw_2) licensed, you can use the DW02_sincos model. see attached file.