1000 Threads found on edaboard.com: Sine Fpga
How can calculate the sine and consine function by using fpga or VHDL code?
For synopsys users:
If you have the DesignWare Foundation Library (dw_2) licensed, you can use the DW02_sincos model.
see attached file.
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-21-2003 05:46 :: gnomix :: Replies: 19 :: Views: 12384
Hello friends!, I'm using xilinx fpga. I need to multiply two input sine waves(from ADC) of same frequency and amplitude inorder to cancel the phase shifts and get double of it's frequency.(If you product 2 sine of same freq,it's freq inputs are 14-bit from ADC(unsigned integer from 0 to 16383)and output is to a 14-bit DAC. I tried mult
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-27-2008 04:28 :: xtcx :: Replies: 0 :: Views: 1513
how to implement sine inverse in fpga..
please help me in doing this....
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-29-2009 04:21 :: vinodkumar :: Replies: 2 :: Views: 807
am working on a project waveform generation using fpga , i did sine wave with 1k freq(verilog, vhdl) but now i required sine wave with freq. upto 400khz plz gimmi some tips.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-20-2012 01:47 :: Raviraj Sarje :: Replies: 21 :: Views: 3580
I would like to generate a sine wave on my fpga whose output would then be observed through a pmod dac with 2 12-bit d/a outputs. I tried using the dds available in xilinx but whenever i test the behavioural simulation, I end up with undefined signals.
Can someone provide me with a step by step guide on how to achieve this ? I've read a lot of
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-28-2014 03:19 :: Christian Chetcuti :: Replies: 4 :: Views: 310
OK! sine and cosine generation is an old problem, usually solved using look up tables, specially when the frequency of sine and cosine waves are fixed.
if the frequency is variable and you should compute a different sine or cosine value each time, then you should compute it and as our (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-02-2004 11:44 :: mami_hacky :: Replies: 5 :: Views: 2354
I am required to implement a sine wave generator and frequence range is
0.005hz to 5000hz. Given the clock is 100mhz, the problem is whether DDS can generator this frequence range sine wave. If it can, how many bits have the phase acc as well as how long sine table(a whole period)
Is there someone tell me how to computate these (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-27-2005 21:16 :: skycanny :: Replies: 8 :: Views: 1515
Electronic Elementary Questions :: 09-21-2005 03:16 :: dynamicdude :: Replies: 5 :: Views: 1472
I created a RRC filter for an fpga using ONEoverT from Tyder. The VHDL was created fine as well as all the test data and modelsim compile macro. However, when I simulate the design, I expect to see a sine wave at the output, but I don't.
I see output values however, but the it is not in an analog format.
The documents with the software s
Digital Signal Processing :: 11-08-2006 07:28 :: alanmck :: Replies: 0 :: Views: 688
You might also google 'magic sinewaves"
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-21-2007 00:27 :: cherrytart :: Replies: 8 :: Views: 3070
I am trying to make an fpga produce from its IO pins pulses with duty cycle 50%.
The frequency of the pulse must be able to change it from 1 Hz to 10-15 Mhz with a
step 1 Hz.
I have used accumulators to accomplish that. (Idea taken from DDS). I dont care to
make the pulse waveform to a sine one so i dont use DAC or memory to write
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-06-2007 13:05 :: blitzwing :: Replies: 1 :: Views: 1542
i have to implement math functions in fpga.
one way is to express sine function in term of its maclauran series. since in maclauran series we have to compute factorial,divide, add,subtract arithmatics to find sine function which is very lenthy.
please tell me any other method to implement this.
use edatools coregen li
ASIC Design Methodologies and Tools (Digital) :: 10-25-2007 08:55 :: supercst :: Replies: 5 :: Views: 1115
I'm a newbie with fpga and looking for some help in my project.
I have a signal which is a number of pulses of 100 kHz sine sampled at
1 MHz. The problem is that it is shadowed in a number (up to 10) of
interfering continues wave signals at frequencies in 50-200 kHz band,
and I want to suppress them. I decided to use a bank of 2nd order IIR
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-25-2007 05:09 :: Unomano :: Replies: 1 :: Views: 755
I'm currently in the process of developing a control scheme for a custom power device using fpga. The control scheme processes the error voltage through a PI controller whose output (PI output) is used to phase modulate the sinusoidal waveform (50 Hz). The phase modulated waveform is then compared against a triangular carrier wave to generate
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-08-2008 03:26 :: rjai_pradha :: Replies: 0 :: Views: 1245
Hi guys,I am new to Verilog and am writing a code for DDS .I want to know if there are code in Xilinx fpga Verilog for DDS.I wrote a very very simple code based on the Xilinx Coregen sine LookUpTable.I want to know if there is any other code using Advanced Interpolation Techniques.Here is the simple code I wrote
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-18-2008 10:38 :: maheshkuruganti :: Replies: 0 :: Views: 5203
I agree with FvM,
You can create a simple lookup table for 1/4th of your sinewave, then repeate it 4 times up and down to get the correct sinus output values.
The size of the lookup table depends on your frequency.
Take a look at this Xilinx App-note for some ideas on how to do it:
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-28-2009 04:04 :: farhada :: Replies: 4 :: Views: 1778
hi to all. i have a project in which I have to demodulate a fsk-modulated signal that comes from a adc which samples at 5mHzin fpga. to do that, I have to design two bandpass filters at 690 kHz and 710 kHz. Now I am trying to simulate it in matlab to make sure it works. this is my code:
% find the period of the transmitted sin
Digital Signal Processing :: 12-28-2009 17:22 :: fena :: Replies: 0 :: Views: 1073
The below wiki link has some Matlab code:
Gabor filter - Wikipedia, the free encyclopedia
Not sure whether its the complete code.
Possible difficulties during the VHDL implementation are:
1)Fixed point operation handling.
2) Calculating sine and cosine values, exponential values.
3)Large memory nee
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-31-2011 00:33 :: vipinlal :: Replies: 4 :: Views: 1790
I want to implement FFT on fpga..
i am using the approach of Microblaze processor...
A to D converter will give the sine function in digital form to the fpga kit then this sine wave will be sent for FFT and after FFT the result ll be sent to LCD for display.
all this management ll be done by Microblaze processor...
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-19-2010 01:31 :: kajulkumar :: Replies: 8 :: Views: 2277
you can use ad9851 for sine wave generator and you can generate sine and triangle with that
Analog Circuit Design :: 05-24-2010 22:08 :: rajudp :: Replies: 9 :: Views: 3261
The frequency of your sinewave depends on 2 things, the first is the number of sample your VHDL is generating for each cycle and the second one is the frequency of the clock that writes to the DAC.
Say, you have 256 steps for your sine wave, and your clock frequency is 25.6 MHz, you will get a sinewave signals that is 100 KHz.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-18-2010 07:50 :: farhada :: Replies: 3 :: Views: 2043
Why don't you sent a pn sequence?
May be an option, the original poster should clarify the requirements. I was already wondering what's the purpose of a "combination of three sine waves".
I guess it's a small band (e.g. US) transducer, having a sine burst as impulse response anyway. And the intention is to achieve a time resoluti
Digital Signal Processing :: 08-11-2010 08:44 :: FvM :: Replies: 4 :: Views: 1396
I want to implement BPSK modulator and demodulator in verilog on spartan 3 kit.
If anyone has done that on any fpga, i request your guidance...
I know the concept that for transmitting '0', we send the sinusoid as it is and for '1' we add 180 phase shift to the sinusoid.
I request guidance on following points
- BPSK modulator, demodulator b
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-09-2010 23:28 :: devashishraval :: Replies: 2 :: Views: 2258
Is it (if is then how) possible to generate sine wave with frequency lets say 15kHz and 20kHz having only CLK of 48kHz ? Im asking because I wanted to generate this type of a signal and send it through I2S to the AC97 codec on my board and connect it to PC and see signal and its spectrum in SpectraLAB (or any other program which has FFT opti
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-26-2011 17:47 :: Dave_PL :: Replies: 4 :: Views: 1371
Hi, I was asked to figure this out at work and I need some help!
I have a LVDT (Linear Variable Differential Tranformer) that spits out sine waves at 2 KHz, and I want to sample those sine waves 20 times per cycle (sample rate = 40 KHz?). Eventually those sampled rms values will be used for calculating addition, subtraction, divisions and CRCs
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-03-2011 11:57 :: Yihan :: Replies: 1 :: Views: 490
hi dear all...
I have a vector consist of sine and cosine valus (A complex exponential) in MATLAB. How to generate a look-up table with this values in verilog?
I know that should be use a block-RAM, but I don't know how to write verilog code. please help me.
the values placed in a 4096×1 vector in MATLAB. I think a 4K RAM should be used, is it
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-22-2011 06:27 :: Amir.B :: Replies: 6 :: Views: 1648
I'm doing a project on BPSK and DPCM. I have used LMS algorithm for the predictor and all the values I defined are in real. But I found that computation in real especially multiplication is taking too long. I want to convert real values to fixed point binary in the format for example 110.1011. How do I achieve
Digital Signal Processing :: 03-15-2011 14:51 :: pavankumarl73 :: Replies: 1 :: Views: 890
but I have to produce the phase difference between two sine waves oscillating at 1-3 GHz. The signal is analog
So why do you think to use digital logic ICs?
Also, you said I/O delay of any pin would provide the delay, so how can I use this feature of a digital IC.
I said it's a multiple - and it will be very inacc
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-06-2011 04:27 :: FvM :: Replies: 12 :: Views: 1590
for a simple square wave, it like a clock. You need just a counter in your vhdl code. But for sine wave i think you need A/D Hardware.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-04-2011 21:38 :: BuBEE :: Replies: 3 :: Views: 1866
For sine and cosine you only need a quarter of full function period. Just look at sine wave period and you can get it why. This is also why you don't need separate tables for sine and cosine. Also tangent is sin(x)/cos(x), but i don't know wheter this can be useful. Also you don't need that many points in (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-01-2011 20:11 :: poorchava :: Replies: 6 :: Views: 1781
I made a Variable Frequency sine Wave Generator that can vary frequency from 90 to 150Hz, its running fine, but the problem is that the noise in sine wave gets pronounced in between the certain frequency band as can be seen in screen # 4, below & above that band there is less distortion, what I should do to suppress that noise???
Power Electronics :: 11-26-2011 01:16 :: FMradio :: Replies: 10 :: Views: 1322
I am working on a final project for graduate school. I need to be able to calculate cos (x) and sin (x) in VHDL code. My professor tells me I should use a look up table for cos and sin values. I have never worked with look up tables in VHDL and I am a bit confused on how to do this in VHDL. Any suggestions?
cos (2) = -0.4161 (I n
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-01-2011 15:14 :: jerryt :: Replies: 1 :: Views: 1657
I am very new to vlsi......
I want to generate a sine wave using vhdl.
i stored all the samples in a rom and fetch one by one to generate main aim is to change the phase of the sine wave for 45,90 degrees...pls help
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-05-2011 01:35 :: matt2011 :: Replies: 6 :: Views: 2114
I am an electrical engineering student and working on the speed control of PMSM motor using fpga kit SPARTAN 3E. I need sine wave generator code for 2-3 phase converter application
ia = sin θ. iq
ib = sin (θ-2Π/3). iq
ic = sin (θ+ 2Π/3). iq
iq= 8 bit input and θ is also a 8 bit input
ia,ib,ic are all 8 bit
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-31-2012 15:21 :: mohit1108 :: Replies: 1 :: Views: 903
those equation alone enough to design nco in verilog???
I guess, you are referring to the description of NCO operation in IP core manual?
A NCO is comprised of a phase accumulator, a sine table respectively generator algorithm and optionally modulation means. These are essentially simple operations and can be coded from the scr
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-21-2012 02:04 :: FvM :: Replies: 9 :: Views: 972
Hi to all,
I need to generate in the fpga a very precise sine wave. The frequency of the sinewave is constant while the Amplitude and the Phase change.
The aim is not to utilize the sinewave to drive a DAC but instead to use it for signal processing inside the fpga.
Now... an example: I have a 2.5 (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-16-2013 14:59 :: kitepassion :: Replies: 3 :: Views: 491
i've tried the pwm methods suggested but they didn't work.
Not very specific, I think. Provided you have a pwm code, you can test it with constant duty cycle first then connect the sine signal and check the output. Every step can be verified in functional simulation.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-06-2014 08:55 :: FvM :: Replies: 12 :: Views: 758
I tryed to calculate a value of sine and cosine functions using cordic algorithm. But it does not work in fixed point system and i wrote it as simple program.
Here is a code:
integer i = 0;
cordic_iter = 4
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-27-2014 11:05 :: brainiac_rus :: Replies: 4 :: Views: 266
How to generate sine waves by using a verilog code? Can anyone please explain in detail? I heard about the look up table but have no clue on how to implement on fpga? Can anyone post a sample code to help ?
Thanks in advance
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-20-2014 21:14 :: keerthna :: Replies: 8 :: Views: 459
sine wave is analog in nature. And fpga can read only digital values. So how will IP cores generate sine waves? I didnt get the actual meaning here. Can anyone please explain
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-03-2014 09:21 :: keerthna :: Replies: 5 :: Views: 519
I am not familiar with ASIC design flow, maybe somebody else can give some valuable comments....
For fpga design, what I have used synthesis tools(only to synthesis VHDL code): Synplicity Synplify > Synopsys fpga Compiler II > Mentor Leonardo Exemplar
It is only my personal opinion...
Professional Hardware and Electronics Design :: 07-13-2001 17:19 :: :: Replies: 7 :: Views: 3673
In the next months i have to migrate a fpga VirtexII VHDL design (near to million gates) to ASIC.
In the original design i use a classic fpga flow using as main tools Synplify+Amplfy+Modelsim, but i think boundary conditions,timing constraints and layout (even synthesis) in ASIC will be very different and other flow and considerations will be us
ASIC Design Methodologies and Tools (Digital) :: 01-30-2002 05:09 :: hwswboy :: Replies: 21 :: Views: 7473
Here is a very good link of publications on various fpga Technologies by Dr.Jonathan Rose.Njoy the great stuff.....
"Talent does what it can; genius does what it must."
- Edward George Bulwer-Lytton (1803-1873)
ASIC Design Methodologies and Tools (Digital) :: 03-03-2002 03:46 :: satya :: Replies: 6 :: Views: 2549
fpga CPU Links
1. -> t
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-09-2002 08:46 :: jimjim2k :: Replies: 1 :: Views: 2106
The practical Xilinx Designer Lab book by "Dave Van den Bout" from prentice hall is a very good starting point for beginners in fpga field. In this book two proto boards from XESS Corporation are described with schematics etc. - XS40 board for Xilinx fpga XC4005XL and XS95 for Xilinx XC95108 CPLD. The s/w for this boards are free and can be downed
Professional Hardware and Electronics Design :: 03-24-2002 03:29 :: siraj :: Replies: 4 :: Views: 1539
I want to built a test evulation board for fpga from xilinx
the idea is to built this simple JTAG Programmer
in a test board and use IMpact software to download the code .
IMpact software are integ
ASIC Design Methodologies and Tools (Digital) :: 04-11-2002 09:34 :: Celtadevigo :: Replies: 1 :: Views: 2131
How to convert the fpga to asic quickly, smoothly, and efficiently?
Thx in advance.
ASIC Design Methodologies and Tools (Digital) :: 05-12-2002 02:46 :: whatever :: Replies: 12 :: Views: 1781
Anybody know of a good application note or enginners note for porting an existing ASIC netlist to xilinx fpga? :o
ASIC Design Methodologies and Tools (Digital) :: 05-12-2002 11:05 :: rakko :: Replies: 4 :: Views: 1947
I am not sure if this link has been posted already, but another fpga and ASIC course can be found
ASIC Design Methodologies and Tools (Digital) :: 05-30-2002 21:13 :: Sarnouk :: Replies: 6 :: Views: 1882
Hi, can anyone give me some good references/links/books for information on designing systems that consist of a CPU core, with functionality implemented around the CPU (such as ethernet controller, hard disc controller), that are implemented on an fpga.
I am unsure of the number of macrocells a typical fpga has, and the macrocells required to imp
Microcontrollers :: 06-19-2002 13:05 :: O-Dog :: Replies: 3 :: Views: 2652