Search Engine

Single Cycle Processor

Add Question

1000 Threads found on Single Cycle Processor
i am doing an assignment to design a MIPS single cycle processor ,i am doing instruction memory and data memory.may i know what is the functionality and operation of memory ?can anybody help me on this ?
i have a single cycle processor desging code bu nw i have to modify it for Load upper immidiate instruction (lui) shift logic left and shift logic right. i have a pic of that new hardware but not understand how to modify my code. i have the codee of simple single cycle processor. if there (...)
can anybody help out the function table of register file in single mips
i am working with the single mips cycle processor data memory part ,and i am facing problem with the verilog of data memory is my code ... // Data memory // It doesn't have a memory read output module DM(dataread,clock,memwrite,addr,datawrite); input addr,datawrite; input clock, memwrite; output dataread; reg [3
Hi everyone I'm working on converting a single cycle MIPS processor I wrote in Verilog HDL into a Pipelined MIPS processor. I'd just like some detailed guidance, programmatically speaking, about how I should go about this. I understand the main difference between the single (...)
i need the code of multi cycle processor in verilog code. i have single cycle processor code but don't know how to modify it...?
alsalm 3alikom i have a problem to write a verilog code of single cycle in mips processor if anyone can help me to write it its very important plz thank u
How to realize a Read- modify -write in single cycle using a Dual Port RAM?
single cycle- all operations (fetcf,decode,execute,writeback..)are performed in a single clock cycle. Multicycle refers to pipelined datapath where all the above operations are performed in multiple clock cycles. Read Patterson's computer arcchitecture book for more details
Dear Friends how can we measure mains voltage on single cycle(20ms) Micro_brain
I have a chunk of combo logic (synthesizable netlist) where the shortest path is 1 ns and longest path is 7 ns. My clock is 5 ns but I need single cycle throughput. If I were to pump input every clk and capture 2 cycles later at every cycle, the shortest path will have a problem, and longest path may have problem in best (...)
Hello everyone, Can antone please help me in understanding this instruction logic of the single cycle processor. I am confused at some points. what's the input to the program counter? The output to the program counter is going to the instruction memory. But I am confused about the input stage. I read the theories from the book by David A. (...)
anybody have verilog code for data memory in single cycle processor mips ?i need it badly ...assignment pls help
can anybody explain on how this data memory code work on in this single cycle mips ?
write a c program to execute x/2^y in single clock cycle
hey everyone i need help finding the solution to the single-cycle and muti-cycle MIPS processor using VHDL code. i've worked on it for 5 days now and no luck. someone help me if they can find me some VHDL files. see ya
All, Is there any scheme at all in which it is possible to synchronize a single-bit data signal with an asynchronous clock signal in one cycle of that clock? Rgrds animotion
hey , i hav made my single cycle mips code in verilog HDL now i hav 2 check my processor for results...can u plz help me out abt what are the steps now ? n simulation tools required ...i don't know how 2 write assembly code 4 it plz. do provide some examples ...thanx
All of the three options are correct. Internal register width, determines number of bits a processor is capable of handing at a time. Register width in turn dictates data bus width, and number of bits ALU can process in single go. 8-bit processor can very well process 16 & 32-bit data, but not necessarily in a single (...)
oh thank u :-) but sir ....still i am in confusion , that DDR3 1033 ...wat is that number in front of ddr3 and single core means only one processor having XGhz of speed and dual core means 2XGhz ?
Hi I need to decide which CEVA DSP processor to use to incorporate in a digital hearing aid But I am not sure how to choose the right one seems to be the most popular one for hearing aids and it is the only one listed in the website that
Hello, I am trying to implement a single cycle MIPS processor. I've been able to execute the dual level controller but there seems to be some error with the datapath. Can someone please see and tell me what the error is. I used a test output signal called test_pc to check if the value from pc is correct or not. Initially 0's and then (...)
SL11IDE USB t IDE single chip processor
if u have a big combinational logic in ur design which will never run at ur required frequency... u have 2 options 1)Add pipeline stage(s) to divide the logic into single-cycle paths 2. Ease off the single-cycle requirement: allow more clock cycles using set_multicycle_path command. (...)
Hi, I would look at least at three different companies about 8051. If you need the fastest and best analog features, look at Silabs. They have a great variety with some exceptional features, outperforming any other 8-bit architecture I know with 100 MHz single cycle devices. If you need more "standard parts" and top performance is not as imp
Dear vikas_lakhanpal27, Multi cycle path must be configured during synthesis, to ensure synthesis tool doesnot try to optimise the path into a single clk cycle. Multi cycle path needs timimg analyse its a need and must. it must be optimised santu
There are many Harvard microcontrollers, DSPs are mostly Harvard, but the key advantages of DSP are: - most instuctions are single cycle, and 16 or 32 bit devices; - supports special instructions for signal processing: multiplications, multiply and accumulate the result (MAC) in 1 cycle, data adjusting, representation conversion; - (...)
Who can modify the HDL code for the single-cycle MIPS processor to handle SRA(shift right arithmetic)...?? ------------------------------------------------------------ -- mips.vhd -- and 30 May 2006 -- single cycle MIPS processor -----------------------------------------
As far I know I don't think that you could find a faster way to test the status of a I/O line using a commercial CPU: usually the status of processor's IO line is mapped to a specific bit in one (or more depending on the IO pin count) CPU register. So I suppose that 2 clock cycles are the minimum overhead you could expect to acquire this informatio
Hi I need a implementation datapath and controller for MIPS instructions(R-type and I-type instructions) in single cycle with verilog code,can u help me ?
plz any one help to modify the MIPS single cycle processor for lui and shift instructions. or any one have any link related to that.
MCP's are driven by Design, not by tools. By protocol, if design want to meet in single cycle and if tool is unable to meet the constraint, you cant put straight away the MCP to 2 or more. Below are the scenarios : 1. When you multi clock designs , like div by 2. you can meet some times in single clock cycle. Need to (...)
Hi everyone. I have a college work where I have to use a VHDL file that was given to me. But whoever made this file used std_logic_arith. So I went and converted it to numeric_std. So far so good, but now I had to add some content, and it's failing to work. I have to use the SLL operator with std_logic_vector. I know it's not ideal, but it wo
I have watched the book "Computer Organization And Design", and i want to implement a simple single clock mips(chapter 4.4) in my altera fpga board. Here is the problem i encountered: the altera fpga sram read the address at the rising edge and gives the valid data the next clock rising edge. that seems make the single clock implementation impossi
The flop to save the CSN could be generated in the same time as the address generation, not at memory level, but at the bus level. Dependand of the address mapping usage, you could used the MSB bit has direct chip select. RAM0:0x1xxxYYYY RAM1:0x2xxxYYYY RAM2:0x4xxxYYYY A single bit MSB is used for the CS, and the 16bits-LSB for address.
Getting MP3 decoding going on a Xilinx may be quite difficult. Have you thought of using a dedicated decoder chip such as the MAS35xx series? ( ) You will also need to have some sort of CPU to string this all together again the opencores site have a few! An alternative could be to use the LEON sparc core ( www.g
Hi, May someone post the professional hardware setting for Laker-linux in your company? For example: 1. Brand of Mother board 2. CPU(Intel? or AMD?, speed??, single/Dual processor?) 3. Memory(DDR? or RDRAM? , w/ or wo/ ECC?, 512M/1G/2G??) 4. Brand/model of Graphics card, how many video memory? 5. What kind of mouse for better drawing
Hi, uC is suited for simple applications taht does not require huge memory and program. No extra memory is intended to be used with this. uP is for larger memory and for aminly Computers. DSP is an Signal processing optimized uC. Here there are devices with small and large memory, but are mainly intended for standalone applications. Of cou
Having visited the feko website, I noticed the following bit of news: ******************************************************* MLFMM for Electrically Large Structures A new module that will be released with FEKO Suite 4.2 will make the simulation of electrically large structures simpler and a lot faster, requiring dramatically less memory. Wh
can any one help me in getting my own 8051 core certified. If someone can provide a software to say that the 8051 core i developed is 100% working and perfect, i will be very happy. my core is a single cycle 8051 core. thanking you :D
ok guys division operator in RTL is a tough mother... there exist the textbook algorithms for iterative division. Read the ASM (Algorithmic State Machine) for one of these and work it out. It's only single day for medium-level RTL engineer (with testbenches, verification and all), a little more (days) for student. In OpenCores there exist
If you are using harware multiplier, you should have your result after single cycle plus propagation time. Un saludo
Dear Friends, I am using 8051 & my clock frequency is 11.0592 mhz. If i want to put my software outside controller then how i will select a proper EPROM for that. HOW I WILL DECIDE THE SPEED PARAMETER FOR THIS APPLICATION. Means particular speed IC is best for my application. bye..
"Sure, a DSP can make the calculations and generate the pixel bitmap for an audio spectrum analyzer, but at what cost? Robert gets the same result from a single PIC processor with a design so good he walked away with a Design98 first prize." May be even simpler with a
Wishbone is an open bus architecture. It is more of a specification than a standard. Opencores are now hosting Wishbone -> The revision B3 is the latest version of this specification. There exist certain open IPs adhering to Wishbone. It is much more simple to set than AMBA. In Wishbone you can set a) point-point i
Hold Check is performed one cycle before the setup (in single cycle) because setup you check if data will be captured correctly in the next clock edge. That is the data arrival time is before the data required time.Which in other words means the data will not toggle in the setup window. 2. In hold check , you insure that the data laun
I have went through both specs (not thoroughly though). AMBA and Wishbone both give me good impression. Let state some pros and cons. +Wishbone: Easy to interface to OPB (Xilinx-Microblaze SoCs) +Wishbone: Easier than AMBA in general. +AMBA: single-cycle master handover (not sure if this is possible in Wishbone). +AMBA: Has more sophistica
when our using DC,it usualy make timing cons and check by STA. In STA,the default logic path timing check is single cycle, in complex design we usual have multicycle path, asyn logic , in this design DC will not detect it by itself, so will need us to set it with DC command to make these logic path as Timing Exception
such lcd panels from ex equipment need 30 mhz + much cycle addresed single mode single cycle stepped adressed programming to make them usable these lcd are big area and 32 bit X 4 at least addressed by custom ic of there day fpga ... 1986 not to say it cant be done using pic or mpu good luck i (...)
The microphone input will be AC coupled and filtered to voice frequencys. The usuall way is to use audio frequency shift keying. There is a lot of information on the web about packet radio with an amateur radio license. When I played with it a few years ago the standard mode was 1200baud, I vaguely recall it sent a single cycle of 1200HZ or 240