40 Threads found on edaboard.com: Single Cycle Processor
i am doing an assignment to design a MIPS single cycle processor ,i am doing instruction memory and data memory.may i know what is the functionality and operation of memory ?can anybody help me on this ?
Digital communication :: 12.03.2010 11:43 :: funjoke :: Replies: 1 :: Views: 1031
i have a single cycle processor desging code bu nw i have to modify it for Load upper immidiate instruction (lui) shift logic left and shift logic right. i have a pic of that new hardware but not understand how to modify my code. i have the codee of simple single cycle processor. if there (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 19.06.2011 02:33 :: ss_engg :: Replies: 0 :: Views: 498
can anybody help out the function table of register file in single mips
Hobby Circuits and Small Projects Problems :: 25.03.2010 22:09 :: funjoke :: Replies: 8 :: Views: 2310
i am working with the single mips cycle processor data memory part ,and i am facing problem with the verilog of data memory ...here is my code ...
// Data memory
// It doesn't have a memory read output
input clock, memwrite;
PLD, SPLD, GAL, CPLD, FPGA Design :: 06.04.2010 13:20 :: funjoke :: Replies: 2 :: Views: 1421
i need the code of multi cycle processor in verilog code. i have single cycle processor code but don't know how to modify it...?
Digital Signal Processing :: 19.04.2012 11:09 :: ss_engg :: Replies: 0 :: Views: 468
I'm working on converting a single cycle MIPS processor I wrote in Verilog HDL into a Pipelined MIPS processor.
I'd just like some detailed guidance, programmatically speaking, about how I should go about this.
I understand the main difference between the single (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 29.04.2013 05:19 :: comp_engineer :: Replies: 0 :: Views: 251
i have a problem to write a verilog code of single cycle in mips processor
if anyone can help me to write it
its very important plz
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.05.2009 15:34 :: dody_fadel :: Replies: 0 :: Views: 1454
How to realize a Read- modify -write in single cycle using a Dual Port RAM?
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.05.2011 02:43 :: blooz :: Replies: 4 :: Views: 823
i need help finding the solution to the single-cycle and muti-cycle MIPS processor using VHDL code. i've worked on it for 5 days now and no luck.
someone help me if they can find me some VHDL files.
PLD, SPLD, GAL, CPLD, FPGA Design :: 05.03.2004 13:46 :: email@example.com :: Replies: 2 :: Views: 6896
Can antone please help me in understanding this instruction logic of the single cycle processor. I am confused at some points. what's the input to the program counter? The output to the program counter is going to the instruction memory. But I am confused about the input stage. I read the theories from the book by David A. (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 17.11.2006 12:29 :: amira :: Replies: 2 :: Views: 963
There are many Harvard microcontrollers, DSPs are mostly Harvard, but the key advantages of DSP are:
- most instuctions are single cycle, and 16 or 32 bit devices;
- supports special instructions for signal processing: multiplications, multiply and accumulate the result (MAC) in 1 cycle, data adjusting, representation conversion;
Microcontrollers :: 16.08.2008 09:04 :: Eugen_E :: Replies: 2 :: Views: 955
anybody have verilog code for data memory in single cycle processor mips ?i need it badly ...assignment pls help
PLD, SPLD, GAL, CPLD, FPGA Design :: 02.04.2010 12:24 :: funjoke :: Replies: 0 :: Views: 1276
can anybody explain on how this data memory code work on in this single cycle mips ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 16.04.2010 12:13 :: funjoke :: Replies: 23 :: Views: 6087
hey , i hav made my single cycle mips code in verilog HDL now i hav 2 check my processor for results...can u plz help me out abt what are the steps now ? n simulation tools required ...i don't know how 2 write assembly code 4 it plz. do provide some examples ...thanx
PLD, SPLD, GAL, CPLD, FPGA Design :: 30.11.2010 23:18 :: sarah23 :: Replies: 0 :: Views: 362
All of the three options are correct.
Internal register width, determines number of bits a processor is capable of handing at a time. Register width in turn dictates data bus width, and number of bits ALU can process in single go.
8-bit processor can very well process 16 & 32-bit data, but not necessarily in a single (...)
Microcontrollers :: 20.04.2011 03:30 :: Jack// ani :: Replies: 3 :: Views: 695
I need to decide which CEVA DSP processor to use to incorporate in a digital hearing aid
But I am not sure how to choose the right one seems to be the most popular one for hearing aids and it is the only one listed in the website that
Digital Signal Processing :: 18.09.2012 23:09 :: mahaju :: Replies: 2 :: Views: 230
Its not a easy question to answer, it depends entirely of which processor you are using.
You have to search in the datasheet/manuals for the specific processor you are interested in.
Most of the manufactures specify how many clock cycles is takes to execute an instruction.
For the Coldfire for example, you find this information in the (...)
Microcontrollers :: 19.02.2004 09:58 :: jzo777n :: Replies: 1 :: Views: 844
The clock frequency is devided by 2 inside the 8085 microcontroller ..
Frankly, I don't recall any advantage of deviding the clock frequency, and it is more like an artifact of the 8080 arangement, where the latter used to use 2-phase clock, generated by an external clock IC, the 8224, to perform reading and writing cycles using another external
Electronic Elementary Questions :: 09.05.2005 07:40 :: IanP :: Replies: 3 :: Views: 1252
hi there, please help me with a clear explanation about machine cycle related to the second, please give me the equation, and then about the clock.
Firstly, you should know about clock cycle, which is the highest frequency component in the processor, and is used as a basis for all other operations.
An instruction cycle (
Microcontrollers :: 25.08.2005 11:20 :: checkmate :: Replies: 4 :: Views: 1419
I would look at least at three different companies about 8051.
If you need the fastest and best analog features, look at Silabs. They have a great variety with some exceptional features, outperforming any other 8-bit architecture I know with 100 MHz single cycle devices.
If you need more "standard parts" and top performance is not as imp
Microcontrollers :: 11.05.2006 16:28 :: bobsanjose :: Replies: 2 :: Views: 646
PacoBlaze is a from-scratch synthesizable & behavioral Verilog clone of Ken Chapman's popular PicoBlaze embedded microcontroller. KCAsm is a lightweight PicoBlaze assembler written in Java.
While Ken's version aims toward the most efficient implementation in the Xilinx FPGA architecture, PacoBlaze tries to be as configurable as possible, maint
ASIC Design Methodologies and Tools (Digital) :: 20.04.2007 09:57 :: RegUser_2 :: Replies: 13 :: Views: 15812
Who can modify the HDL code for the single-cycle MIPS processor to handle SRA(shift right arithmetic)...??
-- and 30 May 2006
-- single cycle MIPS processor
Embedded Systems and Real-Time OS :: 19.05.2010 16:21 :: gokhan33 :: Replies: 0 :: Views: 1048
As far I know I don't think that you could find a faster way to test the status of a I/O line using a commercial CPU: usually the status of processor's IO line is mapped to a specific bit in one (or more depending on the IO pin count) CPU register. So I suppose that 2 clock cycles are the minimum overhead you could expect to acquire this informatio
Digital Signal Processing :: 09.06.2010 15:51 :: mowgli :: Replies: 5 :: Views: 955
I need a implementation datapath and controller for MIPS instructions(R-type and I-type instructions) in single cycle with verilog code,can u help me ?
excuse me,did you find what you wanted?if you did,is it possible to send it for me?
PLD, SPLD, GAL, CPLD, FPGA Design :: 23.12.2010 16:31 :: nhn22 :: Replies: 4 :: Views: 2580
plz any one help to modify the MIPS single cycle processor for lui and shift instructions. or any one have any link related to that.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03.04.2011 03:58 :: ss_engg :: Replies: 14 :: Views: 1552
I have a college work where I have to use a VHDL file that was given to me. But whoever made this file used std_logic_arith. So I went and converted it to numeric_std. So far so good, but now I had to add some content, and it's failing to work.
I have to use the SLL operator with std_logic_vector. I know it's not ideal, but it wo
ASIC Design Methodologies and Tools (Digital) :: 11.06.2012 10:14 :: GuiRitter :: Replies: 0 :: Views: 870
Duty cycles can be measured with input capture unit by determing both low and high period, but only within the timing resolution given by the processor clock. Duty cycle infomation at 1 MHz will be respectivly coarse.
Outputs of ATmega are exclusively digital (0/1), so I wonder how you want to output the duty cycle by a (...)
Microcontrollers :: 04.03.2013 04:06 :: FvM :: Replies: 5 :: Views: 424
So which one is better, 1GHz dual core or 2GHz single core?
Depends on your application. If you're just doing a single task a 2GHz single core would be faster. If you're multitasking, the dual-core would probably be faster.
Electronic Elementary Questions :: 11.07.2013 07:48 :: barry :: Replies: 14 :: Views: 378
"The P89LPC932 is a single-chip microcontroller, available in low cost packages,
based on a high performance processor architecture that executes instructions in two
to four clocks, six times the rate of standard 80C51 devices. Many system-level
functions have been incorporated into the P89LPC932 in order to reduce component
count, board space,
Microcontrollers :: 27.04.2004 09:36 :: gorkin :: Replies: 6 :: Views: 1151
has anyone implemented the PHY itself as software ?
It's a chalenge for you at 2.4 GHz.
Why don't you try what is already done in the market ?
You have an 2.4 Ghz IEEE 802.15.4 compliant RF transceiver and 32 MHz syngle-cycle low power 8051 MCU with 128 kByte in-system programable flash and 8 kByte SRAM in a single
Microcontrollers :: 07.02.2006 02:19 :: silvio :: Replies: 10 :: Views: 1738
you can even consider a VLIW processor architecture in which a single clock cycle is enuff to execute a multi-op which has several instructions clubbed together. well as for the clock generated it has to be double the internal clock frequency for the fact that lots of spatial variations could be encountered.. so as to avoid that external (...)
Microcontrollers :: 07.02.2006 07:58 :: arunragavan :: Replies: 3 :: Views: 1342
It is possible to purchase the XT-2000 prototyping board.
There is a Virtex-2P for a single core implementation, and another FPGA for custom hardware.
Every time a new core is generated, a new synthesizd encripted core is provided.
The core is ready to support the Xilinx design flow, so you can you ISE.
I hope it will help you
ASIC Design Methodologies and Tools (Digital) :: 28.06.2006 04:13 :: fiber7 :: Replies: 9 :: Views: 941
DSPs are optimized for speed and DSP. For example, most DSPs execute all their instructions in a single machine cycle. Also, DSPs have instructions specifically designed for DSP, such as "MAC" (multiply and accumulate) which execute in a single machine cycle.
Digital Signal Processing :: 16.08.2006 15:46 :: Kral :: Replies: 2 :: Views: 2103
MAC in DSP is Multiply and accumulate in a single clk cycle.
Digital Signal Processing :: 03.04.2007 03:08 :: chin :: Replies: 4 :: Views: 1014
U can easily design it using memory mapped I/O ... It can have a max of 64K ports in 8086....because single bank can have max of 64k....
Microcontrollers :: 15.07.2007 07:03 :: sohiltri :: Replies: 3 :: Views: 451
MICETEK PowerQUICC III MPC8548E development platform
for Network Communication application
The MT8548E-N development system consists of MPC8548E processor card (MPC8548EPC) and Type-N carrier (PQCBN) and can be used for the development of network communication application. It will help developer quickly and simply set up the hardware platform
Professional Hardware and Electronics Design :: 14.07.2009 22:12 :: candy227 :: Replies: 0 :: Views: 943
Originally the JIFFY was the time interval between system timer interrupts, however today it's referred to as the software clock and based on the kernel variable HZ. The value of HZ ranges from 1ms to 10ms, depending on the speed of the processor with 4ms being the default. JIFFIES is the running count of each JIFFY.
The kernel offers two delay
Linux Software :: 04.04.2010 22:58 :: bigdogguru :: Replies: 2 :: Views: 1230
Many times we require precise internal time delays between two actions this can be accomplished using software techniques like Loop Technique but these delays keep the processor occupied because of which other important functions cannot be done. To relieve the processor of this burden we can use TIMERS provided by the controller. 8051 has two inter
Microcontrollers :: 09.12.2011 02:20 :: abuzarshaikh7 :: Replies: 4 :: Views: 385
so assume we have a MIPS-like ISA, such as the one from MIPS R3001. In this, assuming registers are already available, an addition is computed using a single instruction as follows:
where R1 is the register where the result will be stored, and R2 and R3 are the source registers. Now, the execution of the instruct
ASIC Design Methodologies and Tools (Digital) :: 17.11.2012 10:12 :: kingslayer :: Replies: 3 :: Views: 260
DC-bus current ripple depends on load inductance and PWM scheme (2-level or 3-level), but will be generally high for a single phase H-bridge. Assuming sufficient load inductance and preferable 3-level scheme, the DC-bus "sees" the 30 A motor current switched on and off, resulting in 15 A rms ripple current at 50% duty cycle.
Power Electronics :: 03.03.2013 15:26 :: FvM :: Replies: 4 :: Views: 886