1000 Threads found on edaboard.com: Single Cycle Processor
i am doing an assignment to design a MIPS single cycle processor ,i am doing instruction memory and data memory.may i know what is the functionality and operation of memory ?can anybody help me on this ?
Digital communication :: 03-12-2010 11:43 :: funjoke :: Replies: 1 :: Views: 1261
i have a single cycle processor desging code bu nw i have to modify it for Load upper immidiate instruction (lui) shift logic left and shift logic right. i have a pic of that new hardware but not understand how to modify my code. i have the codee of simple single cycle processor. if there (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-19-2011 02:33 :: ss_engg :: Replies: 0 :: Views: 615
can anybody help out the function table of register file in single mips
Hobby Circuits and Small Projects Problems :: 03-25-2010 22:09 :: funjoke :: Replies: 8 :: Views: 2382
i am working with the single mips cycle processor data memory part ,and i am facing problem with the verilog of data memory ...here is my code ...
// Data memory
// It doesn't have a memory read output
input clock, memwrite;
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-06-2010 13:20 :: funjoke :: Replies: 2 :: Views: 1570
I'm working on converting a single cycle MIPS processor I wrote in Verilog HDL into a Pipelined MIPS processor.
I'd just like some detailed guidance, programmatically speaking, about how I should go about this.
I understand the main difference between the single (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-29-2013 05:19 :: comp_engineer :: Replies: 0 :: Views: 389
i need the code of multi cycle processor in verilog code. i have single cycle processor code but don't know how to modify it...?
Digital Signal Processing :: 04-19-2012 11:09 :: ss_engg :: Replies: 0 :: Views: 606
i have a problem to write a verilog code of single cycle in mips processor
if anyone can help me to write it
its very important plz
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-16-2009 15:34 :: dody_fadel :: Replies: 0 :: Views: 1622
How to realize a Read- modify -write in single cycle using a Dual Port RAM?
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-30-2011 02:43 :: blooz :: Replies: 4 :: Views: 1041
single cycle- all operations (fetcf,decode,execute,writeback..)are performed in a single clock cycle.
Multicycle refers to pipelined datapath where all the above operations are performed in multiple clock cycles.
Read Patterson's computer arcchitecture book for more details
ASIC Design Methodologies and Tools (Digital) :: 03-22-2005 19:05 :: eda_wiz :: Replies: 3 :: Views: 1430
how can we measure mains voltage on single cycle(20ms)
Analog Circuit Design :: 12-16-2012 11:25 :: Micro_brain :: Replies: 3 :: Views: 364
I have a chunk of combo logic (synthesizable netlist) where the shortest path is 1 ns and longest path is 7 ns.
My clock is 5 ns but I need single cycle throughput. If I were to pump input every clk and capture 2 cycles later at every cycle, the shortest path will
have a problem, and longest path may have problem in best (...)
ASIC Design Methodologies and Tools (Digital) :: 03-07-2013 01:01 :: kel8157 :: Replies: 1 :: Views: 212
Can antone please help me in understanding this instruction logic of the single cycle processor. I am confused at some points. what's the input to the program counter? The output to the program counter is going to the instruction memory. But I am confused about the input stage. I read the theories from the book by David A. (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-17-2006 12:29 :: amira :: Replies: 2 :: Views: 1043
anybody have verilog code for data memory in single cycle processor mips ?i need it badly ...assignment pls help
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-02-2010 12:24 :: funjoke :: Replies: 0 :: Views: 1460
can anybody explain on how this data memory code work on in this single cycle mips ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-16-2010 12:13 :: funjoke :: Replies: 23 :: Views: 6994
write a c program to execute x/2^y in single clock cycle
Embedded Systems and Real-Time OS :: 04-22-2014 08:17 :: Maharshi :: Replies: 2 :: Views: 371
i need help finding the solution to the single-cycle and muti-cycle MIPS processor using VHDL code. i've worked on it for 5 days now and no luck.
someone help me if they can find me some VHDL files.
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-05-2004 13:46 :: email@example.com :: Replies: 2 :: Views: 7174
Is there any scheme at all in which it is possible to synchronize a single-bit data signal with an asynchronous clock signal in one cycle of that clock?
ASIC Design Methodologies and Tools (Digital) :: 01-21-2010 17:11 :: animotion :: Replies: 2 :: Views: 679
hey , i hav made my single cycle mips code in verilog HDL now i hav 2 check my processor for results...can u plz help me out abt what are the steps now ? n simulation tools required ...i don't know how 2 write assembly code 4 it plz. do provide some examples ...thanx
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-30-2010 23:18 :: sarah23 :: Replies: 0 :: Views: 426
All of the three options are correct.
Internal register width, determines number of bits a processor is capable of handing at a time. Register width in turn dictates data bus width, and number of bits ALU can process in single go.
8-bit processor can very well process 16 & 32-bit data, but not necessarily in a single (...)
Microcontrollers :: 04-20-2011 03:30 :: Jack// ani :: Replies: 3 :: Views: 752
oh thank u :-) but sir ....still i am in confusion , that DDR3 1033 ...wat is that number in front of ddr3 and single core means only one processor having XGhz of speed and dual core means 2XGhz ?
General Computer :: 07-28-2012 07:45 :: sunidrak :: Replies: 7 :: Views: 609
I need to decide which CEVA DSP processor to use to incorporate in a digital hearing aid
But I am not sure how to choose the right one seems to be the most popular one for hearing aids and it is the only one listed in the website that
Digital Signal Processing :: 09-18-2012 23:09 :: mahaju :: Replies: 2 :: Views: 388
I am trying to implement a single cycle MIPS processor. I've been able to execute the dual level controller but there seems to be some error with the datapath. Can someone please see and tell me what the error is.
I used a test output signal called test_pc to check if the value from pc is correct or not. Initially 0's and then (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-29-2014 06:49 :: sarjumaharaj :: Replies: 1 :: Views: 209
SL11IDE USB t IDE single chip processor
Microcontrollers :: 02-21-2003 08:17 :: tctsai :: Replies: 1 :: Views: 1233
if u have a big combinational logic in ur design which will never run at ur required frequency...
u have 2 options
1)Add pipeline stage(s) to divide the logic into single-cycle paths
2. Ease off the single-cycle requirement: allow more clock cycles using set_multicycle_path command. (...)
ASIC Design Methodologies and Tools (Digital) :: 11-17-2004 08:13 :: eda_wiz :: Replies: 8 :: Views: 18822
I would look at least at three different companies about 8051.
If you need the fastest and best analog features, look at Silabs. They have a great variety with some exceptional features, outperforming any other 8-bit architecture I know with 100 MHz single cycle devices.
If you need more "standard parts" and top performance is not as imp
Microcontrollers :: 05-11-2006 16:28 :: bobsanjose :: Replies: 2 :: Views: 728
Multi cycle path must be configured during synthesis, to ensure
synthesis tool doesnot try to optimise the path into a single clk
Multi cycle path needs timimg analyse its a need and must. it must be optimised
ASIC Design Methodologies and Tools (Digital) :: 02-13-2008 23:20 :: santuvlsi :: Replies: 4 :: Views: 934
There are many Harvard microcontrollers, DSPs are mostly Harvard, but the key advantages of DSP are:
- most instuctions are single cycle, and 16 or 32 bit devices;
- supports special instructions for signal processing: multiplications, multiply and accumulate the result (MAC) in 1 cycle, data adjusting, representation conversion;
Microcontrollers :: 08-16-2008 09:04 :: Eugen_E :: Replies: 2 :: Views: 1018
Who can modify the HDL code for the single-cycle MIPS processor to handle SRA(shift right arithmetic)...??
-- and 30 May 2006
-- single cycle MIPS processor
Embedded Systems and Real-Time OS :: 05-19-2010 16:21 :: gokhan33 :: Replies: 0 :: Views: 1195
As far I know I don't think that you could find a faster way to test the status of a I/O line using a commercial CPU: usually the status of processor's IO line is mapped to a specific bit in one (or more depending on the IO pin count) CPU register. So I suppose that 2 clock cycles are the minimum overhead you could expect to acquire this informatio
Digital Signal Processing :: 06-09-2010 15:51 :: mowgli :: Replies: 5 :: Views: 1079
I need a implementation datapath and controller for MIPS instructions(R-type and I-type instructions) in single cycle with verilog code,can u help me ?
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-16-2010 03:39 :: mostafa272 :: Replies: 4 :: Views: 3032
plz any one help to modify the MIPS single cycle processor for lui and shift instructions. or any one have any link related to that.
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-03-2011 03:58 :: ss_engg :: Replies: 14 :: Views: 1698
MCP's are driven by Design, not by tools. By protocol, if design want to meet in single cycle and if tool is unable to meet the constraint, you cant put straight away the MCP to 2 or more.
Below are the scenarios :
1. When you multi clock designs , like div by 2. you can meet some times in single clock cycle. Need to (...)
ASIC Design Methodologies and Tools (Digital) :: 04-24-2012 06:08 :: sam536 :: Replies: 4 :: Views: 960
I have a college work where I have to use a VHDL file that was given to me. But whoever made this file used std_logic_arith. So I went and converted it to numeric_std. So far so good, but now I had to add some content, and it's failing to work.
I have to use the SLL operator with std_logic_vector. I know it's not ideal, but it wo
ASIC Design Methodologies and Tools (Digital) :: 06-11-2012 10:14 :: GuiRitter :: Replies: 0 :: Views: 1129
I have watched the book "Computer Organization And Design", and i want to implement a simple single clock mips(chapter 4.4) in my altera fpga board. Here is the problem i encountered:
the altera fpga sram read the address at the rising edge and gives the valid data the next clock rising edge. that seems make the single clock implementation impossi
ASIC Design Methodologies and Tools (Digital) :: 09-25-2012 04:02 :: aspirinnnnn :: Replies: 2 :: Views: 353
The flop to save the CSN could be generated in the same time as the address generation, not at memory level, but at the bus level.
Dependand of the address mapping usage, you could used the MSB bit has direct chip select.
A single bit MSB is used for the CS, and the 16bits-LSB for address.
ASIC Design Methodologies and Tools (Digital) :: 03-21-2014 04:12 :: rca :: Replies: 7 :: Views: 270
Getting MP3 decoding going on a Xilinx may be quite difficult. Have you thought of using a dedicated decoder chip such as the MAS35xx series? ( )
You will also need to have some sort of CPU to string this all together again the opencores site have a few!
An alternative could be to use the LEON sparc core ( www.g
Professional Hardware and Electronics Design :: 03-18-2002 20:48 :: SysDaemon :: Replies: 7 :: Views: 2074
May someone post the professional hardware setting for Laker-linux
in your company?
1. Brand of Mother board
2. CPU(Intel? or AMD?, speed??, single/Dual processor?)
3. Memory(DDR? or RDRAM? , w/ or wo/ ECC?, 512M/1G/2G??)
4. Brand/model of Graphics card, how many video memory?
5. What kind of mouse for better drawing
Linux Software :: 03-27-2003 09:12 :: sunjimmy :: Replies: 0 :: Views: 1583
uC is suited for simple applications taht does not require huge memory and program. No extra memory is intended to be used with this.
uP is for larger memory and for aminly Computers.
DSP is an Signal processing optimized uC. Here there are devices with small and large memory, but are mainly intended for standalone applications. Of cou
Microcontrollers :: 05-10-2004 08:26 :: brmadhukar :: Replies: 7 :: Views: 13706
Having visited the feko website, I noticed the following bit of news:
MLFMM for Electrically Large Structures
A new module that will be released with FEKO Suite 4.2 will make the simulation of electrically large structures simpler and a lot faster, requiring dramatically less memory. Wh
Electromagnetic Design and Simulation :: 06-05-2004 12:25 :: wave-maniac :: Replies: 26 :: Views: 4115
can any one help me in getting my own 8051 core certified. If someone can provide a software to say that the 8051 core i developed is 100% working and perfect, i will be very happy. my core is a single cycle 8051 core.
thanking you :D
Microcontrollers :: 09-09-2004 04:19 :: silencer3 :: Replies: 0 :: Views: 1368
division operator in RTL is a tough mother...
there exist the textbook algorithms for iterative division. Read the ASM (Algorithmic State Machine) for one of these and work it out. It's only single day for medium-level RTL engineer (with testbenches, verification and all), a little more (days) for student.
In OpenCores there exist
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-21-2004 06:15 :: the_penetrator :: Replies: 8 :: Views: 1945
If you are using harware multiplier, you should have your result after single cycle plus propagation time.
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-21-2004 05:12 :: bercam :: Replies: 1 :: Views: 825
I am using 8051 & my clock frequency is 11.0592 mhz. If i want to put my software outside controller then how i will select a proper EPROM for that. HOW I WILL DECIDE THE SPEED PARAMETER FOR THIS APPLICATION. Means particular speed IC is best for my application.
Embedded Systems and Real-Time OS :: 11-09-2004 03:36 :: sacrpio :: Replies: 2 :: Views: 882
"Sure, a DSP can make the calculations and generate the pixel bitmap for an audio spectrum analyzer, but at what cost? Robert gets the same result from a single PIC processor with a design so good he walked away with a Design98 first prize."
May be even simpler with a
Hobby Circuits and Small Projects Problems :: 12-31-2004 07:13 :: Gorilla :: Replies: 8 :: Views: 17937
Wishbone is an open bus architecture. It is more of a specification than a standard.
Opencores are now hosting Wishbone ->
The revision B3 is the latest version of this specification. There exist certain open IPs adhering to Wishbone. It is much more simple to set than AMBA. In Wishbone you can set a) point-point i
ASIC Design Methodologies and Tools (Digital) :: 12-16-2004 09:29 :: the_penetrator :: Replies: 2 :: Views: 3215
Hold Check is performed one cycle before the setup (in single cycle) because setup you check if data will be captured correctly in the next clock edge.
That is the data arrival time is before the data required time.Which in other words
means the data will not toggle in the setup window.
2. In hold check , you insure that the data laun
ASIC Design Methodologies and Tools (Digital) :: 04-07-2005 14:58 :: Raptor :: Replies: 4 :: Views: 1657
I have went through both specs (not thoroughly though).
AMBA and Wishbone both give me good impression. Let state some pros and cons.
+Wishbone: Easy to interface to OPB (Xilinx-Microblaze SoCs)
+Wishbone: Easier than AMBA in general.
+AMBA: single-cycle master handover (not sure if this is possible in Wishbone).
+AMBA: Has more sophistica
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-14-2005 21:33 :: the_penetrator :: Replies: 3 :: Views: 2016
when our using DC,it usualy make timing cons and check by STA. In STA,the default logic path timing check is single cycle, in complex design we usual have multicycle path, asyn logic , in this design DC will not detect it by itself, so will need us to set it with DC command to make these logic path as Timing Exception
ASIC Design Methodologies and Tools (Digital) :: 07-11-2005 23:17 :: dolby.yang :: Replies: 8 :: Views: 1384
such lcd panels from ex equipment
need 30 mhz + much
stepped adressed programming
to make them usable
these lcd are big area and 32 bit X 4 at least addressed by custom ic of there day
fpga ... 1986
not to say it cant be done using pic or mpu good luck
Electronic Elementary Questions :: 09-07-2006 20:31 :: VSMVDD :: Replies: 4 :: Views: 1798
The microphone input will be AC coupled and filtered to voice frequencys.
The usuall way is to use audio frequency shift keying. There is a lot of information on the web about packet radio with an amateur radio license. When I played with it a few years ago the standard mode was 1200baud, I vaguely recall it sent a single cycle of 1200HZ or 240
Analog Circuit Design :: 10-03-2005 12:01 :: throwaway18 :: Replies: 11 :: Views: 1964