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3 Threads found on edaboard.com: Sinks Clock
clock latency just means how much time it took for your clock signal to reach from clock generation point to sink. Ideally, the latency to all the sinks from a clock should be same, meaning all registers are receiving clocks at the same time. However, that is not the case, and hence we add (...)
ASIC Design Methodologies and Tools (Digital) :: 03-03-2017 04:28 :: Simranjeet Singh :: Replies: 2 :: Views: 228
If i understood correctly you are trying to build the CTS from pll_clk and this clk goes to divider (flops) and output of those divider will act as clock .
1.why r u building the CTS from root pin to this divider flop if there is no other sink to the root clock except divider flop.
If there are other sinks to the root clk then you (...)
ASIC Design Methodologies and Tools (Digital) :: 12-29-2010 00:15 :: srihari_adem :: Replies: 4 :: Views: 1241
cant you create a separate clock tree for each of these generated clock tree sinks and then balance these 2 sub trees..what is the latency you are seeing? how close are the gators to the sinks? how is your enable pin timing ? Do you set -ve latency constraints on these enable pins of the clock gator? if you (...)
ASIC Design Methodologies and Tools (Digital) :: 09-21-2009 15:46 :: kbulusu :: Replies: 6 :: Views: 2496