16 Threads found on edaboard.com: Sinks Clock
while using SoC encounter, I didn't quite understand a couple of options
you can provide the CTS engine with:
- clkgroup (the sinks of all clock root pins listed in a ClkGroup statement
will meet the maximum skew value set in the clock tree specification file.
clock grouping inserts delays to balance (...)
ASIC Design Methodologies and Tools (Digital) :: 24.05.2009 11:40 :: ludan :: Replies: 2 :: Views: 2634
some FFs are used as a counter to divide the master clock,for example,reg clock,clock is the divided_by_2 clock...
but the CP pin of clock are not balanced by Astro by default.
the document said:"By default, CTS will not balance the skew of FFs that cross clock domains."
so here's the (...)
ASIC Design Methodologies and Tools (Digital) :: 29.04.2008 10:43 :: starmx :: Replies: 3 :: Views: 1142
sinks are nothing but the clock tree end points.The distribution of sinks across the design plays an important role in getting skew to zero for a clock domain.. Also if in case, of balancing across multiple clock domains, that is inter clock domain balancing, sink #s play a important role. (...)
ASIC Design Methodologies and Tools (Digital) :: 04.06.2009 04:25 :: daman :: Replies: 3 :: Views: 2063
I think you should keep in mind that if there are some clocks should be balanced with each other. If so, you should put these clocks into one group to balance them.
Then you can clarify the sinks of the specified clock. clock tree insertion tools will help you synthesize the (...)
ASIC Design Methodologies and Tools (Digital) :: 01.07.2009 01:54 :: owen_li :: Replies: 6 :: Views: 1470
cant you create a separate clock tree for each of these generated clock tree sinks and then balance these 2 sub trees..what is the latency you are seeing? how close are the gators to the sinks? how is your enable pin timing ? Do you set -ve latency constraints on these enable pins of the clock gator? if you (...)
ASIC Design Methodologies and Tools (Digital) :: 21.09.2009 15:46 :: kbulusu :: Replies: 6 :: Views: 2163
I don't know, what are the exact commands to use in SOC encounter per se.. but for checking the QOR of CTS you have to check the local skew, global skew,insertion delay, clock tree cell count,trace the clock tree structure for the top ins delay sinks.
ASIC Design Methodologies and Tools (Digital) :: 16.01.2010 13:40 :: itsmeteja :: Replies: 4 :: Views: 980
If i understood correctly you are trying to build the CTS from pll_clk and this clk goes to divider (flops) and output of those divider will act as clock .
1.why r u building the CTS from root pin to this divider flop if there is no other sink to the root clock except divider flop.
If there are other sinks to the root clk then you (...)
ASIC Design Methodologies and Tools (Digital) :: 29.12.2010 00:15 :: srihari_adem :: Replies: 4 :: Views: 948
I've been working with 8051 for the last 5 years, and this little uC never let me down. But now I've to develop a portable equipment and #A%T$M@E^L 8051 sinks lots of mA... is there any family or uC as easy to find and as cheap as 8051 that would have the same architeture but with much less current consumption?? And also very i
Microcontrollers :: 06.03.2003 20:32 :: 2000 :: Replies: 4 :: Views: 1475
(sorry for my english)
you can generate the signal with one of the blocks, located at sources page of the standart library.
generally, you should to set the type of the time step to discrete (in "Simulation Parameters..." menu)
1. if you work in new version of MATLAB then you should to set the type of output signal of generator. for digital sign
Digital Signal Processing :: 30.07.2005 09:02 :: bpu :: Replies: 2 :: Views: 2071
CML is certainly not neccessary, reasonable (
Analog IC Design and Layout :: 03.07.2007 20:52 :: eternal_nan :: Replies: 22 :: Views: 6353
Maybe it's a trick question, prompting you to put a clock divisor on the PLL output? The PLL would still only output a single frequency ofcourse.. I cannot see how a single PLL can lock onto multiple frequencies. "Multiple outputs" could perhaps also refer to buffering of the PLL output, in order to drive multiple sinks?
Analog IC Design and Layout :: 16.08.2007 00:50 :: vandelay :: Replies: 2 :: Views: 644
It is very common to implement a pullup resistor, then attach sinking logic. This would imply active low. You'll also find some logic that is active on one clock phase, while other logic is inactive. By mixing your active signals you can often reduce hardware.
You will find that most digital logic sinks as opposed to sources. Yet in industrial P
Electronic Elementary Questions :: 29.08.2009 22:24 :: GetDeviceInfo :: Replies: 5 :: Views: 3249
I would suggest not taking Encounters advice and excluding your clock net :) so don't worry about the clock spec. It sounds like the issue is in your design itself. Check the net 'clk' to see if it has more than one driver.
try doing a check_design -all and look to see if it flags multi driven nets. You can also try report_net -net clk, i th
ASIC Design Methodologies and Tools (Digital) :: 21.04.2010 20:37 :: shelby :: Replies: 11 :: Views: 2176
Iam working with place and route of huge mixed signal block , in which i need to reduce the net delay of one net with out modifying its driver, sinks and its length. Is it possible ? If so , please guide me.
ASIC Design Methodologies and Tools (Digital) :: 17.08.2011 06:36 :: viswanadh_babu :: Replies: 6 :: Views: 635
You need target skew, clock buffer list, max trans constraint for sinks , max trans constraint for buffers & max Cap too.
You have some target for insertion delay, then give that too, otherwise in first pass let the tool build clock tree.
Then for better optimization you need
custom ignore pin list, leaf pin group & through pins .. (...)
ASIC Design Methodologies and Tools (Digital) :: 06.12.2012 01:50 :: curty :: Replies: 3 :: Views: 385
global skew gives you an idea about what sinks are pushing the clock insertion delay to increase. For example, if local skew skew is large for a certain skew group in test mode and it is causing hold problem, whether or not the global skew is large in func mode can explain why the local skew is large in test mode.
ASIC Design Methodologies and Tools (Digital) :: 13.03.2013 17:06 :: parkbench :: Replies: 3 :: Views: 408