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1000 Threads found on Sinks Clock
Hi guys, while using SoC encounter, I didn't quite understand a couple of options you can provide the CTS engine with: - clkgroup (the sinks of all clock root pins listed in a ClkGroup statement will meet the maximum skew value set in the clock tree specification file. clock grouping inserts delays to balance (...)
some FFs are used as a counter to divide the master clock,for example,reg clock,clock is the divided_by_2 clock... but the CP pin of clock are not balanced by Astro by default. the document said:"By default, CTS will not balance the skew of FFs that cross clock domains." so here's the (...)
sinks are nothing but the clock tree end points.The distribution of sinks across the design plays an important role in getting skew to zero for a clock domain.. Also if in case, of balancing across multiple clock domains, that is inter clock domain balancing, sink #s play a important role. (...)
Hi I think you should keep in mind that if there are some clocks should be balanced with each other. If so, you should put these clocks into one group to balance them. Then you can clarify the sinks of the specified clock. clock tree insertion tools will help you synthesize the (...)
cant you create a separate clock tree for each of these generated clock tree sinks and then balance these 2 sub trees..what is the latency you are seeing? how close are the gators to the sinks? how is your enable pin timing ? Do you set -ve latency constraints on these enable pins of the clock gator? if you (...)
I don't know, what are the exact commands to use in SOC encounter per se.. but for checking the QOR of CTS you have to check the local skew, global skew,insertion delay, clock tree cell count,trace the clock tree structure for the top ins delay sinks.
If i understood correctly you are trying to build the CTS from pll_clk and this clk goes to divider (flops) and output of those divider will act as clock . Then 1.why r u building the CTS from root pin to this divider flop if there is no other sink to the root clock except divider flop. If there are other sinks to the root clk then you (...)
Does anybody have any experiance with ATTiny12 running with internal clock.How accurate is the clock?Can it run half-duplex RS232 (software emulated)?? Alex
How can i make the constraint(in Synopsys and apollo) to push the different gated clocks domain into balanced clock's latency ?
ICD2053 is the serial programmable pll clock synthesizer chip of Cypress. But it no longer become production. I'm lopking for for the replacement of ICD2053. Is there anybody who know about this solution.
Any one know this topic? I aready know PLL, but how to apply PLL to it?
Synopsys Power Compiler can use integrated gate-clock cell (Latch type) to implement a low power design. Which StandCell Library support the integrated gate-clock cell (Latch Type) that can be used by power compiler ?
Hi: can anyone tell me how to estimate the delay of a clock tree for 500 register. I have gated clock in my design which have a original clock A. using dc, I create a clock for that clock B. but how to set the delay of the clock B relative to clock A. Or I (...)
I need to change the output clock from default to 8MHz, to clock AT90S8515. But sometimes(after RESET button pushed) this freq is more than 8 MHz... Well, can i do smth to stop this bug. Regards...
Hi! I need theory of operation for Dual clock fifos. please help me! Thanks in adv! :)
Hi, I need to use in my project an extra I/O port chips, a real time clock and if possible a LCD display (I know this was available in past from Philips and production stoped) Any advice for a low cost widely used LCD didplay is welcome. I have no problem to find those chips but would like to use components that are widely used on and not ex
Hello, anyone knows a simple way how to divide frequency by 3 ? The whole problem is as follows... I have a TTL compatible signal with the frequency of 10 MHz. I need to multiply the frequency by 3, because I need 30 MHz as an input to AD9851 DDS chip. So, I designed a simple PLL multiplier (NE564) and I need "divide by 3" circuit in th
Hi ! I am looking for Unusual clock deviders & random count generators can any one help me ! I do have some documents I would like to share with you all. :P
who can explain the difference of between clock tree and reset tree?
I have built an FPGA-based FSK demodulator but i have a problem in clock recovery ... can any body give me a hand in this prob. Thanx
hi all this is nice clock thanks s 8O krat
Here is an interesting clock site I came across. Enjoy Sorry for the duplicate post! Enigma460
I have a few questions about LVDS LVDS: (1) The clock pair frequency is different from the data pair frequency. What is the skew requirements between clock pair and data pairs? (2) How should I measure the delay: Is it from the crossing point of the driver differential pair to the crossing point of the receiver differential pair?
clock skew jitter thesis (4 files part 4)
I have several clock in my design. They have different frequency. I have to set false path from clock to clock. The netlist pass the STA chencking, However, it failed in dynamic simulation. How could i solve this problem in my STA scripts?
High Level Analysis of clock Region in a C++ system description
Hello, Does anyone have a clock circuit for displaying sidereal or "star time"? Any and all help is appreciated. Thanks.
use"clock enable " instead of gated clock ?
Does anyone has experience with ASIC design with latch and two phase clock? I though it may save area using latches. The two phase clock scheme can handle the timing problem with latch. What I don't know is whether it can be employed in the ASIC design flow using Synopsys tools. Would anyone like to comment on the timing check and DFT of the des
Hi , I have to transfer a data from Flip flop1 to Flip flop2,Flip flop's hold time is '0' and clk to q delay is 'x' ns.Between Flip flops there are combinational logics which takes 'y' ns.I'm having a pulse whose high period is more than 'x' ns.Its duty cyle is 20% high and 80% low.Can I use this pulse or is there any need that I have to use
Hi there, I'm working on a project and i want to use 628's internal clock.I'm programming on ccs c++ how will i modify my code and how will i modify my circuit?(Esp. osc. section) By the way is it safe like xtall? Can you explain everything deeply please? Analyzer
A clock design pic16c54 for led displays and switch inputs schema+asm
Low-Power Real- time clock
Any info about how to generate a non-integer clock divider. Like Clk_out = Clk_in x (N/M), N and M are integer. Thanks !
hi, i need idea or application how to design PCI 2.2 clock generation. meaning 33/66 MHz depand on M66EN signal. i need to distribute the clock to 3 devices TIA :D
Altera :Multiple clock System Design
use pipe line design to speed up the clock
I need a synthesizable code for FIFO with dual clock (input one clcok. output another clock domain). Anybody can help ?
2 question(s) about FPGA technology: First, how to implement the spread-spectrum PLL on FPGA ? /*--- Spread-spectrum clocking schemes spread the fundamental clock frequency energy to minimize energy peaks at specific frequencies. ---*/ Second, how to implement the clock switchover circuity on FPGA ? /*-- (...)
I design a clock gating circuit now. But it's my first time. Could somebody help me? Give me some advice about it? Thanks in advance. :(
hello friends, I've been working with 8051 for the last 5 years, and this little uC never let me down. But now I've to develop a portable equipment and #A%T$M@E^L 8051 sinks lots of mA... is there any family or uC as easy to find and as cheap as 8051 that would have the same architeture but with much less current consumption?? And also very i
I am trying to design a MCU with gated clock to save the power . I have no idea about how to write the script to synthesis my chip Because the AND or NAND gate used to gate the clock has a long delay but it not make sense since the clock tree has not been created . The clock tree will be created by P&R tool and the (...)
which clock is working in digital part (like bit stuff,NRZI encode)? 480M or 60/30M? 8O
The flexlm return error :system clock has been changed. How to fix it ?
I used to use AT90S8535 with bascomAVR then I change to ATMEGA 16 First I try to program it using STK200/300 Compatible isp cable. It program OK But chip ATMEGA16 was work veryslow. Then I read the data sheet it said that default clocksource is internal 1 MHz osc. (I used Crystal 8 MHz) so i need to changed Fuse bit to make it know what clock sour
Hello, I need clock generator 32kHz (square 3,3V) for CPLD. Does anyboby know a suitable chip (as small as possible). Thanks. FrantaK
Hi I only have in the NS MM53200 datasheet page 1 and 2 Somebody has the complete NS datasheet ? I'd like to know the min and max clock frequency Nothing about in the complete UM3750 datasheet :( Thx
Hi. Can advise the link or the book on algorithm or the circuit for clock recovery for M-FSK if sampling frequency is approximately equal to the double clock frequency.
hi , gated clock vs CE(clock Enable) for LOW POwer Design. which one is good for a low power design. comments please. Also please mention other poupular low power methodologies tnx
Anyone familiar with clock-tree Synthesis(CTS)? Suppose a gigantic SoC design case, there are a RISC cpu core and a number of other sub-modules in it. Then how do you build the clock-tree? Do you build Sub clock-tree within(in) the sub modules or only do CTS from the top-level? In our design case, we do CTS from top-level using (...)