1000 Threads found on edaboard.com: Slew Rate In Op Amp
slew rate can be improved by increasing the output current capacity of the amplifier or decreasing the load capacitor....
Analog Circuit Design :: 10-23-2007 02:46 :: A.Anand Srinivasan :: Replies: 4 :: Views: 1116
Does anyone know how to work out the CMRR (Common Mode Rejection Ratio), PSRR (Power Supply Rejection Ratio) and slew rate using Cadence simulator for a 741 Op-amp?
Could anyone explain to me how to work out the differential gain of my op-amp using the Cadence calculator?
Analog Circuit Design :: 02-24-2004 14:45 :: ee01akk :: Replies: 11 :: Views: 9267
what is your slew rate target. 2000V/us?
Analog Circuit Design :: 05-19-2012 09:27 :: kwkam :: Replies: 5 :: Views: 410
I am measuring slew rate of 2 stage op amp (diff input, single output). I use method connecting output to inverting input and testing square wave to non- inverting input. I expect the output should follow input with slew rate limited. But I did not get full vdd from output(I got vdd -100mV). Could (...)
Analog Circuit Design :: 12-30-2010 02:14 :: tompham :: Replies: 3 :: Views: 559
read this short pdf. u could get some idea... it depends on the compensating capacitor
Analog Circuit Design :: 03-08-2005 23:54 :: cedance :: Replies: 7 :: Views: 2717
What are the bad things about a generators slew rate?
What kind of problems can a generators slew rate cause?
When you overload or Draw to much current from a Generator, its causes a slew rate problem , how can you fix this type of problems when there is a current surge or overload (...)
Electronic Elementary Questions :: 07-26-2013 22:38 :: danny davis :: Replies: 3 :: Views: 347
what is the definition of the effective bandwidth in op amp? who help me,thanks
Analog IC Design and Layout :: 11-15-2007 20:38 :: h.martin :: Replies: 0 :: Views: 724
the problem is : how to raise 30 % direct current (DC) gain in op-amp circuit ?
Do we need to do something at R9 & R10 to improve it?
or depend on the Vcc?
Analog IC Design and Layout :: 07-30-2009 23:36 :: fendyfazeli :: Replies: 5 :: Views: 2243
Please explain the necessity of dc feedback in op-amp.
Analog Circuit Design :: 04-23-2010 12:02 :: mixedsignal :: Replies: 2 :: Views: 992
Please let me know that there is any microcontroller that have built-in OP-amp or can I use internal microcontroller comparator
Microcontrollers :: 03-23-2013 17:30 :: imranahmed :: Replies: 1 :: Views: 694
I see that the biasing circuit below is used a lot in op amp design. However, I couldn't find any document explaining how it works. Could anyone tell me some document explain the operating principle of the biasing circuit?
Or could you explain it to
Analog IC Design and Layout :: 07-11-2014 09:09 :: anhnha :: Replies: 3 :: Views: 277
is there any possibility of improving slew rate of a op-amp IC 741
Electronic Elementary Questions :: 03-13-2006 07:10 :: electronics_kumar :: Replies: 6 :: Views: 3112
I have designed a fully differential op amp. I do not know exactly how to measure the slew rate for a fully differential op amp. Generally for a single ended op amp we connect the op amp in non inverting(feed back) mode and measure the slew rate.
How to (...)
Analog IC Design and Layout :: 04-27-2009 23:34 :: bhargava834 :: Replies: 2 :: Views: 2157
Unity gain configuration allows for large input step (max).
slew limited part ends when the feedback takes control of the loop, so it is easy to see that the unity gain configuration would exhibit the same slew rate over a larger time/voltage that makes it easier to demonstrate and measure.
The series resistor would (...)
Analog Circuit Design :: 02-21-2013 04:10 :: saro_k_82 :: Replies: 3 :: Views: 656
I like to know, how do we measure slew rate of an opamp in cadence.
What is the relation of slew rate and settling time.
Analog IC Design and Layout :: 12-08-2005 00:49 :: Anachip :: Replies: 12 :: Views: 13399
i've designed a CMOS folded cascode opamp to have a slew rate of 150 V/us (Iss of the differential pair is 30 uA and CL = 200 fF) in unity gain configuration. I found that ICL is about 1 mA.I saw current in the differential pair is unbalanced in one branch only for a very quick time so the capacitor can't charge like i would.
So i (...)
Analog IC Design and Layout :: 11-22-2012 08:13 :: -CAM- :: Replies: 7 :: Views: 864
The slew-rate of an op-amp is defined as the maximum rate of change of the output voltage for all possible input signals.
where vout(t) is the output produced by the amplifier as a function of time t.
slew rate is typically expressed in units of V/?s.
Electronic Elementary Questions :: 04-07-2007 13:18 :: mannnish :: Replies: 4 :: Views: 2432
Dear Sir :
I have know how to define the opamp DC gain , and Fu for stage, But I still understand about the slew rate. I read some paper , The slew rate is large signal depend on the CL and CLK rate, But actually I still under, if I have ADC specific , example 10bits (...)
Analog IC Design and Layout :: 10-30-2007 11:55 :: mitgrace :: Replies: 2 :: Views: 728
I designed a folded cascade Opamp with Hspice and I want to know that how can I simulate slew rate with Hspice ?
could you show a schematic about your answer?
with best wishes :wink:
Analog IC Design and Layout :: 07-02-2012 07:15 :: A.jafari :: Replies: 1 :: Views: 480
I am interested in CMOS chip design. And better matching for offset, PSRR, CMRR, slew rate symmetry, EMC etc.
Analog Circuit Design :: 04-29-2013 13:31 :: snfvsd :: Replies: 2 :: Views: 376
To Analog IC helper :
I recently design OP-amp , and got very big issue with current mirror in OP-amp circuit. Please download the circuit ( that is attachment) , Within the white square, that is the simple current mirror to provider current for different amp (1st stage) .
My problem is that I set 40u A in i1 , (...)
Analog IC Design and Layout :: 04-20-2005 04:44 :: wesspower :: Replies: 1 :: Views: 816
i am electrical engg. i am new to this op-amp world. i would like to know what exactly a VIRTUAL GROUND refer to........
Analog Circuit Design :: 06-20-2006 03:47 :: rakesh_aadhimoolam :: Replies: 7 :: Views: 16850
generally slew rate is important in close loop amplifiers.
so, if opamp is closed loop as a unity buffer, SR>V*W is true.
Analog Circuit Design :: 11-26-2007 14:08 :: hr_rezaee :: Replies: 1 :: Views: 986
I want to design sample and hold circuit using double sampling technique at 160MHz clock (320MS/s) and 70dB IMD. Here I choose the two-stage opamp, the schematics are here. (Two stage module and the double sampling). But slew rate and charge injection decrease the IMD (...)
Analog Circuit Design :: 12-16-2007 18:18 :: hbsustc :: Replies: 0 :: Views: 835
its been a confusion for me regarding virtual ground concept in Op-amps.
can anyone explain this in detail...
Analog Circuit Design :: 04-09-2008 05:31 :: Guru59 :: Replies: 3 :: Views: 939
I donot know how the slew rate in this paper is calculated . Does anyone know , please tell me ,thank you!
Analog IC Design and Layout :: 04-29-2008 07:17 :: wwwww12345 :: Replies: 5 :: Views: 2126
Dear all.I have some question about determining resistance value in designing op amp circuit. For example we want to design inverting amplifier with gain=-2. We can choose R combination (Rin=1k and Rf=2k) or (Rin=100k and Rf=200k). The gain is the same. What's difference between two R combination? Is there any effect of choosing small R or (...)
Analog Circuit Design :: 03-08-2009 11:17 :: enas :: Replies: 2 :: Views: 1149
i dont think that should matter, i dont have a slew rate spec, so i just use a nominal current in the buffer stack.. what is ur reasoning behind this...
i will simulate having m12 and m13 to be equal and let u know the results.
Analog IC Design and Layout :: 03-24-2010 22:49 :: steadymind :: Replies: 17 :: Views: 2137
If you want a linear slew rate use the digital control to active a pump up and pump down constant current source.
Analog Circuit Design :: 05-22-2011 16:32 :: RCinFLA :: Replies: 7 :: Views: 929
I had designed a op-amp circuit to control the gain and offset of my input with following connections;
1. Non inverting : connected to a potential divider source (VCC/2) with 3.3V VCC
2. inverting input is connected with input signal via 2.2k resistor and a feedback resistor of 2.94k in parallel with .01uF caps were use between - in and outp
Analog Circuit Design :: 09-12-2012 02:21 :: umesh49 :: Replies: 7 :: Views: 510
i can find the thevenin resistance in circuit such as Cap , Inductor and resistor network but in the op-amp circuit how can i find the thevenin resistance across of the cap pins in these circuit that i imagine to find the thevenin resistance (because i want to design a amplifier and want to find the response frequency with the Cap , cut fr
Electronic Elementary Questions :: 10-25-2012 01:16 :: baby_1 :: Replies: 6 :: Views: 1171
How we generate the 50Hz sine wave using op amp and also this sine wave should be varied 0-50Hz . .any one help me to do this?
Analog Circuit Design :: 08-29-2013 09:26 :: renikanna :: Replies: 4 :: Views: 380
My spec says that the input slew rate should be set to 80ps. I am using Pulse as input signal.
And slew rate is defined by 0.1 Vdd to 0.9 Vdd.
How to I set that in my spice file?
My spice file content.
Software Problems, Hints and Reviews :: 10-07-2013 14:59 :: deepakmd :: Replies: 0 :: Views: 382
How do I connect dc ammeter in output pin of op-amp in proteus software?
Should I connect -ve terminal of dc ammeter to inverting terminal of op-amp or to common ground??
Hobby Circuits and Small Projects Problems :: 09-19-2014 02:31 :: Kick :: Replies: 1 :: Views: 266
Tht's right - if you need fast response it is impossible to slew the gate of the pass device up and down with 100nA. This is probably a device that changes it's bias if it is in slew - similar to the "gain boosted" or "slew-rate enhanced" op amp.
So we cheat, and slew the gate with 2mA, (...)
Analog IC Design and Layout :: 04-11-2006 13:46 :: electronrancher :: Replies: 7 :: Views: 1680
Can op-amp be powered up by a single voltage source? Most books show op-amps powered up by two voltage sources with ground being between them. If op-amps can be powered with only a single voltage source, what would be drawbacks.
Analog Circuit Design :: 05-01-2006 04:23 :: Lucifre :: Replies: 3 :: Views: 885
i have a question about how to simulate slew rate in fully differential switched cap CMFB OPA?
like attached file
Why using 1M Ohm? is more larger more better?
and why using 6.8pF cap as unit gain , why don't use other number?
Analog Circuit Design :: 06-30-2006 05:40 :: chungming :: Replies: 3 :: Views: 1229
Calculate the values of components in op amp circuits.
Licence : Free
File Size : 51Kb
Software Links :: 10-16-2006 04:19 :: Robin Hood :: Replies: 12 :: Views: 5752
This is a very useful small software used to calculate components in Op-amp will need the file vbrun100.dll in Windows folder. Just look for the file on Microsoft website or elsewhere on the internet.
Software Links :: 11-09-2006 04:08 :: nguyennam :: Replies: 3 :: Views: 3366
Hi! I am trying to make a amplifier for 100KHz. I use a commercial op-amp connected to two resistors to realize a non-inverting amplifier likes the typical connection. Although it can provide voltage gain, i find that there is around 30 degrees phase shift for the output when it is compared to the input signal. What can I do to solve this (...)
RF, Microwave, Antennas and Optics :: 07-07-2007 05:10 :: Ching :: Replies: 1 :: Views: 511
hi to all
i want to learn general circuits in op amp and the notes about it.can you guide me or do you know e-book in this field or handbooks?
tanx a lot.
Analog Circuit Design :: 07-30-2007 03:51 :: ashein :: Replies: 16 :: Views: 1039
I need some idea or sample circuit for my project, i want to excite the (sensor(resistance type) , for this i drawn the circuit (using 555 ic ).
And i want implement this circuit into voltage compartor using op-amp. in the non-inverting terminal i applied constant excitation voltage(5v square wave) and inverting terminal connec
Analog Circuit Design :: 12-05-2007 01:14 :: dayal :: Replies: 3 :: Views: 824
What is the effect of negative feedback on slew rate of an amplifier within the feedback loop ?
And if the amplifier has a pole zero doublet what happens to it (I guess that separation between the pole and the zero increases ) ?
Analog Circuit Design :: 06-19-2008 00:11 :: quaternion :: Replies: 7 :: Views: 973
Hi , every one,
I have a question about how to design and analyse a op amp( or any other circuit)´s min Vdd.
I think the basic idea for the min Vdd is it need to let each transistor in a branch "on", that will be Vgs > Vth, right?
so, take a inverter stage for example, then the Vdd min should be (Vthp +Vthn), right?
but in op amp (...)
Analog Circuit Design :: 11-06-2009 09:15 :: zizzbear :: Replies: 2 :: Views: 1049
I am currently still determining the topic my for master's thesis. It has to be an op amp design project that employs gm/id and inversion coefficient (IC) sizing methodology and it has to be novel idea.
Really appreciate suggestions.
Thanks in advanced.
Analog IC Design and Layout :: 01-06-2010 07:29 :: sjamil02 :: Replies: 3 :: Views: 2180
I'm wondering if anyone could clear some issues i have on op-amp output noise.
Seems total output noise would have a KT/C form (with coefficient), and C is the load cap. therefore, a general rule to reduce total output noise is to use large loading cap.
however, from textbook, if we dont take load cap into consideration, the der
Analog Circuit Design :: 03-31-2010 00:57 :: malolo :: Replies: 0 :: Views: 604
slew rate is the output voltage rate in unit time slot.
However, as far as I know the output voltage change rate also depends on the load.
If the load is a capacitor, the voltage change will be slower.
How is the slew rate value in datasheet derived, I mean, the datasheet (...)
Professional Hardware and Electronics Design :: 08-29-2010 21:34 :: rohscomplaint :: Replies: 1 :: Views: 900
Inverting Op-amp 1 with Rf=1kOhm, Ri=1kOhm. Gain = 0dB
Inverting Op-amp 2 with Rf=0.1kOhm, Ri=0.1kOhm. Gain = 0dB
How much is the output impedance of Op-amp 1 and Op-amp 2?
Non-inverting Op-amp 1 with Rf=1kOhm, Ri=1kOhm. Gain = 6dB
Non-inverting Op-amp 2 with Rf=0.1kOhm, Ri=0.1kOhm. (...)
Analog Circuit Design :: 11-01-2011 03:44 :: satheeshvelu :: Replies: 1 :: Views: 614
i read this blog
to use uc for determining the AC voltage value (rms). the first step is to step down the AC voltage to the TTL level using OP amp
and the above blog suggested the OP amp circuitry
Analog Circuit Design :: 05-18-2013 10:10 :: afridii :: Replies: 4 :: Views: 403
How to calculate the baud rate in 8051 & PIC18F microcontroller.?
Microcontrollers :: 09-11-2013 05:41 :: vinothksr08 :: Replies: 4 :: Views: 383