11 Threads found on edaboard.com: Slope Calculation
today I saw an book to describe the modeling of power switch for dcdc.
for me there is a question that about the slope value calculation:
* for the buck, it is obviously that the up slope is S1=(Vin-Vout)/L
* while from the book, it is expressed as S1=Vac/L
I am confused about this equation, and does any one can help me to (...)
Analog IC Design and Layout :: 07-28-2014 11:08 :: dyjguilin :: Replies: 0 :: Views: 174
Nominal Resolution of dual-slope ADC is usually referring to the resolution of the time measurement of de-integration phase and is simply given by your hardware design. Usable resolution is a matter of various error terms and more difficult to determine. Ponts to consider are
- integration capacitor loss factor
- comparator response time
Analog Circuit Design :: 09-22-2012 10:54 :: FvM :: Replies: 2 :: Views: 664
i found the derivative accoring to formula u given ....
i got pulsed waveform 60354
now with this wave form and defination of slew rate we can find slew rate as maximum rate of change of output .....i got such a value equal to...
but these are very high values right ....??
Analog IC Design and Layout :: 08-18-2011 05:53 :: ASHUTOSH RANE :: Replies: 5 :: Views: 1486
I need advices on noise calculation of ADC.
I'm designing a single-slope serial ADC. A two-stage comparator compares Vin with Vramp and drives an NAND-gate. The output of the NAND gate then activates a counter. The counter operates at much higher frequency than the -3dB freq of the compartor.
I want to calculate the thermal noise of t
Analog Circuit Design :: 11-28-2009 21:56 :: noleeach :: Replies: 0 :: Views: 1321
Is this a question?
Is it part of your math homework?
dx(t)/dt denotes the slope of the signal x(t), obtain an expression for the highest allowable slope of the signal in terms of modulation parameters (modulation frequency and step size)
And explain two possible methods to prevent from the slope overloading
Digital Signal Processing :: 06-29-2009 20:26 :: doraemon :: Replies: 1 :: Views: 514
Must be a small question.
I wan to know how to impliment Two point calibration and slope/Offset calculation.
If you have a temperature sensor and you like to calibrate it with two know temperatur levels. There must me some error or difference in the known values and the value given by your sensor.
in software calibration the soft
Microcontrollers :: 08-21-2007 05:16 :: sadat007 :: Replies: 0 :: Views: 2486
If its linear, and you have two points, namely, thinner doping and thicker doping values, make a line and find its slope. X-axis is the distance. Y-axis is the doping profile.
I am not too sure about my answer, but the reason I think its not a bad method is because the gradient is in cm^-4, which is (cm^-3)/cm. Kinda reverse answering..
Analog IC Design and Layout :: 09-14-2006 23:47 :: srivatsan :: Replies: 1 :: Views: 1630
In the opamp design, first u assume the amount of current to flow at the tail, let say about 100uA. Then to find out the value of λ, take a single PMOS or NMOS. You fix the gate voltage and u sweep the VDS (Drain voltage). Later you plot the curve IDS Vs VDS. So, you can measure the value of ro (output impedance) from the slope. Then co
Analog Circuit Design :: 10-11-2005 06:08 :: suria3 :: Replies: 5 :: Views: 980
There is another way to plot gm of one device, however. But for equal gm (Gm) calculation of a specified structure you can measure its slope by using .measure statement and DERIV keyword (or something like that) to calculate the derivative (or slope) of your parameter 'Id/Vgs'. you can name your measurement in your netlist and write the (...)
Analog Circuit Design :: 06-02-2005 04:46 :: ezt :: Replies: 5 :: Views: 4776
It can be runned .Tran analyse with a slow and slope input. It also run .DC analyse and sweep vin.
Analog Circuit Design :: 05-29-2005 05:10 :: staric :: Replies: 4 :: Views: 3438
...please remember following 2 rules for current mirrors..
1. always use Channel length which is 4-5 * Lmin ...(though this is ideal for DSM i.e < 0.25u)....the best thing wud be for u to characterize the MOS and see for which 'L' Id slope is less...use that length
2. Ensure that Vds of mirror X'tors are similar..this takes out (1+
Analog IC Design and Layout :: 09-09-2004 04:03 :: airace :: Replies: 9 :: Views: 986