22 Threads found on edaboard.com: Slope Calculation
...please remember following 2 rules for current mirrors..
1. always use Channel length which is 4-5 * Lmin ...(though this is ideal for DSM i.e < 0.25u)....the best thing wud be for u to characterize the MOS and see for which 'L' Id slope is less...use that length
2. Ensure that Vds of mirror X'tors are similar..this takes out (1+
Analog IC Design and Layout :: 09.09.2004 04:03 :: airace :: Replies: 9 :: Views: 874
just plot 1/slope of the Id-Vd curve of the transistor that will be the curve of the small signal output resistance. Lambda depends upon the biasing point and also the length of the transistor. You can find Lambda from ro if you want, but once you have ro you won't need Lambda.
Analog IC Design and Layout :: 24.06.2005 20:12 :: aryajur :: Replies: 5 :: Views: 1933
In the opamp design, first u assume the amount of current to flow at the tail, let say about 100uA. Then to find out the value of λ, take a single PMOS or NMOS. You fix the gate voltage and u sweep the VDS (Drain voltage). Later you plot the curve IDS Vs VDS. So, you can measure the value of ro (output impedance) from the slope. Then co
Analog Circuit Design :: 11.10.2005 06:08 :: suria3 :: Replies: 5 :: Views: 865
If its linear, and you have two points, namely, thinner doping and thicker doping values, make a line and find its slope. X-axis is the distance. Y-axis is the doping profile.
I am not too sure about my answer, but the reason I think its not a bad method is because the gradient is in cm^-4, which is (cm^-3)/cm. Kinda reverse answering..
Analog IC Design and Layout :: 14.09.2006 23:47 :: srivatsan :: Replies: 1 :: Views: 1461
why the slope of fequency response of gian in Gray's book is -6dB/octave?
i know the slope is -20dB/decade, and i calculate it as follows
what's wrong with my calculation?
Analog Circuit Design :: 08.10.2006 03:52 :: ampper :: Replies: 2 :: Views: 2305
Must be a small question.
I wan to know how to impliment Two point calibration and slope/Offset calculation.
If you have a temperature sensor and you like to calibrate it with two know temperatur levels. There must me some error or difference in the known values and the value given by your sensor.
in software calibration the soft
Microcontrollers :: 21.08.2007 05:16 :: sadat007 :: Replies: 0 :: Views: 2148
The key parameter for EKV is 'n', the slope factor. Our foundry gives us S, the subthreshold slope, which can be converted to n by S=ln(10)*n*Ut. The rest of the parameters for calculating Ispec are process parameters which are easily obtained from the model card. Then I size my devices according to weak and strong inversion I-V equations. How did
Analog IC Design and Layout :: 27.04.2009 21:42 :: oermens :: Replies: 5 :: Views: 2202
dx(t)/dt denotes the slope of the signal x(t), obtain an expression for the highest allowable slope of the signal in terms of modulation parameters (modulation frequency and step size)
And explain two possible methods to prevent from the slope overloading problem using the derived expression.
but one solution will lead to another (...)
Digital Signal Processing :: 29.06.2009 18:12 :: GF1080 :: Replies: 1 :: Views: 452
I need advices on noise calculation of ADC.
I'm designing a single-slope serial ADC. A two-stage comparator compares Vin with Vramp and drives an NAND-gate. The output of the NAND gate then activates a counter. The counter operates at much higher frequency than the -3dB freq of the compartor.
I want to calculate the thermal noise of t
Analog Circuit Design :: 28.11.2009 21:56 :: noleeach :: Replies: 0 :: Views: 1119
Baseband ripple comes from the unavoidable current ripple
(VIN, L) triangle wave as filtered by the output caps. It
doesn't have to do with the control loop. But an unstable
control loop or one that is busy with subharmonic activity
can be much worse than baseband ripple.
In surrent mode control, slope compensation is needed to
quench a f/2 subha
Power Electronics :: 03.01.2012 11:07 :: dick_freebird :: Replies: 9 :: Views: 460
Nominal Resolution of dual-slope ADC is usually referring to the resolution of the time measurement of de-integration phase and is simply given by your hardware design. Usable resolution is a matter of various error terms and more difficult to determine. Ponts to consider are
- integration capacitor loss factor
- comparator response time
Analog Circuit Design :: 22.09.2012 10:54 :: FvM :: Replies: 2 :: Views: 522
Your datasheet shows a straight-line for Characterstics curve.
Straight line has equation y=mx+c
slope (Δy/Δx) = (2.970-0.990)/(90-30) = 0.033 // from Standard characterstics table.
check with substitutions,
c = 0
c = 0
Both of passing throu
Microcontrollers :: 23.08.2013 07:01 :: Raady Here :: Replies: 3 :: Views: 223
It can be runned .Tran analyse with a slow and slope input. It also run .DC analyse and sweep vin.
Analog Circuit Design :: 29.05.2005 05:10 :: staric :: Replies: 4 :: Views: 2863
There is another way to plot gm of one device, however. But for equal gm (Gm) calculation of a specified structure you can measure its slope by using .measure statement and DERIV keyword (or something like that) to calculate the derivative (or slope) of your parameter 'Id/Vgs'. you can name your measurement in your netlist and write the (...)
Analog Circuit Design :: 02.06.2005 04:46 :: ezt :: Replies: 5 :: Views: 4044
well ,, you can make sweep by simulation ,,and measure the slope of drain current in the saturation region,, this vakue will be 1/ro and ro=1/(lamda*Id)
Analog IC Design and Layout :: 04.05.2006 15:01 :: husseinadel :: Replies: 6 :: Views: 3010
Yeah the math is not so complex for us, but you should consider cleaning up noises...e.g on a bumpy road, accelerometer tends to make fail calculation. You can compensate this thou, but like I said, the math will be complicated.
Complicated math that I mean is the real world math, not just v=a*t
Easily you can compensate using Newton's law:
Electronic Elementary Questions :: 02.03.2008 20:50 :: rikie_rizza :: Replies: 19 :: Views: 27931
100 dB = gain of 100k. So first -3 dB point is around 10M/100k = 100 Hz. I asume that the 10 MHz bandwidth is based on the slope of the first pole.
So around 1kHz to 1 MHz you have a 90 degrees phase shift.
55 degrees phase margin (at unity gain I guess) means that the second pole introduces a phase shift of 180-90-55 = 35 degree
Analog Circuit Design :: 30.04.2010 13:39 :: WimRFP :: Replies: 2 :: Views: 672
I am trying to understand the effect on channel length modulation (CLM) in short channel devices esp. the effect on output resistance. In Razavi chap 16 , there is an equation for calculation for ro based on which ro increases with Vds due to CLM. I assume velocity saturation is also taken into account in this equation
Can someone throw light on
Analog Circuit Design :: 02.08.2011 21:08 :: analogartist :: Replies: 0 :: Views: 869
but these are very high values right ....??
have i done any mistake in calculation of maximum slope??
SR+ =229e6 = 229 V/?s which means 7.64ns for your 1.75V step. Zoom into one of your step edges and verify!
Analog IC Design and Layout :: 18.08.2011 06:29 :: erikl :: Replies: 5 :: Views: 1126
The dual transistor circuit is shown in the literature posted by Goldsmith on page 9.
The output of the simple one-transistor circuit is -26 mV * ln(I1/Is), with Is being a transistor parameter. The 26 mV slope is valid for 25°C and proportional to absolute temperature T = t +273°. You'll find more calculation details in the literature.
Analog Circuit Design :: 02.11.2011 11:58 :: FvM :: Replies: 6 :: Views: 578
I would suggest that you try to extract the Kp and Kn instead, you will probably also need the slope factor n. Try to extract Kp,Kn for different values of W/L and see how they vary. Perhaps you could use an average value of the results for the Kp,Kn
I would also be very reserved with the hand calculated results if you intend to use the quadratic
Analog Circuit Design :: 25.01.2013 09:55 :: helpmejerry :: Replies: 3 :: Views: 343
Well if you're just simulating, then it should be a matter of getting the raw data and dumping it into matlab, then doing an FFT. Or you could build the simulation entirely in matlab. Try to make sure that either the duration of the sampled data is an exact integer multiple of your fundamental period, otherwise you'll end up with an incorrect resul
Power Electronics :: 03.04.2013 08:48 :: mtwieg :: Replies: 5 :: Views: 425