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35 Threads found on edaboard.com: **Slope Factor**

Hi all,
is this method is valid for calculating n from week to strong inversion?
or is there any alternate
i need to calculate n(**slope** **factor**) to find technology current.
Thanks

Analog IC Design and Layout :: 17.05.2007 10:22 :: Blackuni :: Replies: **0** :: Views: **823**

When you trace an Id-Vg @ Vd=contant courve of a MOSTand you draw it on a logarithmic vertical scale, you will notice that, for Vg < Vth, the Id current (in the log scale) increases linearly with Vg. The **slope** of this section of the couve is called the WI **slope** or, more exactly, the inverse **slope**.
It tells you how ideal your transistor (...)

Analog Circuit Design :: 08.04.2005 03:15 :: Humungus :: Replies: **1** :: Views: **1550**

Some fabs give Subthreshold **slope** S rather than Subthreshold **slope** **factor** n. You can see here how to convert between the two:

Analog IC Design and Layout :: 25.08.2011 07:44 :: oermens :: Replies: **12** :: Views: **1168**

These are ordinary quarter wave transmission lines. They are sometimes made slightly shorter so that the capacitor between the open end and ground can change the resonant frequency. The reactance **slope** is determined by the loaded Q. You control this with the source and load impedance.

RF, Microwave, Antennas and Optics :: 17.10.2004 22:14 :: flatulent :: Replies: **2** :: Views: **1249**

Plot the Vds vs. Id characteristic of the device.The **slope** of the curve (in saturation region) will give the Ron of the device in saturation.Derive the expression for the Ron of the transistor in saturation and equate it to the measured Ron.Substitute for mu, cox etc and u will be able to calculate lambda.
Regards,
Dhasmana.

Analog Circuit Design :: 05.04.2007 11:06 :: dhasmana :: Replies: **9** :: Views: **7652**

Hello All,
I am trying to extract the source-bulk junction capacitance using eldo. The model I have is BSIM3v3 and the confusion is as follows:
There are two capacitances between the source and bulk
1. Intrinsic CSB which is due to the bulk charge.
2. Extrinsic CSB which is due to the junction between the source and bulk
How do I sepa

Analog Circuit Design :: 03.05.2007 04:12 :: e.Horus :: Replies: **0** :: Views: **906**

Hello,
integration period is actually related to signal frequency, cause i supresses frequencies with a period equal to integration period and it's integer mutiples. It has been often used with 100 ms or 20 respectively 16.7 ms period to suppress mains interferences. Cause it needs a time-to-digital converter with sufficient relative solution, i

Analog Circuit Design :: 21.02.2008 13:23 :: FvM :: Replies: **2** :: Views: **812**

To shady205,
It is may be too late, but I just found your question. There is one easy way to determine the Q-**factor** of your filter. It is equal to ABS(tan(phi)), where phi is the phase angle. By another words Q-**factor** is the **slope** of filter?s phase characteristic. Do not forget that phase must be in radians and frequency in Hertz. To (...)

Analog IC Design and Layout :: 17.06.2008 12:37 :: RF-OM :: Replies: **24** :: Views: **4312**

Dear all:
I'd like to consult a question about reactance **slope** parameter.
I do not understant how to define the parameter.
As we know, reactance **slope** parameter x=ωo/2*(dX(ω)/dω) when ω=ωo.
Based on the classical microwave passive book written by Rizzi.
It can be treated as Energy stored in the resonant circu

RF, Microwave, Antennas and Optics :: 26.09.2008 03:51 :: YCChiou :: Replies: **0** :: Views: **1540**

The key parameter for EKV is 'n', the **slope** **factor**. Our foundry gives us S, the subthreshold **slope**, which can be converted to n by S=ln(10)*n*Ut. The rest of the parameters for calculating Ispec are process parameters which are easily obtained from the model card. Then I size my devices according to weak and strong inversion I-V equations. (...)

Analog IC Design and Layout :: 27.04.2009 21:42 :: oermens :: Replies: **5** :: Views: **2202**

simulate ids-vgs curve, plot ids on log scale, measure the change in vgs for current to increase by one decade, this is called subthreshold **slope** S. the relation between S and n is \dfrac{1}{S}=\ln 10 \times n \times U_t. typical value for S is maybe between 80 mV and 90 mV in 130 nm process.

Analog IC Design and Layout :: 20.08.2010 14:50 :: oermens :: Replies: **5** :: Views: **1423**

The "n" you are describing is not subthreshold **slope** parameter of EKV model, see pg 194.
n=1 Junction emission coefficient.
bsim model does not calculate **slope** parameter, specific current, etc. that you are looking for, they must be approximated/derived from given

Analog IC Design and Layout :: 30.10.2010 10:27 :: oermens :: Replies: **16** :: Views: **1551**

The datasheets are specifying a resistance range for a specific illumination, mostly 10 lux. The variation is typically +/- 50%. Furthermore they specify a logarithmitic **slope** **factor** γ, so you are able to calculate the resistance at different luminance levels. You won't get more accurate data, because the nature of these sensors apparently doe

Analog Circuit Design :: 02.11.2010 04:44 :: FvM :: Replies: **4** :: Views: **792**

Hi
From Pozar, I know that Q=beta/(2*alpha) = pi/(4*alpha*length); ---valid for short circuited transmision lines
and from resonant theory (parallel resoant circuit) Q= **slope**(imag) * fo /(2R).
I am using ADS, I use 2 port simulation to extract alpha and beta..and find Q?? or use one port simualtion to extract Q??
Which one is valid??

RF, Microwave, Antennas and Optics :: 14.03.2011 12:51 :: venu.gongal :: Replies: **0** :: Views: **269**

Hi
From Pozar, I know that Q=beta/(2*alpha) = pi/(4*alpha*length); ---valid for short circuited transmision lines
and from resonant theory (parallel resoant circuit) Q= **slope**(imag) * fo /(2R).
I am using ADS, I use 2 port simulation to extract alpha and beta..and find Q?? or use one port simualtion to extract Q??
Which one is valid??

Electromagnetic Design and Simulation :: 15.03.2011 12:34 :: venu.gongal :: Replies: **5** :: Views: **928**

Hi
I'm confused with NMOS and PMOS transistors in subthreshold region.
Which of them has the higher current value, for a given value of Vgs?
Which of them has the higher subthreshold **slope**?
Which of them has the higher value of threshold voltage?
I'm working with 90nm Tech.
Rosa

Analog Circuit Design :: 06.07.2011 11:49 :: rosaeidi :: Replies: **1** :: Views: **1377**

Nominal Resolution of dual-**slope** ADC is usually referring to the resolution of the time measurement of de-integration phase and is simply given by your hardware design. Usable resolution is a matter of various error terms and more difficult to determine. Ponts to consider are
- integration capacitor loss **factor**
- comparator response time

Analog Circuit Design :: 22.09.2012 10:54 :: FvM :: Replies: **2** :: Views: **522**

I would suggest that you try to extract the Kp and Kn instead, you will probably also need the **slope** **factor** n. Try to extract Kp,Kn for different values of W/L and see how they vary. Perhaps you could use an average value of the results for the Kp,Kn
I would also be very reserved with the hand calculated results if you intend to use the quadratic

Analog Circuit Design :: 25.01.2013 09:55 :: helpmejerry :: Replies: **3** :: Views: **344**

Sorry...all this magnetisation characteristics are given under the topic DC Shunt Generator...
In DC shunt generator the field and armature circuit are in parallel.
Now say E is the generated armature EMF.
E=KΦω, where Φ is field flux and ω is generator speed or turbine speed and K is a proportionali

Electronic Elementary Questions :: 20.01.2005 08:58 :: usernam :: Replies: **7** :: Views: **12514**

hi
suppose i go for cross connection of diff pairs then what shud be the separation of neighbouring voltage references to have good interpolation. just for example take a 6 bit folding adc 3/3 then for 8 folding **factor** what shud be the **slope**, the value of resistance?
i have a folding amplifer with f=8 but the problem is there is a tapering the

Analog IC Design and Layout :: 14.08.2005 16:06 :: Karthikeya :: Replies: **7** :: Views: **1007**

Modifying geometry, only change max. and min. capacitance values, also quality **factor**.
does exists any way to change C-V **slope** for accumulation varactor ??
I want to decrease its **slope**, because the gain of linear region is so high, and very small signal would be enough to change capacitance a lot, maybe undesirabilly.

Analog IC Design and Layout :: 29.09.2005 23:20 :: mazelk :: Replies: **5** :: Views: **1257**

Slew rate is basically how fast an opamp can swing its output. It turns out that when you apply a very fast large-signal transient (like a step voltage) the opamp can't "keep up". The limiting **factor** is often an internal capacitance that is charged by a constant current (when we turn a differential pair completely on, it acts like a constant curren

Electronic Elementary Questions :: 11.04.2006 00:28 :: lladnar23 :: Replies: **2** :: Views: **2466**

We'll the **slope** of the load line dpends on you load resistance. I think it's -1/R but you'll have to draw it out. Anyway if you plot the load line over the IV curves the point is to adjust the load (to change the **slope**) and drive level (length of line) until the left end hits the point of maximum current (until it rolls off the knee) and the righ

RF, Microwave, Antennas and Optics :: 17.08.2006 17:46 :: madengr :: Replies: **2** :: Views: **2270**

you cant determine exact lambda value, because its a function of L and other device parameters.but to determine an avg value plot V-I curves, and find the **slope**

Analog Circuit Design :: 20.08.2007 03:39 :: rajanarender_suram :: Replies: **4** :: Views: **1574**

the reason for this lies in bode plot.bode plot is linearized of the actual curve. the maximum error lies at a point where the two **slope** curve (say horizontal and -20db **slope** line) meet. the error b/w ideal and bode plot at this point is maximum and is -3db.
thus 3db point denotes the frequency at which the roll over stats.
hock

Analog Circuit Design :: 02.01.2009 00:02 :: hock :: Replies: **12** :: Views: **10699**

For any FET, there should be one "magic" point where
Vgs is relatively constant. This beats the subthreshold **slope**
change against the VT change for a net null. I would not expect
it to be fabulously consistent, but play around with a FET at a few
different current densities, across temp and you may see
what I'm talking about.
Then you only

Analog Circuit Design :: 14.01.2010 19:46 :: dick_freebird :: Replies: **3** :: Views: **820**

I want to integrate dc current in a range between 18u and 20u. The refrence voltage has no importance when using the ideal op_amp. But if used an op_amp that i designed by my self it will represent the common mode voltage at which my circuit is working.Notice that I first used a telescopic op_amp that I designed by my self but when it didn't work I

Electronic Elementary Questions :: 14.06.2010 16:15 :: Marina_fekry :: Replies: **5** :: Views: **519**

I don't know "sedra" but the maximum **slope** of a sine wave is the derivative of Vp*sin(wt) which has a maximum value of w*Vp = 2*pi()*f*Vp.
Keith.

Electronic Elementary Questions :: 08.07.2010 10:55 :: keith1200rs :: Replies: **5** :: Views: **508**

A capacitor should be added at the output node of the Buck. In a steady state, the output voltage is constant if voltage ripple is supposed small enough. Then when the switch is turned on, the voltage drop on the inductor is VIN-VO. Here, VIN is the input voltage, and VO is the output voltage. According to di/dt=(VIN-VO)/L, so di/dt is close to a c

Power Electronics :: 06.01.2011 02:18 :: leo_o2 :: Replies: **4** :: Views: **403**

Oshaye, because of the bad quality of the 2nd picture I can detect only two curves.
Nevertheless, a 4th order lowpass always exhibits a maximum phase shift of 360 deg (4x90 deg). This is not surprising at all. The **slope** of the phase characteristic in the pole frequency region is always proportional to the pole quality **factor**. Thus, for diffe

Analog Circuit Design :: 11.04.2011 02:57 :: LvW :: Replies: **3** :: Views: **375**

IBIS models are only covering I/V curves and transient output waveforms of I/O pins. If you are interested in driver impedances, they have all available information.
I know IBIS models give you I/V curves for the buffer. Can I just use the **slope** of the pull-up curve and use that as the on resistance, or is there a more accurate way?[/QUOT

Professional Hardware and Electronics Design :: 25.08.2011 17:00 :: FvM :: Replies: **3** :: Views: **803**

1) To get an 8 bit output we need to count the highs on the itstream for 255 clock periods.
2) It does not matter where in the bitstream we start counting.
That's basically correct, the '1' density is representing the input voltage. In contrast to a simple counter, a first order CIC decimator is working as an accumalator for fracti

Digital Signal Processing :: 19.05.2012 08:16 :: FvM :: Replies: **13** :: Views: **645**

there is not any quality **factor** given but i think we can find it from the information of this question!
Fine, if you can find it ! (I don't know how).
Therefore, as a first attempt I would simply propose to use an active first-order highpass (1 MHz) and an active first-order lowpass 100MHz) in series.
That

Electronic Elementary Questions :: 15.06.2012 08:23 :: LvW :: Replies: **5** :: Views: **376**

With a square wave UPS, there is not the nice gradual
sine **slope** for a differentiator-based peak detector to
work from; this is the scheme I recall using for SCR
motor drives, some decades back, anyway. The time
base probably needs some thinking if it's supposed to
be direct-mains.
Me, I think I'd rectify and filter (forgetting power
**factor** for

Power Electronics :: 04.12.2012 12:47 :: dick_freebird :: Replies: **7** :: Views: **1071**

Logic outputs are essentially non-linear. If you refer to CMOS outputs, it's usually reasonable to determine the dV/dI **slope** near the high and low level as a small-signal impedance value when determining optimal transmission line matching. You should be aware that the slow and fast technology edges are apart impedance-wise at least by a **factor** of t

PCB Routing Schematic Layout software and Simulation :: 24.12.2012 08:23 :: FvM :: Replies: **4** :: Views: **441**

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