| Search found 343 matches on edaboard.com: source follower source follower source follower super source follower follower |
class ab output stage - request for resources
hi,i need to design a class ab output stage. it could be a source follower output stage or a common source output stage.. but the main criteria is class ab operation. i would really appreciate it if someone could post schematics of it including the b...
Analog IC Design & Layout :: 14 Nov 2009 8:58 :: g.s.javed :: Replies: 3 :: Views: 237
what's the drawback of mosfet cap for miller compensation
hi, allive designed a buffer for a reference voltage in standard cmos process. the buffer used a 2-stage miller compensation opamp followed a source follower (the follower feed back to opamp neg), and the output is a follower replica.my problem is th...
Analog Circuit Design :: 29 Oct 2009 21:32 :: snafflekid :: Replies: 6 :: Views: 378
opamp input transistor corner variation
i use 0.18um cmos process to design my opamp, and the telescopic structure with nmos input transistor is used. the body of input transistor is connected to gnd, however i find that when i do corner simulation, the opamp works abnormally at some corne...
Analog Circuit Design :: 24 Oct 2009 23:19 :: dick_freebird :: Replies: 3 :: Views: 120
how to design a digital switch to match 50 ohm or 75 ohm rl?
have a question on a analog design project. in this project, i need to design an amplifier that can match 50 ohm or75 ohm output impedance by using a digital switch. im considering using a source follower output stage. by changing thebias ...
Analog IC Design & Layout :: 22 Oct 2009 7:01 :: wizardz :: Replies: 2 :: Views: 165
how to design a digital switch to match 50 ohm or 75 ohm rl?
have a question on a analog design project. in this project, i need to design an amplifier that can match 50 ohm or75 ohm output impedance by using a digital switch. im considering using a source follower output stage. by changing thebias ...
Analog Circuit Design :: 21 Oct 2009 3:00 :: wizardz :: Replies: 3 :: Views: 144
asic cmos opamp design
hi guyz,the following is my design problem.need to design a cmos opamp in the tsmc 0.35um process. supply voltage is 3.3vsome of the design considerations are as follows:1. the opamp will be set-up in the non-inverting configuration.2. high open loop...
Analog IC Design & Layout :: 05 Oct 2009 6:21 :: carporsche :: Replies: 8 :: Views: 465
bandgap with 60db of psrr at 1mhz
hi,im trying to design a bandgap with a pretty high psrr at high frequency (for a switching regulator which frequency can go up to 1mhz). ive tried a pre-regulation, ive tried voltage subtraction, but the best i get is 30db at 1mhz.any ideas on what ...
Analog IC Design & Layout :: 01 Oct 2009 6:11 :: saro_k_82 :: Replies: 4 :: Views: 171
problem with inl/dnl
designed a flash adc and now i want to test it. but ive some problems with inl/dnl calculation due to the using of tha!i used of track and hold amplifier (tha; a track and hold which is followed by a source follower as a buffer), besides input of adc...
Analog IC Design & Layout :: 29 Sep 2009 12:34 :: shanmei :: Replies: 10 :: Views: 375
how to realize a 0.5v output ldo ?
dear all,i want to design a ldo with 0.5v output. as i know, the output voltage is derived from the bandgap voltage by res devider. so it is easy to realize a ldo with output > 1.2v. but how to realize a 0.5v ldo? could you give me some tips or pape...
Analog IC Design & Layout :: 27 Sep 2009 16:02 :: dick_freebird :: Replies: 4 :: Views: 177
how to generate negative voltage?
ut current is about 100ma through this voltage. except the charge pump chip, how can i realize a negative voltage with simple method on pcb? #2.i also need a big size mosfet (power transistor?) with source follower connection for my test chips power...
Analog Circuit Design :: 23 Sep 2009 7:08 :: FvM :: Replies: 2 :: Views: 333
current mirror design
hi all.i was wondering if anyone knows what the best way of achieving low input impedance and high output impedance in a cmos current mirror? the input of the current mirror is connected to the output of a current steering dac, and the output of the ...
Analog Circuit Design :: 21 Sep 2009 11:24 :: eld03 :: Replies: 3 :: Views: 513
can anyone tell whether the program is correct..
can any one help me... i feel the following program in not complete...the program executes with two warnings...but i don get any out put from the mc....some one pls tell me whether the program is correct and if it is complete(htis program was not wri...
Microcontrollers :: 20 Sep 2009 4:50 :: nirmal_rockin :: Replies: 1 :: Views: 132
adc input buffer in 0.18um cmos
hi,i want to drive the bootstrapped switch track and hold circuit for a 1.5gs/s, 8 bit cmos adc. for 0.18um cmos process, normal source follower buffer has linearity and gain drawbacks because mos transistors output conductance is strongly nonlinear ...
Analog IC Design & Layout :: 09 Sep 2009 18:37 :: dick_freebird :: Replies: 1 :: Views: 201
no output from the enable pins....pls help
don get any output from both the enable pins(pins 18 and 19 of the mc). due to wch the motor refuses to. run... nw im confused how to resolve this problem...any one help pls...i hav also attached the source code for the mc...http://img29.imageshack.u...
Microcontrollers :: 09 Sep 2009 16:46 :: nirmal_rockin :: Replies: 0 :: Views: 90
connecting bulk and source of an nmos for a non-rf applicati
which has to switch on and off approximately 30 times per second. the amplifier is a folded cascode opamp with 2 gain boosting stages. when i run simulations, i get very good results for the bulk and source for all transistors connected together. now...
Analog IC Design & Layout :: 03 Sep 2009 21:40 :: dick_freebird :: Replies: 2 :: Views: 171
c-program compiling for microcontroller...pls help....
hi...im in urgent need.. i got this program somewher from the net and ive edited it for my line follower which im building....but the program shows some errors(the microcontroller used is atmega16) and im totally confused about the header files delay...
Microcontrollers :: 02 Sep 2009 15:11 :: nirmal_rockin :: Replies: 4 :: Views: 156
vco phase noise measurement with spectrum analyzer
i was trying to measure vco phase noise with agilent n9320b spectrum analyzer. my problem is that whenever i connect my vco output to the rf input of the analyzer, the signal on the oscilloscope is gone as my signal swing is reduced from 0-3.3v to ab...
RF, Microwave, Antennas and Optics :: 21 Aug 2009 22:32 :: vfone :: Replies: 1 :: Views: 345
charge pump based ldo
anybody knows how to design charge pump based ldo with nmos as drop-out element ? please suggest some papers....
Analog IC Design & Layout :: 19 Aug 2009 9:08 :: mitgrace :: Replies: 5 :: Views: 516
differential amplifier with source follower
hello,look at my attachment. the output x01_in+ is shifted 180° from the input a. how to make sure so that this shifting is as low as possible? thx...
Analog IC Design & Layout :: 12 Aug 2009 18:27 :: Teddy :: Replies: 3 :: Views: 261
level shifter circuit :
hi ppl !!i am looking for a cmos circuit which will convert cmos 3.3 v supply logicto cmos 1.2 v supply logic. can anybody help me out in this regard.tiaraduga...
Analog IC Design & Layout :: 01 Aug 2009 19:01 :: nadigsharma :: Replies: 7 :: Views: 1095
how to translate signal to a different voltage level
greetings,i am an amateur in this things and i am stuck with this problem:i want to interface a signal to an adc, but the signal is outside the limits of my adc. so, what i am trying to do is basically, without altering the original signal to run it ...
Electronic Elementary Questions :: 29 Jul 2009 9:35 :: rituparnasaikia :: Replies: 6 :: Views: 588
how to compensate super source follower?
hi, im doing a project now using super source follower, besides itself is a negtive feedback system, it is also in a bigger loop( you can find this paper naminga transient-enhanced low-quiescent current low-dropout regulator with buffer impedance a...
Analog IC Design & Layout :: 24 Jul 2009 11:49 :: jesseyu1984918 :: Replies: 0 :: Views: 144
how to compensate a super source follower?
hi, im doing a project now using super source follower, besides itself is a negtive feedback system, it is also in a bigger loop( you can find this paper naminga transient-enhanced low-quiescent current low-dropout regulator with buffer impedance a...
Analog Circuit Design :: 24 Jul 2009 11:47 :: jesseyu1984918 :: Replies: 0 :: Views: 144
related to inverter
in an inverter we connect pmos to vdd, nmos to gnd...wht happens if we do viceversa??i.e pmos to gnd or vss, and nmos to vdd ? will it still function as inverter??if so why??...
Analog IC Design & Layout :: 20 Jul 2009 20:32 :: sandeep_torgal :: Replies: 11 :: Views: 435
how to design vco buffer amplifer?
please give me some advice on how to design vco buffer.i desined a 4~8ghz vco without buffer desined in 2um hbt process.,it works well,but i need a 4~8ghz vco buffer.is a attenuator needed? i dont think insert a attenuator between vco and the buffer ...
RF, Microwave, Antennas and Optics :: 16 Jul 2009 5:14 :: du_hast :: Replies: 9 :: Views: 732
mosfet turning completely on
i seem to be having a problem turning on a mosfet completely. i am using a 2n7000 n-channel mosfet hooked up to a logic gate which is controlling the gate of the mosfet. however, the logic seems to be unable to turn on the mosfet all the way. until t...
Electronic Elementary Questions :: 16 Jul 2009 2:22 :: Audioguru :: Replies: 6 :: Views: 585
help needed in making a stable opamp with big load
hi,im making rail to rail opamp for buffer.the buffer will have big load(10nf) or no load.my current design structure of opamp is two stage opamp.first stage is gain stage(diff amp) and second stage is for rail to rail buffer.i think dominant pole is...
Analog Circuit Design :: 10 Jul 2009 2:40 :: sutapanaki :: Replies: 28 :: Views: 1226
opamp integrator with fast current pulse input
im trying to determine if an opamp, such as lm124, can integrate the current of a very fast pulse. i am simulating the circuit in pspice. the problem is that the voltage proportional to the integral is appearing at the input rather than the output. ...
Analog Circuit Design :: 17 Jun 2009 10:31 :: joker12 :: Replies: 10 :: Views: 1416
need help in sample and hold design
i desinged a sample hold circuit for adc. if i input 1v vpp, i cannot get 1v vpp from output. but if i input 500mv vpp, i can get correct sampled 500mv vpp from output. what is the reason caused this problem? not enough gain or not enough output swin...
Analog IC Design & Layout :: 16 Jun 2009 5:37 :: mdcui :: Replies: 5 :: Views: 390
power supply rejection analysis of ldo regulators
hi everybody,i used cadence to simulate two designs of linear regulators... one used a pmos device as the pass transistor while the other used a nmos pass transistor. the error amplifier had same gain. the plot of psr show that there is a peaking in ...
Analog Circuit Design :: 04 Jun 2009 14:07 :: onteri :: Replies: 2 :: Views: 387
how to test the input impedance of a voltage follower?
hi! guys, i got a voltage follower which was formed by connecting the inverting input to the output of opam opa128 ,say a unit gain amplifier. is there any effective&pratical way to test the input impedance of it? not long ago i ...
Analog Circuit Design :: 03 Jun 2009 11:39 :: wyckaka :: Replies: 0 :: Views: 159
a question that is about source follower and body effect!
hi, every body,i have a question that is about the source follower (common-drain amplifier) and body effect. why does increasing the output bias level can reduce the percentage of source to bulk voltage due to the signal? could everybody explain the ...
Analog Circuit Design :: 01 Jun 2009 18:03 :: davison7 :: Replies: 1 :: Views: 192
jfet source follower gain problem
hi,ive been attempting to simulate a jfet source follower (common drain) and was expecting to get something near to a gain of 1. i understand that i would never get a gain of exactly 1, but near enough. however, i was getting nowhere near. more li...
Analog Circuit Design :: 30 May 2009 9:02 :: FvM :: Replies: 21 :: Views: 1287
how to make a unit gain amplifier ???
hi all i am working on my masters project on phase lock loop . i have to make a unit gain amplifier to include it in my charge pump design . i was wondering how to make it with few complications . also can i use 2 inverters connected in series ??? i ...
Analog Circuit Design :: 23 May 2009 22:32 :: FvM :: Replies: 18 :: Views: 1272
high input impedance opamp gain choices
hi,when designing opamp based low noise amplifiers, is it better to have only one amplifier providing a high input impedance and the gain, or is it better to add another opamp to provide the gain?my situation is that i am designing a high input imped...
Analog Circuit Design :: 13 May 2009 14:04 :: philwinder :: Replies: 6 :: Views: 459
voltage level shifter design
hi, i need a cmos voltage level shifter circuit which shifts *exactly* 400 mv on a dc analog signal.i thought about voltage adder/substractor circuit but they are not applicable because of the resistors.does anybody have an idea how to shift exactly ...
Analog Circuit Design :: 07 May 2009 16:43 :: krivan :: Replies: 2 :: Views: 543
help to explain the super source follower operation theory
it is recently that i studied the analog circuits design with the text book analysis and design of analog integrated circuits. it mentions a circuit that is the super source follower of this book at the chapter 3. but it focus on the circuit characte...
Analog Circuit Design :: 20 Apr 2009 11:26 :: davison7 :: Replies: 0 :: Views: 330
jittered clock generating with cadence analoglib components
hi all,how to generate a jiitered clock signal using analoglib vpulse (or vsin) ?i need such a signal to determine the maximum jitter supported by the flip flops.is there another techniques to determine this maximum jitter supported.thanks in advance...
Analog IC Design & Layout :: 16 Apr 2009 13:06 :: erikl :: Replies: 7 :: Views: 462
challenging mos amplifier
hi all,ive got the following specs for the design of source follower. ive been tryin it for last several days but unable to meet the specs. please try and help with this. im using tsmc librarytechnology details:lmin = 350nmvdd=3.3vspecsoutput impedan...
Analog IC Design & Layout :: 23 Mar 2009 21:47 :: erikl :: Replies: 1 :: Views: 225
cmos image sensor source follower drive strength??
hi everyone,anayone who has worked with imagers please answer this question.a question relating to the source follower that is present in a pixel of a cmos imager. how much capacitive load can this pixel source follower drive. the technology is umc 1...
Analog IC Design & Layout :: 05 Mar 2009 19:41 :: hacksgen :: Replies: 0 :: Views: 177
question about the design of inverter
i want to use an inverter as an sense amplifier. in order to have larger gain, i want to work the nmos and pmos in subthreshold region. but i dont want to lower the vdd voltage, since it would affect the output range directly.my question is how can i...
Analog IC Design & Layout :: 25 Feb 2009 20:22 :: sapphire :: Replies: 7 :: Views: 504
[help] lna & mixer test in receiver design.
in the receiver front end, there is no need for matching between lna and mixer. after tapout, i need to test the chip to verify the design, then i need to test the lna and mixer individually. since all the measurement equiments have 50ohm impedence, ...
RF, Microwave, Antennas and Optics :: 18 Feb 2009 16:35 :: guilinwxb :: Replies: 26 :: Views: 1881
source follower buffer...
can anybody please elaborate the mathematics involved in the source follower buffer circuit....?? on changing the gate voltage of m1 ...how is the source voltage of m1 following it...?which type of feedback is this..(feedback topology)...?...
Analog IC Design & Layout :: 14 Feb 2009 7:47 :: se3 :: Replies: 1 :: Views: 261
self oscillating class d
here is the simplified schema of a self-oscillating class d amplifier. http://images.elektroda.net/23_1232916064.gifcan anyone explain it to me how this circuit work. maybe some intuitive approach help me understand this circuit....
Electronic Elementary Questions :: 01 Feb 2009 19:40 :: svhb :: Replies: 15 :: Views: 2826
adc for cmos image sensor
hi guys,i would like to know what all i have to consider while designing an adc for cmos image sensor. the image sensor is to be used in industrial applications or cinematic high definition applications. the image sensor will have an array of 4000x30...
Analog Circuit Design :: 27 Jan 2009 21:48 :: Pierrot Lafouine :: Replies: 6 :: Views: 1371
bandgap reference - need suggestions on the topology
hi : i am trying to design a bandgap , and the topology is like below , the supply voltage is between 2.4 to 5.8 (v) , and i use .6um process the temperature is vary from -40 to 130 degree the opamp that i used has 75 (db) gain and 60...
Analog Circuit Design :: 13 Jan 2009 9:09 :: cougar168 :: Replies: 10 :: Views: 987
voltage follower troubles
http://farm4.static.flickr.com/3202/3150881274_2ea633f63d_o.pngi am building the above circuit at the moment. the basic operation is this: the two analogue voltages induced across the photodiodes are compared by ic17a whilst ic7a passes the highest v...
Analog Circuit Design :: 30 Dec 2008 16:57 :: FvM :: Replies: 3 :: Views: 657
anyone see this type of ring oscillator?
hi all, iv seen this ring oscillator several times , but i didnot know its performance. does anyone give me some paper about it ? thank you in advance!...
Analog IC Design & Layout :: 11 Dec 2008 8:55 :: FvM :: Replies: 13 :: Views: 996
question about bootstrap ac-coupled voltage follower
can we cancel those two caps c1 and c2 to convert bootstrap ac-coupled voltage follower to bootstrap dc-coupled voltage follower?...
Analog Circuit Design :: 09 Dec 2008 21:18 :: LvW :: Replies: 23 :: Views: 759
question about voltage follower
i have configured an op-amp as a voltage follower.the problem is when the input is 150mv the output is 880mv.is this problem related with input offset voltage, input bias current or input offset current?the voltage follower doesn’t have any gain? how...
Analog Circuit Design :: 08 Dec 2008 21:15 :: EDA_hg81 :: Replies: 13 :: Views: 1293
tran simulation about op point problem
hi, therei am running a tran sim of an opamp in ade, environment is set up as followed:a small ac signal 100uv biased with a dc voltage is added at positive input, a same dc voltage is added at negative input. the single outputs dc operating point is...
Analog Circuit Design :: 17 Nov 2008 16:27 :: LvW :: Replies: 5 :: Views: 225
unity gain buffer oa
hi, i have such a question i have to design unity gain buffer as a part of larger schematics. for this amplifier is better to be with source followers for its output stage. it hase to drive rc lp filter. but input signal is almost rail to rail. if i ...
Analog IC Design & Layout :: 10 Nov 2008 9:39 :: tyanata :: Replies: 2 :: Views: 435
cmfb for high linearity and low noise design
hi all,i am designing an opamp for audio application. the opamp needs to achieve high linearity and low noise. for high linearity, resistor type of cmfb seems to be a good candidate, but big resistors introduce noise. my question is what kind of c...
Analog Circuit Design :: 22 Oct 2008 12:01 :: danielpasti :: Replies: 14 :: Views: 681
output impedance improvment
whats the cascode current mirror output impedance and best transistor size ratio?what the best way to increase output impedance for source follower (with paper source please)....
RF, Microwave, Antennas and Optics :: 07 Oct 2008 10:08 :: vfone :: Replies: 1 :: Views: 99
source follower
dear all,i am looking for a relationship (equation) that links the bw of a source follower with its bias current.can you help me please?thanks...
Electronic Elementary Questions :: 04 Oct 2008 9:42 :: salerno :: Replies: 2 :: Views: 252
how to set drain voltage (vd)
hi all,we know that id=kw/l(vgs-vth)^2 (saturation- first order). from the equation we can get voltage at vg and vs depending on the info that we have (i.e i is fixed or w/l is fixed). from the above equation, i dont see vd term in the equation. so, ...
Analog IC Design & Layout :: 29 Sep 2008 17:52 :: sutapanaki :: Replies: 9 :: Views: 351
can anyone explain this circuit of bitscope?
dear all,i am building an oscilloscope, and i have got much help from you.here is the circuit of the bitscope in the attachment image.:arrow:now i catch on the dc/ac change and the input buffer but other circuit is confused me.thanks.[/img]...
Analog Circuit Design :: 26 Sep 2008 10:15 :: byteptr :: Replies: 1 :: Views: 210
problem with ldo design!
hi freinds!i found some problems duriny=t the design of a low dropout regulator:this regulator should have: vdropout:0.5v, so with vin 3.3v , vout must be 2.8v.the load resisttance goes from 28Ω to 2.8kΩ. the load capacitor is 2.2µfthis reg...
Analog Circuit Design :: 17 Sep 2008 11:46 :: ashish_chauhan :: Replies: 92 :: Views: 3037
is it difficult
to design a 12bit 200m pipelined adc with 1.2v power,130nm...
Analog IC Design & Layout :: 27 Aug 2008 14:39 :: ricklin :: Replies: 10 :: Views: 504
connecting 8ohm speaker without wasting signal
hi ... i have audio frequency signal and i want to play the signal on 8-ohm speaker . i use this signal in one other circuit too . if i connect the speaker directly to the signal , because of its low resistance the signal gone ! i need the matching ...
Analog Circuit Design :: 27 Aug 2008 1:16 :: Audioguru :: Replies: 6 :: Views: 147
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voltage level shifters
can someone gimme a link to read about voltage level shifters using cmos or suggest a book to read? or can someone give example circuits?...
Electronic Elementary Questions :: 26 Aug 2008 20:50 :: elrayes :: Replies: 6 :: Views: 429
buffer amplifier for test pins!
i put some test pins in my analog circuits, so i need some unit-gain buffer to drive the capacitance of the test pins. however, i found its hard to design a buffer with high input common mode range, high output swing and good precision.. so is there ...
Analog IC Design & Layout :: 26 Aug 2008 10:28 :: jecyhale :: Replies: 3 :: Views: 222
ideas for small scale asic project
hi allits my graduation projecti need to work on a small scale asic design project . i am thinking of doing a small scale complete application. i have mentor, cadence , synopsys tools available on hand. any idea would be welcome. just write whatever ...
ASIC Design Methodologies & Tools (Digital) :: 26 Aug 2008 7:01 :: ankurgupta74 :: Replies: 7 :: Views: 345
mosfet drive
hello ,i am using this circuit to drive a load which could take up to 5~250ma.i tried it out and it seems to work fine. depending on the load i tweak the opamp gain to get the desired response.any suggestions if it could be improved ?cheers...
Analog Circuit Design :: 11 Aug 2008 4:03 :: rvionics :: Replies: 7 :: Views: 303
what's the differences between the two level shifter?
the second level shifter add two pmos in the middle. in my thought, the two pmos in the middle should use smalles mosfets. but i dont understand why to add the 2 pmos? does it have any advantages? and which situation wed better select the second leve...
Analog Circuit Design :: 04 Aug 2008 13:46 :: liuyonggen_1 :: Replies: 8 :: Views: 408
from lpf to hpf
how do i configure a lpf to a hpf?and how does it works?...
Analog IC Design & Layout :: 21 Jul 2008 11:29 :: FvM :: Replies: 14 :: Views: 411
can op-amps work without symmetric power sources?
e mostly used opamp circuits (e.g., inverting amplifier, non-inverting amplifier, differentiator, integrator, difference amplifer, voltage follower, etc) would work if we dont use a symmetric voltage source (i.e., we apply a positive voltage value at...
Electronic Elementary Questions :: 19 Jul 2008 5:43 :: hkBattousai :: Replies: 11 :: Views: 600
oscillations at a phase margin of 90?
hi all,im getting a weird behavior from a negative feedback loop. with a phase margin of 90 degrees i have steady state oscillations around 5% the steady state value although i have a gain of about 60 db! any idea?...
Analog IC Design & Layout :: 16 Jul 2008 8:35 :: kisspig_84630 :: Replies: 69 :: Views: 1527
output stage of cmos image sensor's amplifier
deer all,ive designed a cmos image sensor first time.i dont know how to design the output stage cause without any information about output loading.one of my friend had told me set as 20pf cap and 1meg ohm resistor, cause this is the oscilloscopes in...
Analog Circuit Design :: 08 Jul 2008 9:24 :: Old Nick :: Replies: 4 :: Views: 405
left half and right half zero
how the left and right half zero is produced in analog circuits....
Analog IC Design & Layout :: 27 Jun 2008 9:29 :: LvW :: Replies: 10 :: Views: 357
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