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55 Threads found on Spectre Veriloga
Hi, I'm new to Verilog-A I am having convergence issues with a device I modeled in Verilog-A. When I have the device simulated in parallel with a time varying voltage source then the simulation seems to work okay. The issues arise when I try to simulate transient behaviour of my device in series with an added resistor and the voltage source in p
Cadence spectre can not accept Verilog-D. You have to use NCSim with AMS option which is called as AMS Designer. Or legacy VerMix(=spectreverilog) which is a cosimulation between spectre and Verilog-XL might be available.
Hello, I was trying to use veriloga to write a model file and simulate it in Virtuoso Cadence. When I try to simulate i get following error Missing or corrupt .oa file in cellview 'memristordesign/memristor/spectre cmos_sch cmos.sch schematic veriloga'. The OSS netlister can only process cellviews that have a valid .oa file. This file (...)
Hi all, I am trying to run monte carlo analysis on a variable, from veriloga model. I had initially done the implementation with cadence-spectre flow. below is the example of how it is achieved in cadence-spectre. I put it here, so i can explain clearly what I want. 1. included the following in veriloga (...)
I think this is best done in veriloga (which spectre digests just fine, and Cadence supports editing and view-switching). You will want to error-trap that denominator, and a poly- source / analogLib primitives kludge probably doesn't have much for that. I'd recommend to find a resistor veriloga model, off the Web, and just mess with the guts.
Hi, I tried to build a veriloga VCO phase-domain model by referring to Ken Kunder's paper. Then I have no idea how to start with, thus I set up a simple testbench as below image shown. I chose "noise" analysis and run. spectre then showed error indicating "Matrix is singular (detected at 'I0:idt0'). When I tried to remove below codes and re-
If I understand you correctly, you are just not seeing simulation results for the "ncnfet" terminals? I think I ran into that many years ago, and found I needed to put some more traditional analog element in series with the veriloga output (like a trivial 'res') to force the veriloga<->spectre interface to bring out the node data (...)
Hi all, I design 3bit idea DAC using veriloga to decode the signed binary to decimal. My purpose is change: 100 -> 4 011 -> 3 010 -> 2 001 -> 1 000 -> 0 111 -> -1 110 -> -2 101 -> -1 I used modelwriter tools in Cadence spectre to design DAC with parameter (max voltage = 4; min voltage = -3, threshold = 1). However, its result is wro
Hello everyone, I am trying to write a 2x1 multiplexer using the mems switch in veriloga. But when i try to simulate the circuit i am getting errors. ERROR (spectre-11005): Matrix is singular (detected at `out'). ERROR (spectre-16080): No DC solution found (no convergence). Here is my code. `include "disciplines.vams" `include
You can do almost anything you can conceive, in veriloga and spectre will digest it just fine; you have to create the veriloga view alongside the symbol and make sure that it is picked up by your switch / stop view list order (or by using Hierarchy Editor and config-view based simulation).
I am trying to do a mixed signal simulation with AMS under cadence\virtuoso. this is for an old testbench which was working fine with spectre simulator, but then I replace a logic block with a verilog code instead of an old one with veriloga (then I need AMS). the new Verilog block has no problem, as I am able to simulate it in a separate tes
AFAIR SPICE & spectre don't support variables in VPWLF files. Use a math tool (Excel, Matlab, ...) to evaluate the variables first, then use the CSV format to transfer the values.
I would recommend, then, that you try and dig up a veriloga version of a standard FET model (like, try Silvaco's web site) which will be somewhat human- readable and let you edit equations as you see fit. Then you need a version of SPICE, spectre, whatever that supports veriloga code blocks.
What simulator do you use ? Try few simulators, such as HSPICE, XA, spectre, eldo, ADSsim, GoldenGate, etc.... As far as my experience, I often encounter bug in HSPICE Verilog-A compiler.
When i'm running spectre simulator to simulates a circuit's behavioral model by verilog-a, this problem has occured. Any ideas?
Hello guys, I was given a component in a format (compiled veriloga is my guess) and i would like to make it a cell in virtuoso to include it in a schematic and simulate it with spectre. Do you guys know how to do that ? One told me to create a veriloga cellview then include this symbol in my schematic and then to replace the of the
hello guys, i am tryong to generate a counter which has a 10*clock period, by doing a simple verilog A code, on cadence ,spectre simulatior, but the issue is that the simulation takes sooo long time,( +20 minutes ), so is this normal? my code is : // veriloga for lte, counter, veriloga `include "constants.vams" `include (...)
Hi, I meet a problem of convergence when I use veriloga to model the SH circuit. I first use veriloga to build the model of capacitor, ideal switch and ideal opamp, but when I do the simulation with spectre, It tell me no convergence, how can I do with this problem? thx!!
Hi all I am running cadence spectre veriloga simulation using ic610 and mmsim10.1. The output shows ERROR (VACOMP-1008): cannot compile ahdlcmi module library spectre. My OS is ubuntu 11.10. Anyone can help me to solve this problem? Thanks alot Best Regards Tom
Hello, I was trying to use veriloga to write a model file and simulate it in Virtuoso Cadence. When I try to simulate i get following error Missing or corrupt .oa file in cellview 'memristordesign/memristor/spectre cmos_sch cmos.sch schematic veriloga'. The OSS netlister can only process cellviews that have a valid .oa file. This file (...)
AFAIR hierarchical netlisting is also possible within Virtuoso's ADE. Usually, netlisting uses the foll. default rep- & stopList: repList "spectre cmos_sch cmos.sch schematic veriloga ahdl" stopList "spectre veriloga" So if your memory cell has a spectre view, the stopList makes sure to netlist the (...)
I am doing a transient simulation for a sigma delta modulator and the simulation time required to complete is quite long. I have come across the "accelerated parallel simulation" option in cadence that could speed up the simulation but i am not aware of the process of setting up that option. I would appreciate some guidance on setting up APS or
Hello to everyone, It is the first time that I am designing a Sigma Delta modulator. I have started with the example (veriloga) of the 1st odrer Sigma Delta modulator provided by cadence in ahdl Library. I have performed a transient analysis (the input signal is 100KHz and is sampled with a clock 10MHz) and the modulator is working fine (I can
I use Cadence IC5141 on RHEL5.4.There is no simulator whose name is "Cadence IC5141". "Cadence IC5141" is a name of Design Framework where you can use many simulator engine such as Synopsys HSPICE, Agilent ADSsim, Agilent GoldenGate, Cadence spectre, etc. I use the ADE (spectre) to simul
I think the newer versions of Simulink/Matlab allow co-simulation with SPICE blocks, using e.g. spectre.
Hello I'm using IC5141USR5 with spectre 32bi. I'm new to Verilog A/Verilog AMS, so i created new cell, cell view "veriloga", open with Modelwriter. In there i expected to write veriloga. The header files included have extension ".h". But when i looked up the absdelay function (and others) they appear to be (...)
Cadence wants to sell you a Monte Carlo license, so don't rule out malice.... In cdsSpice we used to use gauss() and track() functions. Never peeled the lid off spectre MC setup when I had the chance.
Hi, for acedemic purposes I would like to use a custom made level 1 MOS transistor model in my spectre simulations (I am using Cadence 6.1.3). In my opinion using a verilog-a transistor model is a good solution for this, because I can adjust the transistor behaviour on equation level or is there a better way? In order to do so I built a very
Hello! I write veriloga module which must work together with BSIM model (also written by veriloga) to obtain advanced facilities in comparison with standart BSIM. In this case transistor instance is implemented by subcircuit (inline subckt ...) which include two veriloga modules: BSIM model and my module. My module must obtain (...)
IPC I believe is compuGeek for "InterProcess Communication". Probably the two simulators are not passing data cleanly, one died or concluded when the other was not done (or failed to start). Verilog signals are sometimes "too ideal" for SPICE / spectre to deal with. I tend to put 1-ohm series resistors between verilog / veriloga outputs a
How can I use instances from bmsLib, which have veriloga and verilogams views, in a spectre simulation? I added veriloga and verilogams to the beginning of my switch view list and the circuit netlists without warning/error, but the state of the instance does not change when an input is given. I can't even (...)
Hi all! I have a problem with Verilog-A modeling in spectre 6.x. I use BSIM3 model implemented in Verilog-A by Geoffrey Coram (the file was available at Silvaco and then - at Simucad site some time ago). See attached file. I have successfully used it with spectre 5.1.41. My "standard" task is to simulate MOSFET DC characteristics. Transist
In that case you can make a voltage source with a gauss()* value in each of the relevant sub-blocks and repetitively simulate (probably use ocean) and gather the results for some sort of postprocessing. *gauss(), agauss(), whatever random / stats you can find in the spectre manuals. You could also make a veriloga offset source if the anal
I am doing a top-down mixed-signal ASIC design. Now I have veriloga, functional(verilog code), schematic and config view for blocks. Do I have to use AMS designer to simulate with these views? I think spectre simulator can handle the mixed signal simulation very well since there is no verilogams view in my design. I think AMS designer is (...)
hello, everyone when i use spectre to simulation diode, chose junction model parameters, Level 1. it is said that the effective area is equal to AREA ? M, unitless. so does PJ, unitless? what does unitless mean? if the area and junction perimeter are unitless, how can i sepcify the diode properties? should i specify area PJ as well as W and L?
I am currently modeling jitter in veriloga. For this i need to generate random numbers. This model is to be run with finesim as the simulator. Can anyone suggest any way to do this as finesim does not support $random function unlike spectre?
Hi , When I simulate pss,pnoise of pll(VCO ,PFD ,Divider are written with veriloga), some error comes: Error found by spectre during periodic steady state analysis `pss'. Distributed components and components with hidden state are not allowed with this analysis -- analysis skipped. CP /home
In amplifiers, if the input signal frequency is low enough, I would suggest avoid transient sim (+DFT) or flex-balance (just like HB) in spectre(RF). The easiest way is to use DC simulation, and through veriloga function and calculator to find the Fourier series coefficients. You can obtain much more insight in DC sim and avoid possible settling
I am modeling an OTA with veriloga language. As i want a single pole system, I am using the laplace_nd function in veriloga to model the transfer function of the single pole OTA. When i simulate this model alone in spectre it gives me correct result. But when i am using this OTA in a feedback loop or connecting the output of the OTA to a (...)
Hi, Could anyone please help me running vhdl code integrated with circuits developed using spectre simulator. I need it to run in spectre itself. I ran with veriloga codes. It seems to be working along with designed circuits in spectre but then it is generating errors with vhdl. What should be the "View" name in (...)
Hi Can anyone explain how we can plot PLL transfer function(Output phase/ Input phase) using spectre and spectreRF? If there are any documents pls share. thanks.
1. There are a few kinds of cell views in Cadence design, such as schematic, symbol, spectre, veriloga, etc. Can someone tell me what's the usage of spectre view? How to create the spectre view? 2. I have only the Spice netlist of an I/O cell. I want use it in my schematic design. So I created a blank schematic for it (...)
Hello,everyone! Now I know we can use the veriloga code for adc dnl and inl simulation in cadence spectre,but how to edit the veriloga code? who can help me? my adc is 8bit 12.5Msps 1.8vpp,
There are differencies in the type of models and the syntax for HSpice ans spectre. spectre could typical run all models of HSpice but not reverse. The same applies to the netlist features. The features are Inline Subcircuit Models (I am not shure about the exact name) and veriloga and more relaxed name conventions
You should use ams simulator. It seems that you have chose spectre. spectre can only support veriloga.
I used the Verilog-A program for the for co-simulation with the spectre simulator. Generally I use it when I design some program logic along with the analog circuits. I dont know much about the Verilog-AMS
By now, I think AMS Designer is the best simulator to handle verilog(d,a, ams) and spice(spectre or hspice netlist). The ams simulator comes from Cadence.
I think the "netlist" file is the concatenation of the "netlisHeader" and "netlistFooter". So you should find the same include in the final netlist. Verilog is refenced as a subcircuit in spectre.
Hi kamesh419, Actually,it already told you the reason of errors and how to fix it in the following: ERROR: Netlister: unable to descend into any of the views defined in the view list: "spectreS cmos_sch schematic" for instance I5 in cell Add_rpl_8. Either add one of these views to: Library:MyLib Cell:GlitchAnalyzer or modify the vi
The hspice model of vcvs recognizes the max and min parameters, but the spectre model does not. If you are using spectre, you may use veriloga to model the saturation effect.