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			<div id="results_count">55 Threads found on edaboard.com: <strong>Spectre Veriloga</strong></div>
		
				<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread365745.html" rel="nofollow">Verilog-A convergence issues</a></h2></div>
			</div>
			<div class="content_text">Hi,

I'm new to Verilog-A I am having convergence issues with a device I modeled in Verilog-A. When I have the device simulated in parallel with a time varying voltage source then the simulation seems to work okay. The issues arise when I try to simulate transient behaviour of my device in series with an added resistor and the voltage source in p</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 03-22-2017 07:54 :: mr_mosfet :: Replies: <strong>2</strong> :: Views: <strong>318</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread365005.html" rel="nofollow">Verilog A module for a digital filter (Analog Interface for verilog code)</a></h2></div>
			</div>
			<div class="content_text">Hi,

I want to simulate a delta sigma modulator in Cadence <strong>spectre</strong>. I have a ctrl block in verilog-A and the main circuits in transistor level. I have also a digital filter of two cascased integrators which is defined in verilog module. Now I want to simulate this in <strong>spectre</strong>. but the problem is this digital filter works in logic levels (0,1) wher</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 03-02-2017 12:28 :: ashrafsazid :: Replies: <strong>2</strong> :: Views: <strong>503</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread357549.html" rel="nofollow">Help with VerilogA in Cadence</a></h2></div>
			</div>
			<div class="content_text">Hello,

I was trying to use <strong>veriloga</strong> to write a model file and simulate it in Virtuoso Cadence. When I try to simulate i get following error

Missing or corrupt .oa file in cellview 'memristordesign/memristor/<strong>spectre</strong> cmos_sch cmos.sch schematic <strong>veriloga</strong>'. The OSS netlister can only
process cellviews that have a valid .oa file. This file (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Software Problems, Hints and Reviews :: 07-30-2016 04:03 :: CHIPMUNK_kevin :: Replies: <strong>1</strong> :: Views: <strong>785</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread355823.html" rel="nofollow">Running Monte Carlo on VerilogA Variable with Synopsys Custom Designer</a></h2></div>
			</div>
			<div class="content_text">Hi all,
  I am trying to run monte carlo analysis on a variable, from <strong>veriloga</strong> model. 
  I had initially done the implementation with cadence-<strong>spectre</strong> flow. below is the example of how it is achieved in cadence-<strong>spectre</strong>. I put it here, so i can explain clearly what I want. 

      1. included the following in <strong>veriloga</strong> (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; ASIC Design Methodologies and Tools (Digital) :: 06-15-2016 08:27 :: aarthy_maya :: Replies: <strong>0</strong> :: Views: <strong>424</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread340423.html" rel="nofollow">Cadence Spectre - resistor dependent on equation</a></h2></div>
			</div>
			<div class="content_text">I think this is best done in <strong>veriloga</strong> (which <strong>spectre</strong> digests
just fine, and Cadence supports editing and view-switching).
You will want to error-trap that denominator, and a poly-
source / analogLib primitives kludge probably doesn't have 
much for that.

I'd recommend to find a resistor <strong>veriloga</strong> model, off the Web,
and just mess with the guts.</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 07-02-2015 23:11 :: dick_freebird :: Replies: <strong>4</strong> :: Views: <strong>577</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread334048.html" rel="nofollow">VerilogA VCO Model to Simulate Phase Noise</a></h2></div>
			</div>
			<div class="content_text">Hi,

I tried to build a <strong>veriloga</strong> VCO phase-domain model by referring to Ken Kunder's paper. Then I have no idea how to start with, thus I set up a simple testbench as below image shown. I chose "noise" analysis and run. <strong>spectre</strong> then showed error indicating "Matrix is singular (detected at 'I0:idt0'). 

When I tried to remove below codes and re-</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 03-18-2015 13:34 :: teem :: Replies: <strong>0</strong> :: Views: <strong>889</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread333425.html" rel="nofollow">Problem simulating Veriloga in spectre in cadence</a></h2></div>
			</div>
			<div class="content_text">If I understand you correctly, you are just not seeing 
simulation results for the "ncnfet" terminals? I think I
ran into that many years ago, and found I needed to 
put some more traditional analog element in series 
with the <strong>veriloga</strong> output (like a trivial 'res') to force
the <strong>veriloga</strong><-><strong>spectre</strong> interface to bring out the
node data (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-11-2015 21:23 :: dick_freebird :: Replies: <strong>9</strong> :: Views: <strong>1603</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread323472.html" rel="nofollow">Problem in design 3bit idea DAC to decode signed binary to decimal</a></h2></div>
			</div>
			<div class="content_text">Hi all,

I design 3bit idea DAC using <strong>veriloga</strong> to decode the signed binary to decimal. 
My purpose is change:
100 -> 4
011 -> 3
010 -> 2
001 -> 1
000 -> 0
111 -> -1
110 -> -2
101 -> -1

I used modelwriter tools in Cadence <strong>spectre</strong> to design DAC with parameter (max voltage = 4; min voltage = -3, threshold = 1). However, its result is wro</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 09-21-2014 02:17 :: irisaru :: Replies: <strong>0</strong> :: Views: <strong>474</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread323248.html" rel="nofollow">Convergence problem with cadence spectre</a></h2></div>
			</div>
			<div class="content_text">Hello everyone,

I am trying to write a 2x1 multiplexer using the mems switch in <strong>veriloga</strong>. But when i try to simulate the circuit i am getting errors. 

ERROR (<strong>spectre</strong>-11005): Matrix is singular (detected at `out').
ERROR (<strong>spectre</strong>-16080): No DC solution found (no convergence).  

Here is my code.
`include "disciplines.vams"
`include </div> 
			<div class="content_info">
				&nbsp;&nbsp; ASIC Design Methodologies and Tools (Digital) :: 09-17-2014 22:38 :: rajrevanth61 :: Replies: <strong>0</strong> :: Views: <strong>1130</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread320607.html" rel="nofollow">memristor component in cadence</a></h2></div>
			</div>
			<div class="content_text">You can do almost anything you can conceive, in <strong>veriloga</strong> 
and <strong>spectre</strong> will digest it just fine; you have to create the
<strong>veriloga</strong> view alongside the symbol and make sure that it
is picked up by your switch / stop view list order (or by 
using Hierarchy Editor and config-view based simulation).</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-04-2014 17:08 :: dick_freebird :: Replies: <strong>3</strong> :: Views: <strong>904</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread318126.html" rel="nofollow">Cadence AMS: netlisting failed, with no error message</a></h2></div>
			</div>
			<div class="content_text">I am trying to do a mixed signal simulation with AMS under cadence\virtuoso.

this is for an old testbench which was working fine with <strong>spectre</strong> simulator, 
but then I replace a logic block with a verilog code instead of an old one with <strong>veriloga</strong> (then I need AMS).
the new Verilog block has no problem, as I am able to simulate it in a separate tes</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-24-2014 11:32 :: ahmad.mar :: Replies: <strong>1</strong> :: Views: <strong>2383</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread311722.html" rel="nofollow">Variables in spectre's VPWLF file</a></h2></div>
			</div>
			<div class="content_text">Hi, all,
I am simulating in Cadence ADE with <strong>spectre</strong>. I use a VPWLF source to get a pwl external file as a stimula. In my <strong>spectre</strong> bench, I have set some variables(Fosc, vdd, for example). I compose the pwl file with these variables in math operations to define the pwl waveform. But when <strong>spectre</strong> is parsing, I found it doesn't recognize the (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-14-2014 06:59 :: kickoff1111 :: Replies: <strong>2</strong> :: Views: <strong>1289</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread310031.html" rel="nofollow">How to add new parameters to a MOSFET SPICE model file?</a></h2></div>
			</div>
			<div class="content_text">I would recommend, then, that you try and dig up a
<strong>veriloga</strong> version of a standard FET model (like, try
Silvaco's web site) which will be somewhat human-
readable and let you edit equations as you see fit.
Then you need a version of SPICE, <strong>spectre</strong>, whatever
that supports <strong>veriloga</strong> code blocks.</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-21-2014 18:30 :: dick_freebird :: Replies: <strong>6</strong> :: Views: <strong>1278</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread297856.html" rel="nofollow">Error in verilog A design</a></h2></div>
			</div>
			<div class="content_text">What simulator do you use ?

Try few simulators, such as HSPICE, XA, <strong>spectre</strong>, eldo, ADSsim, GoldenGate, etc....
As far as my experience, I often encounter bug in HSPICE Verilog-A compiler.</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 09-04-2013 16:10 :: pancho_hideboo :: Replies: <strong>4</strong> :: Views: <strong>487</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread262674.html" rel="nofollow">Missing .cdb or .oa file in library inv cell inv view veriloga</a></h2></div>
			</div>
			<div class="content_text">When i'm running <strong>spectre</strong> simulator to simulates a circuit's behavioral model by verilog-a,
this problem has occured. Any ideas?</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 08-13-2012 06:14 :: jihrenee :: Replies: <strong>0</strong> :: Views: <strong>1052</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread259014.html" rel="nofollow">simulate compiled component</a></h2></div>
			</div>
			<div class="content_text">Hello guys,

I was given a component in a format (compiled <strong>veriloga</strong> is my guess) and i would like to make it a cell in virtuoso to include it in a schematic and simulate it with <strong>spectre</strong>.

Do you guys know how to do that ?

One told me to create a <strong>veriloga</strong> cellview then include this symbol in my schematic and then to replace the of the</div> 
			<div class="content_info">
				&nbsp;&nbsp; ASIC Design Methodologies and Tools (Digital) :: 07-11-2012 09:09 :: darockdr :: Replies: <strong>0</strong> :: Views: <strong>503</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread257839.html" rel="nofollow">Verilog A Counter on Cadence</a></h2></div>
			</div>
			<div class="content_text">hello guys, i am tryong to generate a counter which has a 10*clock period, by doing a simple verilog A code, on cadence ,<strong>spectre</strong> simulatior, but the issue is that the simulation takes sooo long time,( +20 minutes ), so is this normal? my code is :
// <strong>veriloga</strong> for lte, counter, <strong>veriloga</strong>

`include "constants.vams"
`include (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 06-30-2012 08:50 :: kimo4ever :: Replies: <strong>1</strong> :: Views: <strong>3906</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread250434.html" rel="nofollow">help for veriloga sample hold circuit convergence problem.</a></h2></div>
			</div>
			<div class="content_text">Hi,

I meet a problem of convergence when I use <strong>veriloga</strong> to model the SH circuit.
I first use <strong>veriloga</strong> to build the model of capacitor, ideal switch and ideal opamp, but when I do the simulation with <strong>spectre</strong>, It tell me no convergence, how can I do with this problem?

thx!!</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 04-30-2012 10:24 :: didibabawu :: Replies: <strong>0</strong> :: Views: <strong>516</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread243687.html" rel="nofollow">cadence spectre error (VACOMP-1008)</a></h2></div>
			</div>
			<div class="content_text">Hi all
I am running cadence <strong>spectre</strong> <strong>veriloga</strong> simulation using ic610 and mmsim10.1. The output shows
ERROR (VACOMP-1008): cannot compile ahdlcmi module library <strong>spectre</strong>. My OS is ubuntu 11.10.
Anyone can help me to solve this problem? Thanks alot

Best Regards

Tom</div> 
			<div class="content_info">
				&nbsp;&nbsp; Software Problems, Hints and Reviews :: 03-07-2012 23:31 :: tompham :: Replies: <strong>0</strong> :: Views: <strong>1441</strong>
			</div>
		</div>
				<div class="result_box">
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				<center>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread243670.html" rel="nofollow">[Moved]:	Help with VerilogA in Cadence</a></h2></div>
			</div>
			<div class="content_text">Hello,

I was trying to use <strong>veriloga</strong> to write a model file and simulate it in Virtuoso Cadence. When I try to simulate i get following error

Missing or corrupt .oa file in cellview 'memristordesign/memristor/<strong>spectre</strong> cmos_sch cmos.sch schematic <strong>veriloga</strong>'. The OSS netlister can only
process cellviews that have a valid .oa file. This file (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Electromagnetic Design and Simulation :: 03-07-2012 19:35 :: maheshgtm :: Replies: <strong>0</strong> :: Views: <strong>1872</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread243020.html" rel="nofollow">Nodeset for subcircuit</a></h2></div>
			</div>
			<div class="content_text">It would be easy with hspice or <strong>spectre</strong> in text mode. But I could not figure out with analog environment and virtuoso ...</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 03-02-2012 18:11 :: titanic :: Replies: <strong>3</strong> :: Views: <strong>1042</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread231409.html" rel="nofollow">Speeding up transient simulations in Cadence Spectre</a></h2></div>
			</div>
			<div class="content_text">I am doing a transient simulation for a sigma delta modulator and the simulation time required to complete is quite long. I have come across the "accelerated parallel simulation" option in cadence that could speed up the simulation but i am not aware of the process of setting up that option.

I would appreciate some guidance on setting up APS or </div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-18-2011 16:08 :: panchkapunch :: Replies: <strong>1</strong> :: Views: <strong>2268</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread225543.html" rel="nofollow">Simulation of Continuous-time Sigma Delta modulator in spectre (cadence)</a></h2></div>
			</div>
			<div class="content_text">Hello to everyone,

It is the first time that I am designing a Sigma Delta modulator. I have started with the example (<strong>veriloga</strong>) of the 1st odrer Sigma Delta modulator provided by cadence in ahdl Library.
I have performed a transient analysis (the input signal is 100KHz and is sampled with a clock 10MHz) and the modulator is working fine (I can </div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 09-23-2011 09:24 :: laoud :: Replies: <strong>1</strong> :: Views: <strong>1236</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread204940.html" rel="nofollow">[Help] error on simulation about verilogA block</a></h2></div>
			</div>
			<div class="content_text">I use Cadence IC5141 on RHEL5.4.There is no simulator whose name is "Cadence IC5141".
"Cadence IC5141" is a name of Design Framework where you can use many simulator engine such as Synopsys HSPICE, Agilent ADSsim, Agilent GoldenGate, Cadence <strong>spectre</strong>, etc.

I use the ADE (<strong>spectre</strong>) to simul</div> 
			<div class="content_info">
				&nbsp;&nbsp; RF, Microwave, Antennas and Optics :: 03-08-2011 15:55 :: pancho_hideboo :: Replies: <strong>1</strong> :: Views: <strong>928</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread108011.html" rel="nofollow">System level design and simulation</a></h2></div>
			</div>
			<div class="content_text">I think the newer versions of Simulink/Matlab allow co-simulation with SPICE blocks, using e.g. <strong>spectre</strong>.</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 09-23-2010 11:17 :: kgl_13gr :: Replies: <strong>12</strong> :: Views: <strong>1616</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread185555.html" rel="nofollow">How to create a new cell in Spectre and write it in VerilogA?</a></h2></div>
			</div>
			<div class="content_text">Hello

I'm using IC5141USR5 with <strong>spectre</strong> 7.1.1.187.isr11 32bi.

I'm new to Verilog A/Verilog AMS, so i created new cell, cell view "<strong>veriloga</strong>", open with Modelwriter. In there i expected to write <strong>veriloga</strong>. The header files included have extension ".h". But when i looked up the absdelay function (and others) they appear to be (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 08-17-2010 09:24 :: Nixphe :: Replies: <strong>1</strong> :: Views: <strong>1103</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread181821.html" rel="nofollow">MonteCarlo Design Input Parameter Variation</a></h2></div>
			</div>
			<div class="content_text">Cadence wants to sell you a Monte Carlo license, so don't rule out
malice....

In cdsSpice we used to use gauss() and track() functions. 
Never peeled the lid off <strong>spectre</strong> MC setup when I had the chance.</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 06-30-2010 02:02 :: dick_freebird :: Replies: <strong>2</strong> :: Views: <strong>1139</strong>
			</div>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread169163.html" rel="nofollow">Using verilog transistor model in Spectre simulation 6.1.3</a></h2></div>
			</div>
			<div class="content_text">Hi,

for acedemic purposes I would like to use a custom made level 1 MOS transistor model in my <strong>spectre</strong> simulations (I am using Cadence 6.1.3). In my opinion using a verilog-a transistor model is a good solution for this, because I can adjust the transistor behaviour on equation level or is there a better way?

In order to do so I built a very </div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 02-05-2010 15:33 :: wookah :: Replies: <strong>1</strong> :: Views: <strong>1885</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread168968.html" rel="nofollow">VerilogA module in Spectre: access to outside data</a></h2></div>
			</div>
			<div class="content_text">Hello!
  I write <strong>veriloga</strong> module which must work together with BSIM model (also written by <strong>veriloga</strong>) to obtain advanced facilities in comparison with standart BSIM.

In this case transistor instance is implemented by subcircuit (inline subckt ...) which include two <strong>veriloga</strong> modules: BSIM model and my module. 

My module must obtain (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 02-03-2010 15:18 :: IADanilov :: Replies: <strong>2</strong> :: Views: <strong>1208</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread165045.html" rel="nofollow">Spetre/Verilog simulator question</a></h2></div>
			</div>
			<div class="content_text">IPC I believe is compuGeek for "InterProcess Communication". 
Probably the two simulators are not passing data cleanly, 
one died or concluded when the other was not done (or failed
to start).

Verilog signals are sometimes "too ideal" for SPICE / <strong>spectre</strong>
to deal with. I tend to put 1-ohm series resistors between
verilog / <strong>veriloga</strong> outputs a</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-15-2009 15:27 :: dick_freebird :: Replies: <strong>2</strong> :: Views: <strong>1011</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread163906.html" rel="nofollow">using bmsLib instances in spectre simulation?</a></h2></div>
			</div>
			<div class="content_text">How can I use instances from bmsLib, which have <strong>veriloga</strong> and <strong>veriloga</strong>ms views, in a <strong>spectre</strong> simulation? I added <strong>veriloga</strong> and <strong>veriloga</strong>ms to the beginning of my switch view list and the circuit netlists without warning/error, but the state of the instance does not change when an input is given. I can't even (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-30-2009 22:21 :: oermens :: Replies: <strong>2</strong> :: Views: <strong>1560</strong>
			</div>
		</div>
								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread162490.html" rel="nofollow">Trouble with veriloga in Spectre 6.x simulator</a></h2></div>
			</div>
			<div class="content_text">Hi all!

I have a problem with Verilog-A modeling in <strong>spectre</strong> 6.x.

I use BSIM3 model implemented in Verilog-A by Geoffrey Coram (the file was available at Silvaco and then - at Simucad site some time ago). See attached file. I have successfully used it with <strong>spectre</strong> 5.1.41.

My "standard" task is to simulate MOSFET DC characteristics. Transist</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 11-10-2009 15:46 :: McSim :: Replies: <strong>2</strong> :: Views: <strong>1749</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread158783.html" rel="nofollow">How to simulate random offset of the comparators in Matlab?</a></h2></div>
			</div>
			<div class="content_text">In that case you can make a voltage source with a
gauss()* value in each of the relevant sub-blocks and
repetitively simulate (probably use ocean) and gather
the results for some sort of postprocessing.

*gauss(), agauss(), whatever random / stats you can 
find in the <strong>spectre</strong> manuals.  You could also make a
<strong>veriloga</strong> offset source if the anal</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 09-18-2009 13:22 :: dick_freebird :: Replies: <strong>9</strong> :: Views: <strong>2296</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread157790.html" rel="nofollow">Virtuoso Spectre simulator &amp; AMS designer</a></h2></div>
			</div>
			<div class="content_text">I am doing a top-down mixed-signal ASIC design. Now I have <strong>veriloga</strong>, functional(verilog code), schematic and config view for blocks. Do I have to use AMS designer to simulate with these views? I think <strong>spectre</strong> simulator can handle the mixed signal simulation very well since there is no <strong>veriloga</strong>ms view in my design.

I think AMS designer is (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Software Problems, Hints and Reviews :: 09-03-2009 18:47 :: november :: Replies: <strong>1</strong> :: Views: <strong>2167</strong>
			</div>
		</div>
								<div class="result_box">
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread156600.html" rel="nofollow">diode simulation issue</a></h2></div>
			</div>
			<div class="content_text">hello, everyone
when i use <strong>spectre</strong> to simulation diode, chose junction model parameters, Level 1. 
it is said that the effective area is equal to AREA ? M, unitless. so does PJ, unitless?
what does unitless mean? if the area and junction perimeter are unitless, how can i sepcify the diode properties?  should i specify area PJ as well as W and L?</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 08-19-2009 09:53 :: prcken :: Replies: <strong>2</strong> :: Views: <strong>2286</strong>
			</div>
		</div>
								<div class="result_box">
			<div class="content_header">
				<div class="content_title"><h2><a href="http://www.edaboard.com/thread143272.html" rel="nofollow">Generating random nos in verilogA for simulation in Finesim</a></h2></div>
			</div>
			<div class="content_text">I am currently modeling jitter in <strong>veriloga</strong>. For this i need to generate random numbers. This model is to be run with finesim as the simulator. Can anyone suggest any way to do this as finesim does not support $random function unlike <strong>spectre</strong>?</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 02-19-2009 09:59 :: sowmiya :: Replies: <strong>0</strong> :: Views: <strong>1875</strong>
			</div>
		</div>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread143079.html" rel="nofollow">pll veriloga simulation of  pss,pnoise</a></h2></div>
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			<div class="content_text">Hi ,

When I simulate pss,pnoise  of pll(VCO ,PFD ,Divider are written with <strong>veriloga</strong>), some error comes:

Error found by <strong>spectre</strong> during periodic steady state analysis `pss'.
    Distributed components and components with hidden state are not allowed
        with this analysis -- analysis skipped.
        
        CP
        
        /home</div> 
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				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 02-16-2009 07:59 :: shanmei :: Replies: <strong>4</strong> :: Views: <strong>3125</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread127782.html" rel="nofollow">THD-cadence simulation</a></h2></div>
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			<div class="content_text">In amplifiers, if the input signal frequency is low enough, I would suggest avoid transient sim (+DFT) or flex-balance (just like HB) in <strong>spectre</strong>(RF).

The easiest way is to use DC simulation, and through <strong>veriloga</strong> function and calculator to find the Fourier series coefficients. You can obtain much more insight in DC sim and avoid possible settling</div> 
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				&nbsp;&nbsp; Analog Circuit Design :: 10-17-2008 02:40 :: xshou :: Replies: <strong>17</strong> :: Views: <strong>9288</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread135509.html" rel="nofollow">convergence problem in OTA verilogA model</a></h2></div>
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			<div class="content_text">I am modeling an OTA with <strong>veriloga</strong> language. As i want a single pole system, I am using the laplace_nd function in <strong>veriloga</strong> to model the transfer function of the single pole OTA. When i simulate this model alone in <strong>spectre</strong> it gives me correct result. But when i am using this OTA in a feedback loop or connecting the output of the OTA to a (...)</div> 
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				&nbsp;&nbsp; Analog Circuit Design :: 10-02-2008 09:57 :: sowmiya :: Replies: <strong>0</strong> :: Views: <strong>1783</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread127516.html" rel="nofollow">Running VHDL code integrated with Circuits in Spectre</a></h2></div>
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			<div class="content_text">Hi,

Could anyone please help me running vhdl code integrated with circuits developed using <strong>spectre</strong> simulator. I need it to run in <strong>spectre</strong> itself. I ran with <strong>veriloga</strong> codes. It seems to be working along with designed circuits in <strong>spectre</strong> but then it is generating errors with vhdl.

What should be the "View" name in (...)</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 06-06-2008 21:35 :: tshankar501 :: Replies: <strong>1</strong> :: Views: <strong>798</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread98933.html" rel="nofollow">PLL transfer function</a></h2></div>
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			<div class="content_text">Hi
Can anyone explain how we can plot PLL transfer function(Output phase/ Input phase) using <strong>spectre</strong> and <strong>spectre</strong>RF? 
If there are any documents pls share. 

thanks.</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 06-16-2007 09:38 :: chacha :: Replies: <strong>1</strong> :: Views: <strong>963</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread95005.html" rel="nofollow">spectre view in Cadence library</a></h2></div>
			</div>
			<div class="content_text">1. There are a few kinds of cell views in Cadence design, such as schematic, symbol, <strong>spectre</strong>, <strong>veriloga</strong>, etc. Can someone tell me what's the usage of <strong>spectre</strong> view? How to create the <strong>spectre</strong> view?
  
  2. I have only the Spice netlist of an I/O cell. I want use it in my schematic design. So I created a blank schematic for it (...)</div> 
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				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-30-2007 09:15 :: hmsheng :: Replies: <strong>7</strong> :: Views: <strong>5953</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread90034.html" rel="nofollow">how to edit veriloga code for adc dnl and inl test?</a></h2></div>
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			<div class="content_text">Hello,everyone!
   Now I know we can use the <strong>veriloga</strong> code for adc dnl and inl simulation in cadence <strong>spectre</strong>,but how to edit the <strong>veriloga</strong> code? who can help me?
   my adc is 8bit  12.5Msps  1.8vpp,</div> 
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				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 03-07-2007 03:21 :: rocky_ :: Replies: <strong>2</strong> :: Views: <strong>2093</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread88840.html" rel="nofollow">Help needed in simulation using Hspice</a></h2></div>
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			<div class="content_text">There are differencies in the type of models and the syntax for HSpice ans <strong>spectre</strong>. <strong>spectre</strong> could typical run all models of HSpice but not reverse. The same applies to the netlist features.

The features are Inline Subcircuit Models (I am not shure about the exact name) and <strong>veriloga</strong> and more relaxed name conventions</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Circuit Design :: 02-22-2007 09:07 :: rfsystem :: Replies: <strong>2</strong> :: Views: <strong>972</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread78260.html" rel="nofollow">cadence verilog AMS, verilog ams compilation failed</a></h2></div>
			</div>
			<div class="content_text">You should use ams simulator. It seems that you have chose <strong>spectre</strong>. <strong>spectre</strong> can only support <strong>veriloga</strong>.</div> 
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				&nbsp;&nbsp; Software Problems, Hints and Reviews :: 10-25-2006 01:24 :: tsinghua :: Replies: <strong>1</strong> :: Views: <strong>2508</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread76398.html" rel="nofollow">what is the difference between verilogA and verilog AMS?</a></h2></div>
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			<div class="content_text">I used the Verilog-A program for the for co-simulation with the <strong>spectre</strong> simulator. Generally I use it when I design some  program logic along with the analog circuits.

I dont know much about the Verilog-AMS</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-01-2006 06:10 :: gunturikishore :: Replies: <strong>4</strong> :: Views: <strong>15031</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread39315.html" rel="nofollow">Circuit simulator for linux</a></h2></div>
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			<div class="content_text">By now, I think AMS Designer is the best simulator to handle verilog(d,a, ams) and spice(<strong>spectre</strong> or hspice netlist). The ams simulator comes from Cadence.</div> 
			<div class="content_info">
				&nbsp;&nbsp; Linux Software :: 08-16-2005 05:57 :: flyinspace :: Replies: <strong>13</strong> :: Views: <strong>5120</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread38936.html" rel="nofollow">Does the Netlist include the Verilog-A?</a></h2></div>
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			<div class="content_text">I think the "netlist" file is the concatenation of the "netlisHeader" and "netlistFooter". So you should find the same include in the final netlist. Verilog is refenced as a subcircuit in <strong>spectre</strong>.</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 05-26-2005 23:22 :: skal81 :: Replies: <strong>2</strong> :: Views: <strong>1196</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread37358.html" rel="nofollow">Simulating Verilog-A model using spectre.</a></h2></div>
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			<div class="content_text">Hi kamesh419,

Actually,it already told you the reason of errors and how to fix it in the following:

ERROR: Netlister: unable to descend into any of the views defined in the view list: "<strong>spectre</strong>S cmos_sch schematic" for instance I5 in cell Add_rpl_8. 

Either add one of these views to: Library:MyLib Cell:GlitchAnalyzer or modify the vi</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-29-2005 01:09 :: jordan76 :: Replies: <strong>4</strong> :: Views: <strong>7638</strong>
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				<div class="content_title"><h2><a href="http://www.edaboard.com/thread27364.html" rel="nofollow">Making an Ideal Opamp for simulation</a></h2></div>
			</div>
			<div class="content_text">The hspice model of vcvs recognizes the max and min parameters, but the <strong>spectre</strong> model does not. If you are using <strong>spectre</strong>, you may use <strong>veriloga</strong> to model the saturation effect.</div> 
			<div class="content_info">
				&nbsp;&nbsp; Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-19-2004 01:26 :: Hughes :: Replies: <strong>18</strong> :: Views: <strong>33436</strong>
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