1000 Threads found on edaboard.com: Sram In Cadence
I am new in VLSI design. I want to start simulation on sram 6T memory cell in cadence. How can I start? Which material or book can help me?
What is spice file? How can I edit or use that file in cadence?
How can I get TSMC files and How to use that files for cadence simulation?
Analog IC Design and Layout :: 07-20-2009 14:27 :: imported_dkalaria :: Replies: 0 :: Views: 1072
To understand the working of 6T sram you can read Digital Integrated Circuits by Rabey.
ASIC Design Methodologies and Tools (Digital) :: 07-21-2009 19:29 :: bobjee :: Replies: 3 :: Views: 2374
I have designed a sram using cadence Virtuoso. I dont know how to test the memory. Basically I want to test each and every memory location, but I am not sure how to generate the input signals. I tested every cell using the stimuli option in the ADE, but when it came to system level, I cannot generate the signals I wanted using stimuli.
Analog IC Design and Layout :: 07-11-2010 10:25 :: somu.atluri :: Replies: 0 :: Views: 893
Please post your circuit..image of 1bit sram and the other details also..
Analog IC Design and Layout :: 12-08-2011 03:52 :: muffassir :: Replies: 3 :: Views: 994
Hello everybody, I'm making design of sram cell in cadence 6.1.4 I have generated layout in virtuoso layout editor but i dont know how to calculate the area of layout... Can anybody help me?..Thanx in advance...
Analog Circuit Design :: 02-23-2012 12:06 :: kpkp :: Replies: 0 :: Views: 545
It looks like what you are saying is right. The power pins on the sram may be quite close which is causing this problem.
1) One way to resolve this issue may be , creation of power ring around the memory, and extend the power pins outside to connect to this ring. You will have to put two rings, one for VDD and another for VSS.
2) Once I work
ASIC Design Methodologies and Tools (Digital) :: 07-01-2012 09:00 :: shobhit :: Replies: 2 :: Views: 520
I tried to draw a layout of spiral inductor in virtuoso, it is not recoganized as an inductor. Do I need any other tools? or did I make any mistakes? thanks!
RF, Microwave, Antennas and Optics :: 12-04-2003 12:25 :: viviana :: Replies: 12 :: Views: 7686
how can I run scripts in cadence Soc Encounter? I'd like to perform the same steps on multiple designs to compare them. So I wrote a tcl script similar to the ones in the tutorial. But how can I execute them? specifying them with the -cmd option at startup didn't work. Just the usual Encounter window pos up but no design is loaded or anyt
Software Problems, Hints and Reviews :: 12-11-2003 11:05 :: miho :: Replies: 3 :: Views: 3125
when I start my project manager in cadence ic5033, I find that I could not select the library.the system tell me this problem.I think something must be wrong about my ,could anyone can tell me how to settle the problem and how to setup ic5033 well in linux.
Log file is "/home/altra/libManager.log".
Linux Software :: 02-21-2004 11:24 :: altra :: Replies: 8 :: Views: 1795
Hi, I am trying to use cadence IC design software...
however I encountered a weird problem..
I made a 2inputs and 3 inputs NAND gate, and it worked file when I simulate them. However, if it gave me errors while I want to simulate their symbols.
the output log always say these:
**error**: subcircuit name missing
>error *** difficulty in re
Electronic Elementary Questions :: 03-18-2004 20:44 :: Rekresreb :: Replies: 6 :: Views: 3979
Assura and Diva both can generate extrated view or analog_extracted view, which are used to be invoked in postlayout simulation in the Analog Design Environment (Artist).
However, if I want to do the same thing with Calibre, how to generate these views?
In fact, I only see netlist generation functions in Calibre interactive PEX.
Analog IC Design and Layout :: 03-23-2004 08:51 :: Aigneryu :: Replies: 4 :: Views: 3901
Is there an instance like ideal op amp in cadence?
Analog Circuit Design :: 05-02-2004 17:46 :: raju :: Replies: 15 :: Views: 12582
Does anyone know about the commands to run a nested sweep in cadence...I need the netlist commands? I am sweeping the voltage and clock timings.
Also...Can we use a variable in setting the tranient analysis stop time? Like if I have a variable "time" can I give the transient analysis stop time as "4*time"??
ASIC Design Methodologies and Tools (Digital) :: 05-19-2004 22:15 :: knataraj :: Replies: 0 :: Views: 845
:( Could somebody tell me:
How to install the SiMKit library(Philips) for Spectre in cadence IC_50?
Thanks in advance!
Software Problems, Hints and Reviews :: 06-07-2004 07:22 :: rfic :: Replies: 0 :: Views: 1049
How to install the SiMKit library(Philips) for Spectre in cadence IC_50?
Analog IC Design and Layout :: 06-08-2004 09:09 :: rfic :: Replies: 1 :: Views: 1451
How to create an instance using skill languahe in cadence, say NMOS.
I have seen the syntax for creating instance
dbCreateInst( d_cellView d_master t_name l_point t_orient
To be specific what should I enter for d_master.
Also how can we edit the parameters like width and length of nmos
Analog IC Design and Layout :: 06-10-2004 00:42 :: raju :: Replies: 5 :: Views: 7773
Can anyone tell me what's the theory behind PSS, PAC analysis in cadence?
Analog Circuit Design :: 07-23-2004 02:54 :: nxing :: Replies: 3 :: Views: 2418
Sorry for ask a stupy problem,
How to create .fsdb in cadence IC5.0(linux version)
I am a new guy
so please list a detail procedure
Tks in advance!!
ASIC Design Methodologies and Tools (Digital) :: 07-27-2004 04:57 :: realtek :: Replies: 3 :: Views: 1452
Hi all I am looking for a turorial for conduction corner analysis in cadence. I use tsmc 0.25 process. Design kit have been installed. It seems I have to write some script to do corner analysis, is it true?
Analog IC Design and Layout :: 08-03-2004 16:52 :: rf_ray :: Replies: 11 :: Views: 3326
I've following task in cadence: I want to find a design flow using tools which are actuall (and will be supported in future). But I've only lx86 tools since I've no sun. Therefore I can't make use of scripts for silicon ensemble since it isn't supported in linux (or I'm wrong). So I've find other design flows but there are so many tools
Linux Software :: 09-10-2004 11:17 :: eda4you :: Replies: 6 :: Views: 1424
How to Define and plot functions in cadence?
With generated netlist or Analog Artist?
Or other way?
Thanks a lot. :cry:
Analog IC Design and Layout :: 09-23-2004 22:23 :: penghan :: Replies: 5 :: Views: 1402
I can use my network printer(HP LaserJet 5000) well in redhat 8, but can't use it in cadence. So I enter /cadence/tools/plot/bin and run ./plotconfig, but I cannot find the model of my printer. How do I install my printer in cadence? Ask for your help!
Thanks and Best Regards,
Linux Software :: 10-13-2004 05:41 :: harryzhu :: Replies: 3 :: Views: 3955
What is new in cadence IC5.1?
What has beeb added for noise analysis? Do you have Design Exp. with it.
ASIC Design Methodologies and Tools (Digital) :: 10-21-2004 04:31 :: Johnson :: Replies: 5 :: Views: 817
I am trying to simulate a bandgap circuit in cadence. The problem is I only have the 0.18 um CMOS technology file. I wanted to know is how do I simulate a BJT in Spectre? Is there any place I can get the model file for that? or is there any way around it?
Analog IC Design and Layout :: 10-25-2004 16:45 :: aryajur :: Replies: 16 :: Views: 3214
How do I save data of the simulation result in cadence so I can export to matlab or excel? And where is wavescan in ADE?
Analog Circuit Design :: 11-09-2004 23:24 :: ccw27 :: Replies: 2 :: Views: 3825
Anybody have a good tutorial on how to do high speed digital design in cadence spectre RF ?
like generating eye diagrams, generating PBRS signals, checking input referred noise and so on.
for fiber optic, backplane applications (high speed digital 1gb/s - 40gb/s)
Analog IC Design and Layout :: 11-12-2004 00:28 :: Puppet1 :: Replies: 0 :: Views: 1162
check AN 333: Developing Peripherals for SOPC Builder for detailed information about using ?Interface to User Logic?. It is also possible to connect your sram in this way.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-17-2004 06:32 :: cube007 :: Replies: 1 :: Views: 1206
I am trying to use the SpectreS. I want to know, whether i can use mosis models (bsim3v3.1) directly in spectreS? if so, what is the format for writing the model file? (if some one can post it or send it to me, it would be fantastic).
thanks in advance.
Analog IC Design and Layout :: 11-17-2004 19:02 :: srivatsan :: Replies: 1 :: Views: 1137
How to measure input impendance in cadence if the circuit is MOS cascode configuration
Analog Circuit Design :: 11-18-2004 21:27 :: selvaraja :: Replies: 2 :: Views: 1485
i want to simulate a analog circuit quickly which contain many components like opamps...etc.can anybody tell how to use standard cells like opamp....and where can i get those standard cell in cadence.
can anybody upload a pnp model file plssss.....
Analog IC Design and Layout :: 11-21-2004 01:46 :: balu304 :: Replies: 3 :: Views: 1395
I am sweeping the input Vgs and would like to plot Vgs-Vt on the x-axis instead of only Vgs. How do I do this in cadence?
PCB Routing Schematic Layout software and Simulation :: 12-03-2004 00:36 :: ccw27 :: Replies: 3 :: Views: 2201
Does anyone know how to use ideal balun in cadence? I need to drive differential LNA. Can I give input to Diff LNA without balun? thanks in advance.
RF, Microwave, Antennas and Optics :: 12-15-2004 17:06 :: chinito :: Replies: 2 :: Views: 5689
In cadence IC5 if follow the way
cadence Analog Design Environment --> Setup --> spectre: Model Library Setup
I see that the latter form works quite strange, namely:
1) Title of model list box is #Disable | Model Library File Section
I do not understand here the meaning of word "#Disable"
2) I can add additional model
Software Problems, Hints and Reviews :: 12-17-2004 06:03 :: ed2000 :: Replies: 2 :: Views: 3732
I have designed a spiral inductor in cadence Virtuoso and in the Schematics I designed the equivalent pi-circuit with lumped passive elements. I want to make LVS. The layout passes successfully the DRC check. However in after the LVS running I get the message that there is a short between the ports, which makes sense since the ports are on th
Analog IC Design and Layout :: 12-17-2004 08:07 :: tromeros :: Replies: 10 :: Views: 2148
I'm doing a BiCMOS design using cadence. I need to put guard rings around the MOS-section. Can anybody tell me how to do it?
Analog IC Design and Layout :: 01-06-2005 14:05 :: pantic :: Replies: 5 :: Views: 5522
How to change Verilog-A text editor in cadence from vi (default) to smth else, e.g. emacs?
Analog IC Design and Layout :: 01-06-2005 23:50 :: borodenkov :: Replies: 3 :: Views: 5911
Does someone know how to use FFT to transform the transient waveform into frequency domain in
cadence analog simulation environment? and is there any way to calculate the amplitude of one
time domain waveform? I coudn't find a good reference for the analog simulation environment.
Thank you very much for your help!
Analog IC Design and Layout :: 01-07-2005 17:08 :: gogomi :: Replies: 11 :: Views: 10641
Hi, I designed an LNA with UMC 0.18CMOS technology. DRC and LVS have been passed. Now, I try to extract parasitics of RFIC with assura in cadence. However, the program is always failed. I think must be some setting errors. Could someone help me with this?
RF, Microwave, Antennas and Optics :: 01-18-2005 19:09 :: duoxz :: Replies: 2 :: Views: 983
I want to simulate a Switched-Capacitor circuits and I only want the samples at the end of one of the two clock phases. Do someone know the method to build an ideal discrete sampler in cadence? (Not Sample-and-Hold, Since I don't want the sin(x)/x coloring effect, I want an discrete point sampler)
Or in other ways, I want to directly evaluate t
Analog Circuit Design :: 01-26-2005 14:07 :: terryssw :: Replies: 7 :: Views: 4803
Is there anybody know how to do the power consumption simulation for a digital design in cadence?
ASIC Design Methodologies and Tools (Digital) :: 01-26-2005 23:31 :: TiwstedNeurons :: Replies: 0 :: Views: 1568
I hav simulated a simple PMOS buffer op-amp in hspice which generated by 3.3V supply & te result i get as below :
t.output noise=3.58m V/√Hz
equivalent inp. noise = 188.4u V/√Hz
*While i tried te same cct in cadence(Spectre) n i get te same o/p noise
t. o/p noise =12.87u V?/Hz
equivalent i/p noise =189.725u V/√
Analog IC Design and Layout :: 01-27-2005 23:14 :: pnanda65675 :: Replies: 4 :: Views: 3121
I need to know how to obtain a list with all net names of a design in cadence Virtuoso because I want to do a RCX-Extraction of selected nets with Assura.
Analog IC Design and Layout :: 01-31-2005 16:50 :: pantic :: Replies: 4 :: Views: 3307
i've a specific problem in cadence BuildGates.whenever i write code with component instantiation it works but i gave entity insatiation it will not work. what may be problem.kindly help
like if i give r1:entity work.filename
it is giving error that can't read from file
but the same code is working
ASIC Design Methodologies and Tools (Digital) :: 02-08-2005 06:33 :: smith_kang :: Replies: 1 :: Views: 592
Dear all :
somebody know how to sim eye diagram in cadence ?
I try a lot of time , the waveform is not same to book.
so if someone know to to sim please tell me .
RF, Microwave, Antennas and Optics :: 02-17-2005 22:43 :: super :: Replies: 2 :: Views: 2677
I tried to include a verilog code to a schematic in cadence. For ex a cell XOR has a schematic and I created another view called functional and wrote verilog code inside that text file.
But when I saved the verilog code, it pops with a error -- parsing error at line 1. do anyone have idea what this error means.
Analog IC Design and Layout :: 02-24-2005 23:04 :: dream_taker :: Replies: 2 :: Views: 940
I want to know how to generate random NRZ signals in cadence IC design tool.
I want to simulate the transient output of my CDR circuit. And want to input random NRZ signal into it.
Also, I want to plot the output as eye diagram.
I want to know how to do above things in the cadence IC environment.
Analog Circuit Design :: 03-01-2005 22:33 :: beabroad :: Replies: 2 :: Views: 2077
What is the tools' name in cadence Virtuoso for DRC, ERC and LVS. I think those are specific tools embedded into Virtuoso. As for Mentor Graphics, the DRC is ICrules, and LVS is ICtraces.
Analog Circuit Design :: 03-02-2005 12:36 :: tia_design :: Replies: 6 :: Views: 1473
i am doing LNA for 2.4G wireless lan application.i am struggling to characterise regarding noise figure,s parameters in cadence.can anubody help me to simulate the circuit for those parameters in cadence.i want detailed information.pls post some documents or help manual regarding that.
for s parameter simulation,i took 2 ports.for the i/p por
RF, Microwave, Antennas and Optics :: 03-09-2005 00:53 :: balu304 :: Replies: 3 :: Views: 3736
I have the following trouble with Calculator tool in cadence Analog Design Environment...
I am doing a transient analysis, and I want to compare the derived result with a strait line.
The line has the equation:
y=0.1x + 0.96
Could this line be drawn i Calculator tool.....
What is the name o
Analog IC Design and Layout :: 03-22-2005 03:18 :: massive :: Replies: 1 :: Views: 1787
i just simulate a very basic LC cross-coupled VCO in cadence.
It's weird to me that the results is subjective to simulation time.
say when simulate 20ns, I can see the oscillation wave, while if i change to 10ns or 30ns, the wave is gone and seems not oscillate at all.
And, the Oscillation start time point is varies with
RF, Microwave, Antennas and Optics :: 03-28-2005 18:50 :: mbright :: Replies: 6 :: Views: 2454