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36 Threads found on Sram In Cadence
Hi, I am new in VLSI design. I want to start simulation on sram 6T memory cell in cadence. How can I start? Which material or book can help me? What is spice file? How can I edit or use that file in cadence? How can I get TSMC files and How to use that files for cadence simulation? Thank you.
Hi, To understand the working of 6T sram you can read Digital Integrated Circuits by Rabey.
Hi, I have designed a sram using cadence Virtuoso. I dont know how to test the memory. Basically I want to test each and every memory location, but I am not sure how to generate the input signals. I tested every cell using the stimuli option in the ADE, but when it came to system level, I cannot generate the signals I wanted using stimuli. Al
hi everyone, I am trying to implement sram in cadence. So, I need to perform monte carlo anlaysis on sram and also I need to draw scatter plot of leakege current against process variation vth. I know how to set statistics block and running monte carlo but I donot know how to plot scatter plot for these two. can anyone tell (...)
Please post your circuit..image of 1bit sram and the other details also..
Hello everybody, I'm making design of sram cell in cadence 6.1.4 I have generated layout in virtuoso layout editor but i dont know how to calculate the area of layout... Can anybody help me?..Thanx in advance...
Hi, It looks like what you are saying is right. The power pins on the sram may be quite close which is causing this problem. 1) One way to resolve this issue may be , creation of power ring around the memory, and extend the power pins outside to connect to this ring. You will have to put two rings, one for VDD and another for VSS. 2) Once I work
There is a question about layout. I am designing sram in 0.18 CMOS process. Someone told me that there is a technique - drived mask - and it's possible to make nmos using only "ndiff" and poly except "n-implant". Is it right? If so, what's the method?
Word line is made of Salicide polysilicon in sram. Salicide process makes polysilicon reduce its resistance. Even though, Salicide Polysilicon have larger sheet resistance than Metal Line. To make sram control command, I realized I have to consider delay in word line. Of course, the delay is due to polysilicon sheet resistance, about 10
hi i just want to know the interconnect structure of 8 CLB FPGA how to do that? and how to simulate sram in cadence?(what are input? clock timming diagram i have to insert in ananlog environment?)
Hi I have designed a 8 bit register file using 6T sram cell in cadence spectre. I want to evaluate the leakage power for this circuit. can anyone tell how to resolve this problem
I am working on sram 6T cell simulation in cadence using different model files. Added after 7 minutes: I am simulating the circuit in Analog Design Environment with spectreS host simulator.
Hi, I am a new student in VLSI and I am working in one of my project related to sram 6T cell design using cadence tool. Can anybody have material or book name? so I can get idea about sram cell simulation in cadence and How to design sram cell? Thanks,
i need to simulate 8T sram cell on cadence..... how to get read and write timing curves
Hi, I recently posted a question about 'how to test sram: generating the inputs'. I would like to know, if I write a verilog code (which will have the test data inputs), is there a way to interface the verilog code with the schematic. Thanks in advance for the help. Ps: I have UltraSim & cadence virtuoso.
I have a 0.18 um 8K bit sram schematic in cadence Virtuoso, I want to scale it to 90 nm, which means to change the width and length of every MOSFETs to half of origin size, But is has too many MOSFETs,I don't want change it one by one, is there any fast way to do it? Thanks~~
Hey, I am trying to work on sram cell in cadence. Could any1 help with with the simulation of the butterfly curve in cadence? please help me out. Thank you Mohana
HI all I have face difficulty in designing of sram design using Negetive word line concept. any body please help me to proceed.any body have complete sram design ( scematic capture) in LT spice....?:???:
i have designed a static RAM circuit(32 nm). I wanted to perform simulation for read operation. So i needed to set the bit lines to vdd(0.9v). I used nodeset command to set the initial volatge of bitline to vdd, but the initial voltages remain upto 0.35 volt. So can u tell me what is going wrong or should i use another command if any to set the ini
Hi everybody, i'm making analog design of 6t sram cell in cadence. but my cell does not store the value 0 or 1 inside the cell. when i apply complementry values to bit line (Vdd) and bit_bar (gnd) line it keeps the value storing inside bt as i remove the voltage it takes the value of power supply. that means it does not store the values applied at
Hi, I'm trying to connect 128 symboled sram cells in series using Multiplicity. I followed instructions on to use the parametric option for the value of "Multiplicity". When I want to run a transient analysis using Analog environment, it gives me an error saying that the multiplici
Hi I dont know how to calculate SNM of the sram 6T Cell in cadence virtuoso. Also i have less knowledge about beta and gamma ratios of the sram cell. kindly help me out with this.... thanks! Madura
Dear all, I am doing a project titled "Power Modelling of embedded sram". There are 2 types of sram cells that I need to take care of one is the standard sram and the other is the assymetric sram cell (where writing a zero is significantly less energy consuming than writing a one). The model should provide an estimate (...)
Hi, I am familiar with cadence HDL, cadence Allegro and cadence SPECTRAAQuest (ver 15.2) tools in designing PCBs but new to cadence Package Designer (APD). Now, I need to design an sram chip made by Micron. The design is a microBGA and is similar to Tessera TV46. I don?t know how to start this design. Are (...)
Hi, I am familiar with cadence HDL, cadence Allegro and cadence SPECTRAAQuest (ver 15.2) tools in designing PCBs but new to cadence Package Designer (APD). Now, I need to design an sram chip made by Micron. The design is a microBGA and is similar to Tessera TV46. I don?t know how to start this design. Are (...)
The gallery shown seem to model the physical process steps without any lateral effects. It could have a good value if some of the important lateral effects are built in. In this case you can optimize the density of a sram cell by checking the 3D spacings. If only metal 3D is shown it the impression that everything is capacitive connected. But th
can anybody give me a pspice code of 6 transistor sram cell? i need it urgently... please help thanks in advance... dip
can anybody give me a pspice code of 6 transistor sram cell? i need it urgently... please help thanks in advance...
hi, can somebody tell me which are circuitaries associated in reading and writing of 6T ,1 bit sram
Hi all, I want to perform post layout simulation of sram cell in cadence 6.1.4. I have completed drc n lvs steps successfully with assura.But i can't extract gives error that "no directory found". I have attached screenshots of settings for directory please help me if anybody can solve this problem...Thanks in advance...[A
Greetings everyone, Since I couldn't find a similar topic I decided to post my problem : I am using Faraday Mem Maker along with UMC90 technology for sram generation. In general, I want to use the .gds and .siz (net list) files from the me maker tool to perform some post-layout simulations with Hspice. The flow utilises cadence 5 and Assura 4.1
Hi i am very new to the cadence virtuoso layouts . I am trying to make a 6T sram layout . The schematic has two coupled inverters . I have recently added the Nangate 45nm layout in which it has already a inverter layout, so i am trying to use the create instance icon to place the layout of the inverter. when i am trying to place that i can only
Does anyone know how to measure power dissipation of memory block from sdf format? My design is work with sram block, and I need information how much power is being consumed in memory block. Please give me some information about this problem. I am mainly working with cadence and Synopsys tools. THX.
Hi, I'm trying to simulate a basic sram cell 6T with cadence Spectre simulator and Ocean script. More precisely, I need to carry out a parametric analysis but I haven't succeeded in. Here's my netlist : ///////////////////////////// // basic gates description // ///////////////////////////// subckt sramCell WL BLb BL M0 net0
Hi, We are looking for : Candidate is expected to contribute individually by working hands-on layout design of sram/ROM/CAM/Custom memories and physical verification of memories. He/She is expected to mentor / lead team of memory layout designer depending on requirement of project. Candidate is required to interact and work with customer pr
Hi, For cadence analog design envirenment i built 32x32 memory array. I want to nodeset the sram latch. If i use simulation -> convergence aids -> nodeset , i am gonna have to nodeset every instance of the 6T memory cell. How can i nodeset subcircuit so that , every instance obeys that nodeset arrangement ..? (i.e. making nodeset as