1000 Threads found on edaboard.com: Sram Precharge
I'm having trouble understanding the purpose of precharging the BLs during a read operation of a traditional sram.
Is it because after a previous operation you want a common starting point (both bit lines being 1) so the sense amplifier can begin to sense the change in the BLs?
Thanks everyone. I love this community.
ASIC Design Methodologies and Tools (Digital) :: 12-04-2013 14:44 :: mspagon :: Replies: 1 :: Views: 265
precharge is avery importment step before you read another row in DRAM and sram. In DRAM, precharge will turn off active word line and precharge bit line pairs to ready state. If you ignore this procedure, bl and blb will have some voltage difference. After charge sharing, maybe the voltage difference will not (...)
Professional Hardware and Electronics Design :: 05-09-2002 12:52 :: maskrom :: Replies: 5 :: Views: 11904
In sram cells, we usually precharge the bit lines. We may use the p-type devices to precharge to full VDD. But does it improve only the writes and reads for logic 1, and makes slow memory access for logic 0?
How can we handle the situation?
ASIC Design Methodologies and Tools (Digital) :: 11-23-2006 13:12 :: spartacus2 :: Replies: 1 :: Views: 761
As I understand question was regarding PMOS size in sram cell.
As PMOS size is decreased in sram the stability of sram cell decreases.
As per the critical path in sram I would suggest that it is not straight forward.
There are 2 paths which are in race.
1.. Clock to Row Selection
2. Clock to (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-27-2006 10:14 :: nitu :: Replies: 3 :: Views: 856
can someone give info on the timers used in large sram arrays to synchronize the precharge(enable and disable),sense amp enable and disable in the same clock period.
to use dummy slices or sdls to genrate the timers etc...
ASIC Design Methodologies and Tools (Digital) :: 02-05-2007 11:05 :: atul799 :: Replies: 0 :: Views: 622
I have a question about write operation of 6T sram
I know for sram read:
phy2 : precharge both bitlines high
phy1 : Then turn on wordline, One of the two bitlines will be pulled down by the cell
for sram write, my question is that during phy2, does the bitline and bitline_bar need to be (...)
Analog Circuit Design :: 08-27-2013 19:26 :: onion2014 :: Replies: 0 :: Views: 334
I am designing single ported sram with 6T cell. I am using cadence virtuoso.The components would be write circuit, precharge, sense amplifier, 6T cell, address decoders. It has to be 4 banks of 256 bits so muxes would also be required. How do I size each of them? All I know is about sizing 6T cell to minimum so it saves area.
ASIC Design Methodologies and Tools (Digital) :: 04-19-2014 19:30 :: Kathan Shah :: Replies: 3 :: Views: 275
I want to measure the read delay and write delay of an sram cell 6T in HSPICE, Would you please help me to do this?
Many Thanks in advance
Analog Circuit Design :: 08-05-2014 01:38 :: electronics20 :: Replies: 3 :: Views: 230
I'm searching for sram device to use with a Analog ADSP-21160.
I don't understand the memory configuration of the device I found!
256K x 36
512K x 36
1Meg x 18....
Why this strange format? Why not a data widht of 16 or 32 bit?
Professional Hardware and Electronics Design :: 07-29-2002 12:28 :: BGA :: Replies: 3 :: Views: 825
you have interface it parallel to your PIC.
1 pin for write
1 pin for read
1 pin for cs (not necessary)
8 pins for data
20 pins (2^20 = 1024) for address pins
I think that you do not have so much pins on the pic. So you have to use a extra device (latch).
How much pins are left for the connection to your sram?
PC Programming and Interfacing :: 12-28-2002 13:05 :: cube007 :: Replies: 10 :: Views: 1885
Could some one guide me as to how to get sram from Cypress Technologies working.........or if some one knows any verilog code for writing into sram plz post it in your reply .
Professional Hardware and Electronics Design :: 01-11-2003 02:29 :: Aircraft Maniac :: Replies: 3 :: Views: 1072
a whitepaper on sram DPGA security
ASIC Design Methodologies and Tools (Digital) :: 01-18-2003 01:57 :: rewkie :: Replies: 0 :: Views: 1033
Professional Hardware and Electronics Design :: 01-26-2003 00:55 :: DrBELL :: Replies: 0 :: Views: 761
This application note shows how to reconfigure an sram based FPGA
using a flash based microcontroller. The text for "Controlling
FPGA Configuration with a Flash-Based Microcontroller" can be
found by clicking on the Web site icon, or by dialing up Atmel's
faxback system (1-800-29-ATMEL or International: 1-408-441-0732)
or by re
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-07-2003 05:43 :: 0levanhoc :: Replies: 3 :: Views: 2248
Does anyone know how to measure power dissipation of memory block from sdf format?
My design is work with sram block, and I need information how much power is being consumed in memory block.
Please give me some information about this problem. I am mainly working with Cadence and Synopsys tools.
ASIC Design Methodologies and Tools (Digital) :: 02-18-2003 23:43 :: kokmin :: Replies: 2 :: Views: 1582
This document is free available
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-23-2003 09:59 :: dainis :: Replies: 1 :: Views: 1875
I want to config Altera sram based FPGA (ex ACEX series) with AVR MCU+EEPROM by ps mode,
because the smallest AVR mcu only have 6 IOs,and clk need 1,
so I think I may tie e2prom's clk whith fpga's DCLK,tie e2prom's Dout with
I wang to see if it alwayes config successfully when I low nConfig,I first feed some
dummy bits before the
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-02-2003 04:07 :: leonqin :: Replies: 1 :: Views: 1561
Ask TSMC to give you the sram compiler, it is free of charge if you are their client !
ASIC Design Methodologies and Tools (Digital) :: 04-23-2003 07:29 :: kwkam :: Replies: 3 :: Views: 1155
The best way is to look at the memory corner of Xilinx's site:
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-20-2003 17:49 :: sb :: Replies: 1 :: Views: 1351
Professional Hardware and Electronics Design :: 10-31-2003 07:01 :: dainis :: Replies: 5 :: Views: 818
Can anybody tell me the differences of
pipelined and flow-through syncronous burst sram like it is used for
MPC555 or 565.
I can see the additional registerbank in the pipelined version but what is the different behavior of both.
Microcontrollers :: 11-25-2003 03:41 :: mueller5321 :: Replies: 0 :: Views: 649
Al Farouk, there is no following link posted!
i don;t understand multi-port RAM in the sense that i have not encountered generators for anything else than single- and dual-port.
In my designs i often use multiple-output register banks which is different.
I would like if some vendor provided sram-based configurable register banks.
ASIC Design Methodologies and Tools (Digital) :: 12-17-2003 05:00 :: the_penetrator :: Replies: 8 :: Views: 3622
Are there any other manufacturers besides ST who do flash/sram in same chip?
ST's psd chips have to small sram and have IO cpld I don't need...
Trying to reduce a FPGA's system IC count (o;
Professional Hardware and Electronics Design :: 03-23-2004 08:58 :: davorin :: Replies: 4 :: Views: 1121
Cypress ( ) has a lot of Synchronous srams. They are working together with Micron. Some year ago Cypress bought the company Galvantech with all their RAM-production too.
Microcontrollers :: 04-09-2004 08:49 :: cube007 :: Replies: 4 :: Views: 758
So, when someone says, data buffer, does it means,
it could be either register(DFF) or RAM?
In verilog coding, does it have different coding style
to refer to data buffer using registers and to refer to RAM?
In verilog, if I declare
If the design goes to synthesis or layout, will it become df
ASIC Design Methodologies and Tools (Digital) :: 07-02-2005 09:12 :: eda_wiz :: Replies: 10 :: Views: 2146
Please tell which vendor offer radiation hard or radiation tolerant sram,especially SBsram.
Professional Hardware and Electronics Design :: 04-18-2004 20:52 :: jerred :: Replies: 2 :: Views: 1194
Can anybody help me to choose a good sram dual port to use with my Xilinx Virtex2 Pro that have few control signals and it is easy to use...
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-17-2004 11:22 :: OvErFlO :: Replies: 2 :: Views: 1077
I need to design a circuit to generate 1.5v~2.4v precharge voltage for large cap load(10pf).
But the working environment is too tough:1.6v~6v,
Besides the time response should not too slow(10ns~20ns).
Any suggestion or comment on it?
thanks in advance!
Analog IC Design and Layout :: 05-26-2004 05:00 :: jordan76 :: Replies: 0 :: Views: 1047
i think that better is to download the Data Sheet of sram whic you would use.
After simply copy the waveform for Read And Write.
is not to hard to make it.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-04-2004 06:33 :: firstname.lastname@example.org :: Replies: 15 :: Views: 2639
I want to integrate flash , sram, eeprom and cpu core... on a single silicon,
how to do that?
ASIC Design Methodologies and Tools (Digital) :: 06-17-2004 12:03 :: dada1019 :: Replies: 0 :: Views: 485
i need to design a board containing 1MB sram, 1MB of flash(for program) and 1MB of EEPROM(for data) together with adsp-bf531,I am planning to initialize data and program address in sram at the time of problem is how to load data from flash and EEPROM to the addresses initialized in sram, do i have to do it with the help of proce
Digital Signal Processing :: 06-21-2004 07:03 :: pimr :: Replies: 3 :: Views: 1188
Is there a COTS based integrated EDAC sram available?
Are there EDAC controllers that can be interfaced with srams?
delay (delay by technology)
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-23-2004 04:02 :: delay :: Replies: 1 :: Views: 911
Can anybody introduce me how to do the following 6-T sram bit cell analysis with Hspice:
1.Standby current on VDD;
2.Read and Write Margin;
I have tried to simulate the standby current on VDD. I set BL,BL_ and WL to 0, and also using ic(Q)=1.8v(I simulate with 018u logic process model card). I find i(VDD) is very close to ze
Analog IC Design and Layout :: 06-28-2004 11:26 :: jemmy :: Replies: 5 :: Views: 7423
Does anybody know how to wirte Hspice input file to calculate 6-T sram's
Static Noise Margin(SNM)?
Analog Circuit Design :: 07-05-2004 12:39 :: jemmy :: Replies: 1 :: Views: 3283
Asynchronous sram need controller?
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-04-2004 02:58 :: leonqin :: Replies: 3 :: Views: 2013
The cache and sram may be adjusted only during startup. I do not think that it is possible in runtime. Setting up is normally explained in the users amnual. (eg: Blackfin)
Hope this helps,
B R M
Digital Signal Processing :: 08-25-2004 09:52 :: brmadhukar :: Replies: 3 :: Views: 705
Look at tis website
Electronic Elementary Questions :: 10-25-2004 06:58 :: mariaR :: Replies: 2 :: Views: 3700
for a particular sized dram and sram cell, how many sense amps do you need? for example a 512 X 512 X 8 (bit) memory array, how many sense amps would be needed for dram and sram?
I know that each column in sram would have 8 sense amp for the 8 bits. that makes 8 X 512 sense amps total? or just 8 sense amps (all 512 columns sharing (...)
Electronic Elementary Questions :: 10-28-2004 01:40 :: wwfieee :: Replies: 2 :: Views: 1365
Could someone please explain what is the different between async sram and sync sram?
Thanks & best regards.
Microcontrollers :: 11-10-2004 06:23 :: virus :: Replies: 0 :: Views: 1492
check AN 333: Developing Peripherals for SOPC Builder for detailed information about using ?Interface to User Logic?. It is also possible to connect your sram in this way.
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-17-2004 06:32 :: cube007 :: Replies: 1 :: Views: 1189
Can any one tell me how the program from PROM is transferred to sram and how the data is organized in the sram.
several configuration mode, let's use Xilinx as example, I use SelectMAP mode to download fpga data, which I like it very much, because I can still use the COnfiguration port as regular CPU port after the FPGA
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-19-2004 21:31 :: speedoak :: Replies: 5 :: Views: 892
Are you sure ur code is compiling clean???
I am getting compilation error for following line in code!!!
type memory_array is array(integer range 0 to 127,integer range 0 to 15);
Why are you trying to use two dimensional array for memory!
Only single dimension array is sufficient!
You can get free SARM VHDL models from sram manufaturer
ASIC Design Methodologies and Tools (Digital) :: 12-20-2004 08:46 :: nand_gates :: Replies: 4 :: Views: 1017
ROM & FLash & sram Collect
It's very useful for ROm emulator and MicronasControl Board.
In normal case ,you just need SSTFlash to develop.
Microcontrollers :: 01-03-2005 11:07 :: jones :: Replies: 0 :: Views: 745
You can refer to the sram library from TSMC. Usually, you can place psub contact and nsub contact at each of 8 or 16 cell. You can calculate the p-sub current from the EDR
Analog IC Design and Layout :: 06-03-2005 11:05 :: kwkam :: Replies: 14 :: Views: 3778
Who can tell me what's the difference
between Borderless sram and Bordered sram.
especially the layout difference.
Analog Circuit Design :: 01-10-2005 01:18 :: cpsean :: Replies: 2 :: Views: 577
Could somebody tell me where information on the control/status registers of the PXA270 Internal sram might be found?
On one hand, the PXA27x Developer's Manual states "the Internal sram consists of 4 blocks, control/status registers ...".
On the other hand, again the PXA27x Developer's Manual states "There are no associated registers for the In
Microcontrollers :: 01-18-2005 10:42 :: wurzelsepp :: Replies: 0 :: Views: 819
Register file compiler can produce small memory as sram compiler does. And I have compared two memory generated by the regfile compiler (regfile) and sram copiler (sram) respectively with the the same parameters and found that the regfile got smaller area and the sram have moer driving capability. Is it the main difference (...)
ASIC Design Methodologies and Tools (Digital) :: 01-19-2005 21:15 :: suituse :: Replies: 4 :: Views: 1820
I am new to HSPICE and digital circuit design at transistor level. I am trying to generate the VTC (Voltage Transfer Characteristic) of a 6T sram cell. Here is my simulated netlist,
MM5 q q-comp vdd vdd PMOS W=6 L=2 GEO=0
MM1 q q-comp gnd gnd NMOS W=3 L=2 GEO=0
MM6 q-comp q vdd vdd PMOS W=6 L=2 GEO=0
MM2 q-comp q gnd gnd NMOS W=3 L=2 G
Analog Circuit Design :: 01-22-2005 16:06 :: fgomezp :: Replies: 2 :: Views: 2394
I'm designing a synchronous onchip sram controller.
I'm wondering whether i should connect oen(output enable negative) always to the ground to let output not be high impedence.
Someone said it should be because high impedence will cause the circuit's power be very large.
Someone said that if i block high impedance from bus interface(just use a m
ASIC Design Methodologies and Tools (Digital) :: 04-19-2005 05:50 :: qslazio :: Replies: 4 :: Views: 762
Can you explain more on the physical structure of the sram cell. Is it 4T or 6T cell. For 6T cell, I never see such thing. By the way, have you calculate the substrate resistance and the leakage path of the storage node.
If you checked that your word and column decode have no problem. You have better check the sram cell.
Analog Circuit Design :: 04-24-2005 10:02 :: kwkam :: Replies: 6 :: Views: 1008