Search Engine

Sram Precharge

Add Question

1000 Threads found on Sram Precharge
I'm having trouble understanding the purpose of precharging the BLs during a read operation of a traditional sram. Is it because after a previous operation you want a common starting point (both bit lines being 1) so the sense amplifier can begin to sense the change in the BLs? Thanks everyone. I love this community.
Hello ahgu: precharge is avery importment step before you read another row in DRAM and sram. In DRAM, precharge will turn off active word line and precharge bit line pairs to ready state. If you ignore this procedure, bl and blb will have some voltage difference. After charge sharing, maybe the voltage difference will not (...)
In sram cells, we usually precharge the bit lines. We may use the p-type devices to precharge to full VDD. But does it improve only the writes and reads for logic 1, and makes slow memory access for logic 0? How can we handle the situation?
Hi.. As I understand question was regarding PMOS size in sram cell. As PMOS size is decreased in sram the stability of sram cell decreases. As per the critical path in sram I would suggest that it is not straight forward. There are 2 paths which are in race. 1.. Clock to Row Selection 2. Clock to (...)
can someone give info on the timers used in large sram arrays to synchronize the precharge(enable and disable),sense amp enable and disable in the same clock period. to use dummy slices or sdls to genrate the timers etc...
Hi all, I have a question about write operation of 6T sram I know for sram read: phy2 : precharge both bitlines high phy1 : Then turn on wordline, One of the two bitlines will be pulled down by the cell for sram write, my question is that during phy2, does the bitline and bitline_bar need to be (...)
Look up sram butterfly curves. You can't have all the transistors in the 6T cell as minimum.
Which sram architecture? Clocked or self-timed? Also, see here!
I'm searching for sram device to use with a Analog ADSP-21160. I don't understand the memory configuration of the device I found! 256K x 36 512K x 36 1Meg x 18.... Why this strange format? Why not a data widht of 16 or 32 bit?
Hi salamander, you have interface it parallel to your PIC. 1 pin for write 1 pin for read 1 pin for cs (not necessary) 8 pins for data 20 pins (2^20 = 1024) for address pins I think that you do not have so much pins on the pic. So you have to use a extra device (latch). How much pins are left for the connection to your sram? by,
Hi there, Could some one guide me as to how to get sram from Cypress Technologies working.........or if some one knows any verilog code for writing into sram plz post it in your reply . Aircraft Manic
a whitepaper on sram DPGA security
FPGAMCU.exe This application note shows how to reconfigure an sram based FPGA using a flash based microcontroller. The text for "Controlling FPGA Configuration with a Flash-Based Microcontroller" can be found by clicking on the Web site icon, or by dialing up Atmel's faxback system (1-800-29-ATMEL or International: 1-408-441-0732) or by re
Does anyone know how to measure power dissipation of memory block from sdf format? My design is work with sram block, and I need information how much power is being consumed in memory block. Please give me some information about this problem. I am mainly working with Cadence and Synopsys tools. THX.
This document is free available
I want to config Altera sram based FPGA (ex ACEX series) with AVR MCU+EEPROM by ps mode, because the smallest AVR mcu only have 6 IOs,and clk need 1, so I think I may tie e2prom's clk whith fpga's DCLK,tie e2prom's Dout with fpga's data0, I wang to see if it alwayes config successfully when I low nConfig,I first feed some dummy bits before the
Ask TSMC to give you the sram compiler, it is free of charge if you are their client !
Who has designed a controller module, for a QDR sram memory? I want to know, if there is any special point, that should be considered, while designing the controller module.
Can anybody tell me the differences of pipelined and flow-through syncronous burst sram like it is used for MPC555 or 565. I can see the additional registerbank in the pipelined version but what is the different behavior of both. Regards Max
Al Farouk, there is no following link posted! Also: i don;t understand multi-port RAM in the sense that i have not encountered generators for anything else than single- and dual-port. In my designs i often use multiple-output register banks which is different. I would like if some vendor provided sram-based configurable register banks.
Are there any other manufacturers besides ST who do flash/sram in same chip? ST's psd chips have to small sram and have IO cpld I don't need... Trying to reduce a FPGA's system IC count (o;
Cypress ( ) has a lot of Synchronous srams. They are working together with Micron. Some year ago Cypress bought the company Galvantech with all their RAM-production too. Bye, cube007
So, when someone says, data buffer, does it means, it could be either register(DFF) or RAM? In verilog coding, does it have different coding style to refer to data buffer using registers and to refer to RAM? In verilog, if I declare reg memory If the design goes to synthesis or layout, will it become df
Hi, Please tell which vendor offer radiation hard or radiation tolerant sram,especially SBsram. jerred
Can anybody help me to choose a good sram dual port to use with my Xilinx Virtex2 Pro that have few control signals and it is easy to use... Thanks...
Hi I need to design a circuit to generate 1.5v~2.4v precharge voltage for large cap load(10pf). But the working environment is too tough:1.6v~6v, temperature:-50C~150C. Besides the time response should not too slow(10ns~20ns). Any suggestion or comment on it? thanks in advance! regards, joran76
i think that better is to download the Data Sheet of sram whic you would use. After simply copy the waveform for Read And Write. is not to hard to make it.
I want to integrate flash , sram, eeprom and cpu core... on a single silicon, how to do that?
hi, i need to design a board containing 1MB sram, 1MB of flash(for program) and 1MB of EEPROM(for data) together with adsp-bf531,I am planning to initialize data and program address in sram at the time of problem is how to load data from flash and EEPROM to the addresses initialized in sram, do i have to do it with the help of proce
Is there a COTS based integrated EDAC sram available? Are there EDAC controllers that can be interfaced with srams? Thanks, delay (delay by technology)
Can anybody introduce me how to do the following 6-T sram bit cell analysis with Hspice: 1.Standby current on VDD; 2.Read and Write Margin; 3.bit-lin leakage I have tried to simulate the standby current on VDD. I set BL,BL_ and WL to 0, and also using ic(Q)=1.8v(I simulate with 018u logic process model card). I find i(VDD) is very close to ze
Does anybody know how to wirte Hspice input file to calculate 6-T sram's Static Noise Margin(SNM)? Thanks.
Asynchronous sram need controller?
Hi, The cache and sram may be adjusted only during startup. I do not think that it is possible in runtime. Setting up is normally explained in the users amnual. (eg: Blackfin) Hope this helps, B R M
Look at tis website
I think is the same number. Even I am confused for you question. sram DRAM differ in way of handling.
Hi all, Could someone please explain what is the different between async sram and sync sram? Thanks & best regards.
Hello FrEEk, check AN 333: Developing Peripherals for SOPC Builder for detailed information about using ?Interface to User Logic?. It is also possible to connect your sram in this way. Bye, cube007
Can any one tell me how the program from PROM is transferred to sram and how the data is organized in the sram. several configuration mode, let's use Xilinx as example, I use SelectMAP mode to download fpga data, which I like it very much, because I can still use the COnfiguration port as regular CPU port after the FPGA
Are you sure ur code is compiling clean??? I am getting compilation error for following line in code!!! type memory_array is array(integer range 0 to 127,integer range 0 to 15); Why are you trying to use two dimensional array for memory! Only single dimension array is sufficient! You can get free SARM VHDL models from sram manufaturer
ROM & FLash & sram Collect It's very useful for ROm emulator and MicronasControl Board. In normal case ,you just need SSTFlash to develop.
You can refer to the sram library from TSMC. Usually, you can place psub contact and nsub contact at each of 8 or 16 cell. You can calculate the p-sub current from the EDR
Question: Who can tell me what's the difference between Borderless sram and Bordered sram. especially the layout difference. Thanks
Could somebody tell me where information on the control/status registers of the PXA270 Internal sram might be found? On one hand, the PXA27x Developer's Manual states "the Internal sram consists of 4 blocks, control/status registers ...". On the other hand, again the PXA27x Developer's Manual states "There are no associated registers for the In
Register file compiler can produce small memory as sram compiler does. And I have compared two memory generated by the regfile compiler (regfile) and sram copiler (sram) respectively with the the same parameters and found that the regfile got smaller area and the sram have moer driving capability. Is it the main difference (...)
Hi, I am new to HSPICE and digital circuit design at transistor level. I am trying to generate the VTC (Voltage Transfer Characteristic) of a 6T sram cell. Here is my simulated netlist, MM5 q q-comp vdd vdd PMOS W=6 L=2 GEO=0 MM1 q q-comp gnd gnd NMOS W=3 L=2 GEO=0 MM6 q-comp q vdd vdd PMOS W=6 L=2 GEO=0 MM2 q-comp q gnd gnd NMOS W=3 L=2 G
I'm designing a synchronous onchip sram controller. I'm wondering whether i should connect oen(output enable negative) always to the ground to let output not be high impedence. Someone said it should be because high impedence will cause the circuit's power be very large. Someone said that if i block high impedance from bus interface(just use a m
Can you explain more on the physical structure of the sram cell. Is it 4T or 6T cell. For 6T cell, I never see such thing. By the way, have you calculate the substrate resistance and the leakage path of the storage node. If you checked that your word and column decode have no problem. You have better check the sram cell.