9 Threads found on edaboard.com: Sram Precharge
precharge is avery importment step before you read another row in DRAM and sram. In DRAM, precharge will turn off active word line and precharge bit line pairs to ready state. If you ignore this procedure, bl and blb will have some voltage difference. After charge sharing, maybe the voltage difference will not (...)
Professional Hardware and Electronics Design :: 09.05.2002 12:52 :: maskrom :: Replies: 5 :: Views: 11633
In sram cells, we usually precharge the bit lines. We may use the p-type devices to precharge to full VDD. But does it improve only the writes and reads for logic 1, and makes slow memory access for logic 0?
How can we handle the situation?
ASIC Design Methodologies and Tools (Digital) :: 23.11.2006 13:12 :: spartacus2 :: Replies: 1 :: Views: 734
As I understand question was regarding PMOS size in sram cell.
As PMOS size is decreased in sram the stability of sram cell decreases.
As per the critical path in sram I would suggest that it is not straight forward.
There are 2 paths which are in race.
1.. Clock to Row Selection
2. Clock to (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 27.12.2006 10:14 :: nitu :: Replies: 3 :: Views: 819
can someone give info on the timers used in large sram arrays to synchronize the precharge(enable and disable),sense amp enable and disable in the same clock period.
to use dummy slices or sdls to genrate the timers etc...
ASIC Design Methodologies and Tools (Digital) :: 05.02.2007 11:05 :: atul799 :: Replies: 0 :: Views: 566
During read operation, the BL remains VDD (slightly down in simulation), while BL_ decrease or vice versur until the voltage difference is about 100mV (mostly). But what I could not understand is why both the bit line voltage rise to VDD after the access transistor is turned off. It's due to leadage?
Anyone could help me? Thanks in advance..
ASIC Design Methodologies and Tools (Digital) :: 02.09.2008 04:50 :: iamxo :: Replies: 3 :: Views: 674
For read operation, we need a precharge circuit to charge the bit lines. I know the precharge circuit for two bit lines.
How the precharge circuit for single bit line would look like???
Analog IC Design and Layout :: 10.04.2010 09:07 :: raman_87 :: Replies: 1 :: Views: 594
I have a question about write operation of 6T sram
I know for sram read:
phy2 : precharge both bitlines high
phy1 : Then turn on wordline, One of the two bitlines will be pulled down by the cell
for sram write, my question is that during phy2, does the bitline and bitline_bar need to be (...)
Analog Circuit Design :: 27.08.2013 19:26 :: onion2014 :: Replies: 0 :: Views: 306
Does anyone know how to measure power dissipation of memory block from sdf format?
My design is work with sram block, and I need information how much power is being consumed in memory block.
Please give me some information about this problem. I am mainly working with Cadence and Synopsys tools.
ASIC Design Methodologies and Tools (Digital) :: 18.02.2003 23:43 :: kokmin :: Replies: 2 :: Views: 1533
I have a problem with my spice codes. When I add the precharge circuit, the error appears.
I have this problem only with finfet model. With other types, it works.
.option accurate=1 method=gear delmax=30p
.OPTIONS ABSTOL=1p VNTOL=1u
Analog IC Design and Layout :: 04.12.2010 07:19 :: rosaeidi :: Replies: 6 :: Views: 1528