13 Threads found on edaboard.com: Sram Precharge
I am currently working on 6T sram cell.
I am trying to measure the leakage power dissipation of the sram during HOLD state. I turned of the access transistors and performed operating point analysis using NGSPICE.
Even though i am able to calculate the leakage current, i also observed that the contents in the external bit and bit bar lines chang
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-14-2016 13:08 :: ashR :: Replies: 4 :: Views: 361
Why it's necessary to open/close pages while working with sram? What does it mean?
What does the term "precharge" mean in terms of sram?
What does the term "bank" mean in terms of sram? Does saying "close the sram bank" mean the same as "close the sram row"?
ASIC Design Methodologies and Tools (Digital) :: 07-07-2015 14:46 :: ivlsi :: Replies: 4 :: Views: 421
I am creating a 4x4 6T sram array and i want to know that
1) what will be the idle writing and reading time for which the word line should high for 6T sram?
2)whenever i turn on the wordline after precharge the bitline and bitline bar gets discharged frequently why?
Analog Circuit Design :: 04-01-2015 05:32 :: oly :: Replies: 0 :: Views: 373
What are the typical values of Capacitors of BitLine and Bitline Bar in a 6T conventional sram cell in 16nm PTM?
Analog Circuit Design :: 12-25-2014 08:35 :: electronics20 :: Replies: 1 :: Views: 537
I have designed a 6T sram cell along with precharge circuit as depicted in attached Fig. However, I dont know what pulse is appropriate for the gate of precharge circuit (ΦB`) since precharge circuit bears the responsibility of making both BL and BLB high only before read action.
plz help. thanks a lot.
Analog Circuit Design :: 12-25-2014 07:31 :: electronics20 :: Replies: 1 :: Views: 651
Which sram architecture? Clocked or self-timed? Also, see here!
Analog Circuit Design :: 08-05-2014 17:12 :: erikl :: Replies: 3 :: Views: 1841
Look up sram butterfly curves. You can't have all the transistors in the 6T cell as minimum.
ASIC Design Methodologies and Tools (Digital) :: 04-30-2014 09:26 :: jbeniston :: Replies: 3 :: Views: 657
I'm having trouble understanding the purpose of precharging the BLs during a read operation of a traditional sram.
Is it because after a previous operation you want a common starting point (both bit lines being 1) so the sense amplifier can begin to sense the change in the BLs?
Thanks everyone. I love this community.
ASIC Design Methodologies and Tools (Digital) :: 12-04-2013 19:44 :: mspagon :: Replies: 1 :: Views: 680
I have a question about write operation of 6T sram
I know for sram read:
phy2 : precharge both bitlines high
phy1 : Then turn on wordline, One of the two bitlines will be pulled down by the cell
for sram write, my question is that during phy2, does the bitline and bitline_bar need to be (...)
Analog Circuit Design :: 08-27-2013 23:26 :: onion2014 :: Replies: 0 :: Views: 665
For read operation, we need a precharge circuit to charge the bit lines. I know the precharge circuit for two bit lines.
How the precharge circuit for single bit line would look like???
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 04-10-2010 13:07 :: raman_87 :: Replies: 1 :: Views: 797
can someone give info on the timers used in large sram arrays to synchronize the precharge(enable and disable),sense amp enable and disable in the same clock period.
to use dummy slices or sdls to genrate the timers etc...
ASIC Design Methodologies and Tools (Digital) :: 02-05-2007 16:05 :: atul799 :: Replies: 0 :: Views: 835
As I understand question was regarding PMOS size in sram cell.
As PMOS size is decreased in sram the stability of sram cell decreases.
As per the critical path in sram I would suggest that it is not straight forward.
There are 2 paths which are in race.
1.. Clock to Row Selection
2. Clock to (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-27-2006 15:14 :: nitu :: Replies: 3 :: Views: 1086
In sram cells, we usually precharge the bit lines. We may use the p-type devices to precharge to full VDD. But does it improve only the writes and reads for logic 1, and makes slow memory access for logic 0?
How can we handle the situation?
ASIC Design Methodologies and Tools (Digital) :: 11-23-2006 18:12 :: spartacus2 :: Replies: 1 :: Views: 938