Search Engine www.edaboard.com

Sram Precharge

Add Question

9 Threads found on edaboard.com: Sram Precharge
Hello ahgu: precharge is avery importment step before you read another row in DRAM and sram. In DRAM, precharge will turn off active word line and precharge bit line pairs to ready state. If you ignore this procedure, bl and blb will have some voltage difference. After charge sharing, maybe the voltage difference will not (...)
In sram cells, we usually precharge the bit lines. We may use the p-type devices to precharge to full VDD. But does it improve only the writes and reads for logic 1, and makes slow memory access for logic 0? How can we handle the situation?
How the size of pmos transistor affects the performance of sram and what is meant by critical path in sram
can someone give info on the timers used in large sram arrays to synchronize the precharge(enable and disable),sense amp enable and disable in the same clock period. to use dummy slices or sdls to genrate the timers etc...
During read operation, the BL remains VDD (slightly down in simulation), while BL_ decrease or vice versur until the voltage difference is about 100mV (mostly). But what I could not understand is why both the bit line voltage rise to VDD after the access transistor is turned off. It's due to leadage? Anyone could help me? Thanks in advance..
For read operation, we need a precharge circuit to charge the bit lines. I know the precharge circuit for two bit lines. My question: How the precharge circuit for single bit line would look like???
Hi all, I have a question about write operation of 6T sram I know for sram read: phy2 : precharge both bitlines high phy1 : Then turn on wordline, One of the two bitlines will be pulled down by the cell for sram write, my question is that during phy2, does the bitline and bitline_bar need to be (...)
Does anyone know how to measure power dissipation of memory block from sdf format? My design is work with sram block, and I need information how much power is being consumed in memory block. Please give me some information about this problem. I am mainly working with Cadence and Synopsys tools. THX.
Hi I have a problem with my spice codes. When I add the precharge circuit, the error appears. I have this problem only with finfet model. With other types, it works. .option accurate=1 method=gear delmax=30p .OPTIONS ITL1=100 .OPTIONS ITL4=100 .OPTIONS RELTOL=.01 .OPTIONS DIGSTEPBACK .OPTIONS ABSTOL=1p VNTOL=1u .OPTIONS METHOD=GEAR