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14 Threads found on Ssram
OK so I was confused for the last 2 days on what is going and what figured out what the actual problem is that is making it difficult to follow Altera documentation. It seems that there is a bug in the program. I am using Altera Quartus II 15.0 64 bit. I select SRAM/ssram controller from the IP catalog. Then I click generate HDL and select Veril
Hello, I m working on a Altera DE2-70 board, and i need simple vhdl/verilog programs to make use of all the resources in the system. The available resources are ? 2-Mbyte ssram ? Two 32-Mbyte SDRAM ? 8-Mbyte Flash memory ? SD Card socket ? 4 pushbutton switches ? 18 toggle switches ? 18 red user LEDs ? 9 green user LEDs ? 50-MHz oscil
I guess you are talking about synchronous RAM (ssram)? Why not asking the datasheet?
Hello, Does anyone have and could share schematics (best for gEDA sofware) with actel and external ssram/sdram. I'm not sure how to design io connection between them. I'm thinking about actel devices without embeded cortex-m1 block where some ip core for memory controller will be needed. Do you konw what does it cost of Actel's "coreddr" and
Hello everybody! I am an absolute beginner in this field, but I would like to use FPGA. I bought (well, my boss did) a NEEK (NIOS embedded evaluation kit) which implements a Cyclone III device. I am using the latest tools (Qartus 9.1 sp1, and NIOS IDE 9.1). In order to understand the basics, I first built a led blinking program. 1. In
i try to controll ssram... but my ssram controller works bad my board is DE2-70, ssram model name is issi is61lps51236a i write my verilog code.... module ssram_ctrl(input wire CLK_200, // clock output reg oSRAM_A, // address output reg oSRAM_ADSC_N, // controller address status output reg oSRAM_ADSP_N, // (...)
Hello dear friends. Please, help me understand some things about ssram(cypress). Get, for example, CY7C1381C. In datasheet we see that it is 512K X 36/1M X 18 Flow-Thru sram. What does it means? What amount of memory we have? I see only 19 pins of address bus. With 19 pins we can address only 512kbytes. A0 and A1 pin used for burst counter. If I
See CY7C1470 on Cypress website for ssram, and MT48LC16M16 on Micron for SDRAM
Can some body suggest me literature about ssram and SDRAM, their application in FPGA design and DSP circuits
Please provide me any links or information for coding SRAM controller in verilog for CYPRESS ssram chip. Thank You.
Hi, can anybody tell me the gross area of the following ssram chips: <1> a single-port ssram 128*32: <2> a dual-port ssram 123*32: <3> a single-port 256*8: <3> a dual-port 256*8: <4> a single-port 256*32: <5> a dual-port 256*32: The fabricating process is 0.18um! Thanks a lot! Thomson
Hallo fellow members... i have question on JTAG usage. i recall that JTAG used to add wait states in order to perform the scan. While one of their docs stated that this was inevitable, i remember running code on ARM from ssram (external static RAM). (this was done because we ought to disable the cache/scratchpad RAM to perform some current me
Dear my friends, I need a good vhdl model of ssram (including timing). Thanks,
Dear my friends, I want to design a ssram based queue with diffrent clock rate at input and output. I test some idea but these are not good. I need some stuff. Thanks,