standard and cell and rise and fall and

question about standard cell library

hican anyone tell me which cell should we include in a cell library?thankselika...
ASIC Design Methodologies & Tools (Digital) :: 14 Sep 2009 20:17 :: srpatel9 :: Replies: 3 :: Views: 303

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characterisation of standard cell library

hi,iam presently studying about characterisation of cell library.i down loaded a .13u library from www.vlsitechnology.org .a sample is given below//power characterisation for an input pin of and gatepower_lut_template(pwr_x2_676_5x10) {variable_1 : i...
ASIC Design Methodologies & Tools (Digital) :: 03 Sep 2009 16:16 :: tomorrowglue :: Replies: 1 :: Views: 231

a lot interview questions with resposes

hi all,here is a nice collection of interview questions with reponses:cmos interview questions.1/ what is latch up?latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or scr) is in...
EDA Jobs, Promotions, Advertising :: 21 Jan 2009 9:03 :: sridhar540 :: Replies: 15 :: Views: 8816

layout of standard cell

hi.................... can any body tell me that how can i improve the area power and delay of standard cell like flip flops and latches. and what iss the responsebilities of standard cell library development engineer. plz help me...
ASIC Design Methodologies & Tools (Digital) :: 19 Apr 2008 5:17 :: srp :: Replies: 9 :: Views: 762

standard cell 1x driving strength, gate sizing, delay

dear all,i m doing standard cell of library. different gates have different gate sizing that will satisfy systhsis request.for all types of driving strength in standard cell, i m no idea how to decide the normal(1x) condition.e.g.--------------------...
ASIC Design Methodologies & Tools (Digital) :: 31 Jan 2008 12:58 :: Chethan :: Replies: 16 :: Views: 660

input capacitance of combination gate

for one nand2 gate, i run simulation(use lx(m)) and get the capacitances of two input ports. after i check two different standardcell libraries, there are two different result.(pmos size of a and b are equal. nmos size of a and b are equal too)one , ...
ASIC Design Methodologies & Tools (Digital) :: 15 Jan 2008 4:09 :: rain_181914 :: Replies: 6 :: Views: 174

standard cell library achitecture

hi,recently i encounter the following problem when i want to design a standard libray under submicron soi technology.as follow1 how to ascertain unit drive strenth ,such as invx1?2 how to acquire the p/n width ratio of invx1?addtionally,whats the dif...
ASIC Design Methodologies & Tools (Digital) :: 14 Jul 2007 23:54 :: eternal_nan :: Replies: 4 :: Views: 375

standard cell&i/o library

how much loading is added when we simulate the standard cell and i/o? and how to decide the w and l of mosfets? what parameters do we care? fall time? rise time? setup time? hold time?...
Analog Circuit Design :: 19 Jun 2007 6:01 :: ronialeonheart :: Replies: 9 :: Views: 282

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