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118 Threads found on Standard And Vhdl
I'm guessing the types for a and b should be signed from numeric_std? I know that you might think of std_logic_signed, std_logic_arith, but no one should use them, instead, the standard. -- Id: A.2 function "-" (ARG: SIGNED) return SIGNED; -- Result subtype: SIGNED(ARG'LENGTH-1 downto 0). -- Result
1. WIDTH is a reserved vhdl name (standard attribute) and shouldn't be used for a generic. 2. There's little use of putting a fixed parameter in a generic. You better use a constant. In practice there may be cases where you wanted to write parameterizable code but took a short cut at some point. So it works with the (...)
The resource utilization of a look-up table implemented in logic cells will strongly depend on the actual table data because it undergoes the standard process of logic minimization during synthesis. A look-up table with little resource usage can be implemented in block RAM, provided your FPGA family has it.
SystemC is the standard for SoC exploration and model IP sharing. As the EDA vendors have integrated SystemC with their Verilog/vhdl simulators, the system analysis model can also be used for early verification. Unfortunately, model construction is very tedious in SystemC, can take months for one IP, and (...)
try using ieee.numeric_std rather than std_logic_arith, because std_logic_arith is not a standard vhdl library. Please post the whole code with the problem, rather than an out of context snippet.
Then the problem is you havent compiled the fixed_pkg code into the ieee_proposed library. ieee_proposed is not a standard vhdl library - it was a '93 compatible version of the new code added to vhdl 2008 to allow people to compile designs in software without 2008 compatibility. So you either need to switch to 2008 code : (...)
You'll notice that all vhdl experts suggest to use IEEE standard library numeric_std instead of outdated std_logic_arith and related libraries. If you are however stuck with the legacy libraries for some reason, you have to use the respective type conversion functions, e.g. conv_signed() instead of to_signed(). - - - Upd
O.K., HREAD (=hexread) is a function from stdlogic_texio, a non-standard Synopsys library.
There are problems here because you have included both numeric_std and std_logic_arith in your code. They both define signed and unsigned types - causing a conflict that means you cannot see either type without directly using them. The solution is to remove std_logic_arith as it is not a standard vhdl (...)
the textio package only covers std.textio for types defined in std.standard - integer, real, bit_vector etc. std_logic_textio was defined by synopsys (so is not a standard vhdl package) as a way to directly read/write std_logic_vectors without having to first convert to bit_vector or integer or the like, (...)
There is no write function for numeric std. You have a few options: 1. Include the non-standard std_logic_textio package and convert your unsigned to a std_logic_vector before using the write, owrite or hwrite functions 2. Convert the unsigned to an integer or bit_vector 3. Use vhdl 2008. Each package has textio functions (...)
You just confused the coefficient order. Rather than having c(0) = 1 as assumed in the first code, you have actually c(0) = 4. and so on. By the way. Why in 2015 people are still starting vhdl with the non-standard Synopsys library std_logic_unsigned?
Hi guys, I'm implementing a certain packet decoder. The incoming packet is sliced according to certain ranges defined in a standard. I want to define the slice ranges in a package so that my code is readable and generic at the same time. For example if I'm slicing the control_field then I want to write for example frame_length <
HI, Can we design a look-up table without targeting to FPGA , means using standard FETs in cadence. ? I am new to look up table and vhdl. thanks
Unlike Verilog $readmemb(), there's no standard method to import ROM data to design tools. Some tools understand vhdl files for inferred ROM, some can import hex files for vendor ROM macros. Generating a *.VHD file with a constant array is probably the most portable method.
aside from the non-standard coding style, the problem comes because you are using a signal in a for loop. Signals get assigned when a process suspends, not immediatly (like a variable). So in your case every element in the array is compared to 0, and it will find the last element larger than zero, as a signal takes the last value assigned to (...)
Use Design Compiler to synthesize the Verilog RTL into a Verilog gate-level netlist. Then you can import the Verilog netlist into Synopsys Custom Designer, if you have it, and simulate through that. If not, providing you have the transistor levels models for the standard cells, you should be able to simulate with that. You will just need (...)
This is just a standard N tap FIR. First of all, I suggest you bring in all C co-efficients separately, not as a single bus. Second, for N taps, you will probably need a package to create the array types to make the design generic. I dont know why you have declared RAM and ROM types - there is no RAM or ROM in your drawings. They are just (...)
So what is the problem? Can you post the testbench? why cant you just put a sign bit on the front of the unsigned number? the problem here is you're using the non-standard std_logic_signed library, so you cannot do signed and unsigned arithmatic in the same file. You need to use the signed/unsigned types from numeric_std, (...)
This is just the standard, but you havent posted the problem.
Hi Guys,So sorry my first post here would be requesting for help.I am currently doing a project which is writing a Data Encryption standard(DES)using vhdl,I am currently halfway done but I am having trouble reading from a input file.I entered 3 inputs and it could be written to a file.But when I put the 3 inputs in a file (...)
The main difference is SXT/EXT are for std_logic_vectors. Resize is for signed/unsigned types. SXT/EXT are non-standard vhdl EXT zero extends the std_logic_vector. SXT sign extends. EXT and SXT are both from the non-standard package std_logic_arith. resize always extends based on (...)
sLeds <=conv_std_logic_vector(tState'pos(sMainState), sLeds'length); and here is how to do it with the standard library numeric_std: sLeds <= std_logic_vector(to_unsigned(tState'pos(sMainState),sLeds'length));
Usuallly while loops aren't supported for synthesizable vhdl. This is specified in IEEE 1076.6-2004 (RTL synthesis) and also applies to tools not strictly following this standard. Technically, only loops with "bounded" iteration number can be synthesized, because they are enrolled to parallel logic. The shown snippet (...)
You are trying to include vhdl standard libraries in Verilog. The library and use keywords are unknown in Verilog.
hello! i have a problem in vhdl and i hope you can help me i want to take LS bits from a signal, but the number of these bits it's not certain. to be more specific, i want to do this: a <= b(x-1 downto 0). a, b, x are std_logic_vectors. x is calculated somewhere else in my program. range of a should be x bits, range of b is 54 bits, ra
Yes, that is the standard way of generatin and distributing many clocks from a single clock input in an FPGA. Open coregen and search for DCM (Digital Clock Manager). There will be a link to the datasheet. r.b.
the std_logic_arith and numeric_std both define unsigned type, so you cannot see either without being explicit eg: signal my_us : numeric_std.unsinged(3 downto 0); To avoid this, you should not use the non-standard std_logic_arith library, and stick withe the IEEE standard numeric_std instead.
Dear friends, I'm trying to create layout using SoC Encounter. these are the steps i follow: 1.loading my vhdl code into synopsys design vision 2.compiling the design using "lsi10k" library as link, target and symbol library. 3.creating verilog gate level netlist and sdc file. 4.loading verilog gate level netlist, timing libraries (...)
@trickydicky.. Just intruding into pradeepa thread.. 1. Irrespective of using variable logic as pradeepa mentioned here or a standard template, the synthesis will lead to same schematic at the output.. am i right? 2. But the space EEPROM occupied by program and execution time are high in this logic than (...)
bit and bit vector are defined in the std.standard package, which is included in ALL vhdl files by default.
They are different. One is an IEEE standard (to_integer) and one is not standard vhdl (conv_integer). Also, to_integer converts unsigned/signed type. Conv integer converts std_logic_vectors. So, to do standard vhdl, you should use (...)
i want to implement the following operation in vhdl: x(52:0) = y(23:0) >> z (>> is the logical right shift) value of z is not standard, it's the result of a substraction and it can change. i already tried operator srl and function shift_right but they don't work because of the different width of (...)
yes. First of all delete the std_logic_arith and std_logic_unsigned libraries - they are non-standard vhdl libraries. Also, std_logic_arith conflicts with numeric_std, hence another reason to delete it. finally, you cannot resize a std_logic_vector. You need to resize a signed or unsigned type. so you need to cast a (...)
Probably not in any easy way you would like. You'd need some sort of standard way to go between the SV language constructs and vhdl. That would mean either you write some wrappers or you find some collection of macros/whatevers that do this work for you. Now the problem of "use UVM with vhdl with maximum (...)
You will have to existing standard cell library to which you vhdl/verilog code synthesizes to. Once you import the gate level netlist into cadence it needs to map to the actual gate which should exist in the cadence library(if you have one). Once you get the library, then you dump the netlist and layout from the (...)
the standard template for a register with async and synchronous reset is this: process(clk, reset) begin if reset = '1' then --do async reset here elsif rising_edge(clk) then if sync_reset = '1' then --sync reset here else --normal logic end if; end if; end process; You cannot reset on a "chang
i have a vhdl code ...and we have standard cell in cadence in the front end. How can i import vhdl CODE into cadence and link it with standard cells and simulate it? Pl Help
Hi, In my design i synthesize the vhdl description using Synopsys Design Compiler and got the following figures for Power Consumption on 45nm standard cell asic tecnology. 1) Total dynamic power = 36.1 mWatt 2) Total leakage power = 1.20 mWatt. Now, i want to estimate the expected power consumption (keeping in view (...)
No, you cannot use std_logic_vector for arithmatic with standard vhdl, because it does not represent a number, just a collection of bits. You should use the the signed and unsigned types instead, and yes multiply and division functions exist for these (but I wouldnt use the divide, because (...)
its really up to you. SRAM controllers are fairly standard, so in a real world design you'd probably just pull one "off the shelf" and make your own FIFO controller to interface to it.
there is no + for std_logic_vectors in standard vhdl. You need to use signed/unsigned types in the numeric_std package.
This code does not conform to any standard templates. Did you write the code, or get disgnworks to export it? What simulator are you using? I am not familiar with design works. This code probably wont synthesise for an FPGA because of the odd coding stule and the use of internal tristates. But the runtime error points to a variable (...)
"Range bound must be a constant." Yes, it's required by the vhdl standard. The usual solution is to iterate over the full index range and add a condition that performs the intended operation only for the actual selected range. There's however a problem beyond simple vhdl syntax. You should consider that (...)
At first sight, mzakharo has done a great job in implementing a NIOS-free ISP1362 interface. I wonder if the device should use a standard device class like HID to make use of the generic PC drivers.
you cannot do unsigned+ with std_logic_signed. they are different. std_logic_signed works on std_logic_vectors. It is NOT part of the vhdl standard. You cannot do unsigned arithmatic in the same file. numeric_std works on signed and unsigned types. It is part of the vhdl (...)
first of all: you shouldnt use std_logic_arith and numeric_std in the same file. They have conflicts. The standard library is numeric_std. Secondly - you havent said what problems you are having?
Dear all, I am facing a problem while simulating a vhdl design. I am using 'ncvhdl' from Cadence for simulation, and I am trying to use asserts along the simulation. In particular, I have the following code: -- standard includes library IEEE; use IEEE.STD_LOGIC_1164.ALL; use (...)
Hi everyone. I have a college work where I have to use a vhdl file that was given to me. But whoever made this file used std_logic_arith. So I went and converted it to numeric_std. So far so good, but now I had to add some content, and it's failing to work. I have to use the SLL operator with std_logic_vector. I know it's not ideal, (...)
Your code, while getting the idea across has a couple of problems: - Counter is of type std_logic_vector but you're doing math with it (adding 1). This implies that you're using non-standard package std_logic_arith but you didn't include the statement to use std_logic_arith in your code. Counter should be of type unsigned and the (...)