241 Threads found on edaboard.com: Standard Ieee
As said in the standard, you can set default value in the entity declaration like
input_data : in std_logic_vector(7 downto 0):= "00000000";
If you left that port (input_data) open, no error will be reported. You do this in the component declaration on the parent design block.
PLD, SPLD, GAL, CPLD, FPGA Design :: 01-07-2017 12:46 :: sherif123 :: Replies: 4 :: Views: 1107
Are there any EDA tools available that support ieee Std 1735?-2014 standard (a.k.a. p1735 v2) IP encryption? Also, how can I encrypt my IP to make them compliant with ieee p1735 v2 standard?
Professional Hardware and Electronics Design :: 12-18-2016 05:08 :: vpopli :: Replies: 1 :: Views: 1197
In most cases (i.e. ignoring special values in the ieee floating point standard such as infinity and NaN), the only difference between a fixed and floating point implementation is that with floating point you will add a little extra stage which locates the most significant set bit (i.e. the most significant '1', assuming unsigned numbers). The loca
Digital Signal Processing :: 10-16-2016 00:02 :: weetabixharry :: Replies: 2 :: Views: 590
try using ieee.numeric_std rather than std_logic_arith, because std_logic_arith is not a standard VHDL library.
Please post the whole code with the problem, rather than an out of context snippet.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-09-2016 10:51 :: TrickyDicky :: Replies: 15 :: Views: 509
You'll notice that all VHDL experts suggest to use ieee standard library numeric_std instead of outdated std_logic_arith and related libraries.
If you are however stuck with the legacy libraries for some reason, you have to use the respective type conversion functions, e.g. conv_signed() instead of to_signed().
- - - Upd
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-28-2016 15:12 :: FvM :: Replies: 15 :: Views: 681
For IO testing we do boundary scan also known as JTAG(ieee 1149.1 standard). This includes EXTEST which test the I/O's as well as the logic between two blocks.
One more method is to use NAND tree test for IO testing which includes the insertion of NAND tree structure at all IO pads on the chip.Then apply your NAND tree pattern and observe the outpu
ASIC Design Methodologies and Tools (Digital) :: 03-22-2016 08:29 :: shalin mandiwala :: Replies: 1 :: Views: 495
Follow the ieee standard 1241 about ADC measurement methodology. Apply sinusoidal wave to the input and sampling it with numbers of samples≥2^N and make FFT of collected samples to get SINAD. Next calculate ENOB from formula ENOB=(SINAD-1.76)/6.02
Of course the sampling frequency cannot be an integral multiplicity of input signal frequency to
RF, Microwave, Antennas and Optics :: 02-28-2016 12:29 :: Dominik Przyborowski :: Replies: 3 :: Views: 924
Hi people How are you All ,
I hope you are all fine ,
I think It will be helpful for beginners like me if any/some of the Experienced members make a Complete Comprehensive tutorial that will pinned about the following points related to each of the international standard organizations involved in Telecommunication Study and Industry :
Professional Hardware and Electronics Design :: 01-05-2016 22:20 :: eng_boody :: Replies: 2 :: Views: 770
Tricky question because if you use some conceptual design as shown it is not real design, then all you can use are block diagrams.
Then you must dream up your own logic symbols using standard shapes and text.
Not very good for detail oriented Engineers but perhaps ok for your purposes.
For example the Johnson counter you have shows
Software Recommendations :: 08-09-2015 21:23 :: SunnySkyguy :: Replies: 10 :: Views: 127
The standard is covered by the free "ieee Get" program
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-21-2015 15:44 :: FvM :: Replies: 5 :: Views: 581
Sarathkumarkj, you need to update your quiz to the 21st century. There is no longer an ieee Verilog standard. it has been replaced by ieee 1800 in 2009, the current revision is 1800-2012
ASIC Design Methodologies and Tools (Digital) :: 06-04-2015 15:14 :: dave_59 :: Replies: 8 :: Views: 1879
Just curious on everyone's opinion of numeric_std_unsigned in the recent VHDL2008 standard. The most cited reason against using std_logic_unsigned was its origin at synopsys, followed by concerns that the code would not be portable. Now that ieee has recreated (and updated) the package, will the advice be to move to numeric_std, or numeric_std_un
PLD, SPLD, GAL, CPLD, FPGA Design :: 05-26-2015 19:32 :: vGoodtimes :: Replies: 0 :: Views: 538
According to this article, effect on frequency shift may be negligible if we consider the intrinsic standard error associated to crystal frequency:
RF, Microwave, Antennas and Optics :: 05-24-2015 12:53 :: andre_teprom :: Replies: 4 :: Views: 1020
Can somebody help me to find ieee standard for mm wave frequencies in Radio over fiber link?
I am using a 30 GHz wave in my radio over fiber link and I need to know what should be the power of my transmitted data? In the receiver side I need to know which sensitivity is acceptable for the receiver.
Your help is appreciated.
RF, Microwave, Antennas and Optics :: 05-20-2015 20:21 :: Natasha123 :: Replies: 0 :: Views: 348
in page 78 of ieee 159 standdard (1992) - table 10.2 : it was written that for low voltage application the voltage THD must be less than 5%.
my question is what is the exact value of low voltage? what is the range of low voltage? less than 100v ? or ....116001
Power Electronics :: 03-28-2015 12:48 :: zizi110 :: Replies: 0 :: Views: 499
While on the subject of typing, this massive load of package uses is a fairly standard way to confuse yourself (...)
PLD, SPLD, GAL, CPLD, FPGA Design :: 02-09-2015 08:13 :: TrickyDicky :: Replies: 2 :: Views: 797
Welll, exactly one trivial google and less than 10 seconds away:
1735 IP Encryption and Rights Management
As part of its Plug-and-Play IP initiative, Xilinx has adopted the ieee P1735 encryption standard to ensure interope
PLD, SPLD, GAL, CPLD, FPGA Design :: 12-18-2014 12:28 :: mrflibble :: Replies: 3 :: Views: 1609
hi all. i am working on developing 100G Ethernet PCS based on ieee std.802.3bj-2014.
i am confused about the scrambler and 256B/257B transoder.
the tx flow described in ieee 802.3bj-2010 standard is below:
Encode -> Scramble -> Block Distribution -> Alignment Insertion
-> Lane block sync -> Alignment block removal -> Transode -> (...)
Digital communication :: 11-27-2014 05:21 :: ember.cc :: Replies: 0 :: Views: 683
can you help me to solve the below error
I am running vsim -t ps -sdfmin /tb_msp=output.sdf -c tb_msp
vsim -t ps -sdfmin /tb_msp=output.sdf -c tb_msp
# vsim -c -sdfmin /tb_msp=output.sdf -t ps tb_msp
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading work.target
# Loading ieee.std_logic_arith(
PLD, SPLD, GAL, CPLD, FPGA Design :: 10-20-2014 05:04 :: abu9022 :: Replies: 3 :: Views: 1739
i am a student and got a project for "implementation of a channel equalizer for a wireless OFDM according to the ieee 802.11a and Hiperlan/2 standard."
i dont have knowledge about system level design environments for DSPs into FPGAs..,what i have is this ieee paper and nothing else,
i was unable to gain knowledge on (...)
Digital Signal Processing :: 10-08-2014 09:05 :: nick123 :: Replies: 0 :: Views: 677
This types of problem happens when generated evcd format does not meet the evcd ieee 1364 standard. For that you just need to check the PLI you used during simulation/ during evcd generation.
If evcd does not meet the standard, thn TMAX not able to read evcd format properly.
Can you please put the line where this error came?
Thanks & (...)
ASIC Design Methodologies and Tools (Digital) :: 06-19-2014 05:53 :: maulin sheth :: Replies: 5 :: Views: 2066
This is just a standard N tap FIR.
First of all, I suggest you bring in all C co-efficients separately, not as a single bus.
Second, for N taps, you will probably need a package to create the array types to make the design generic.
I dont know why you have declared RAM and ROM types - there is no RAM or ROM in your drawings. They are just arrays o
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-12-2014 07:19 :: TrickyDicky :: Replies: 23 :: Views: 2440
There is no standard from ieee that specifies which constructs should be synthesizable, or which constructs should be ignored in SystemVerilog. That is up to each synthesis vendor. DC ignores them.
ASIC Design Methodologies and Tools (Digital) :: 06-03-2014 20:17 :: dave_59 :: Replies: 4 :: Views: 635
I want to publish my paper related to microwave frequency range work. What are the good impact factor and good and standard journal for publishing microwave related work other than ieee JOURNALS. I know the ieee Microwave theory and techniques and microwave wireless components letters. Other than (...)
Miscellaneous Engineering :: 05-13-2014 07:23 :: pusparaga :: Replies: 1 :: Views: 1092
Whatever the answers is for the standard, EDA tools might have a different idea ;)
ASIC Design Methodologies and Tools (Digital) :: 04-08-2014 12:04 :: jbeniston :: Replies: 5 :: Views: 543
Have you tried to add them? Modelsim works fine with them?
What version of modelsim are you using? You dont need fixed_pkg_c.vhd with newer versions (its included as part of the 2008 standard in the ieee package).
PLD, SPLD, GAL, CPLD, FPGA Design :: 03-26-2014 14:31 :: TrickyDicky :: Replies: 4 :: Views: 762
rEtotal refers to the magnitude of the electric field vector (this will vary based on your input power, distance of farfield measurements and other similar parameters).
Gaintotal refers to the total gain (defined using normalized power over entire sphere and compared against an isotropic radiator, i.e., the standard ieee definition)
RF, Microwave, Antennas and Optics :: 11-26-2013 15:16 :: jeeudr :: Replies: 2 :: Views: 1257
Boundary-scan was devised as a method for testing manufacturing faults on PCBAs (assembled boards). Using a shift register that is isolated from the core of the device you can control a device's pins (provided it is compliant to the boundary-scan standard ieee 1149), with appropriate hardware e.g. USB => boundary-scan (aka JTAG) controller and soft
ASIC Design Methodologies and Tools (Digital) :: 11-25-2013 14:51 :: Barry Pearson :: Replies: 6 :: Views: 942
to satisfy ieee 512 standard I suggest using of LCL filter.
many papers have been published about optimized selection of LCL values such as:
W. Sui et. al "Intelligent Optimize Design of LCL Filter for Three-Phase Voltage-Source PWM Rectifier" in proc. ieee IPEMC 2009.
Power Electronics :: 11-25-2013 10:04 :: kappa_am :: Replies: 2 :: Views: 1152
I am asking that, in our SoC there will be many cores. Ok? We wrap up those cores by ieee 1500 standard for testing various cases.
My question is can each of those core have sub-cores?
Ans our SoC will be placed on 1 PCB. On that PCB there can be sub-system modules. And those modules also may contain some cores.
ASIC Design Methodologies and Tools (Digital) :: 10-28-2013 07:10 :: kenambo :: Replies: 5 :: Views: 676
I started modelsim to find no libraries loaded,not even ieee standard libraries, only my work library that I added using vlib but nothing more.
The libraries list in gui is empty.
Is there something wrong with my modelsim.ini file ?? the file is located at $modeltech and I haven't changed or altered it in anyway.
ASIC Design Methodologies and Tools (Digital) :: 10-03-2013 17:13 :: 3wais :: Replies: 5 :: Views: 1328
Usuallly while loops aren't supported for synthesizable VHDL. This is specified in ieee 1076.6-2004 (RTL synthesis) and also applies to tools not strictly following this standard.
Technically, only loops with "bounded" iteration number can be synthesized, because they are enrolled to parallel logic. The shown snippet seems completely unsuitable
PLD, SPLD, GAL, CPLD, FPGA Design :: 09-11-2013 06:40 :: FvM :: Replies: 3 :: Views: 1272
I am replicating an ieee paper using Low-Power split-path data-driven dynamic logic. Since they are not standard logic blocks I was not able to synthesize it from RTL so I did fully custom schematic and layout by hand. The design is a 16x16 bit multiplier, and the layout passes DRC/LVS without any warnings or errors.
I have ran about 35 random
ASIC Design Methodologies and Tools (Digital) :: 08-30-2013 16:23 :: jiffyg89 :: Replies: 3 :: Views: 792
can the eNodeB share the same guardband ? is there any restriction in the ieee standard
i mean for 20MhZ cell, it will have 600 subcarriers as guard band for each side i feel this number is large , so can it be shared ?
Digital communication :: 08-26-2013 20:08 :: mr_byte31 :: Replies: 0 :: Views: 535
Analog Circuit Design :: 07-22-2013 08:14 :: FvM :: Replies: 3 :: Views: 569
You are trying to include VHDL standard libraries in Verilog.
The library and use keywords are unknown in Verilog.
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-02-2013 09:35 :: FvM :: Replies: 5 :: Views: 2903
the std_logic_arith and numeric_std both define unsigned type, so you cannot see either without being explicit
signal my_us : numeric_std.unsinged(3 downto 0);
To avoid this, you should not use the non-standard std_logic_arith library, and stick withe the ieee standard numeric_std instead.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-07-2013 11:13 :: TrickyDicky :: Replies: 3 :: Views: 642
The ieee 1800-2012 standard for SystemVerilog is now freely available from the ieee get program. This standard replaces the 1364 Verilog Language Reference Manual.
PLD, SPLD, GAL, CPLD, FPGA Design :: 06-02-2013 21:20 :: dave_59 :: Replies: 1 :: Views: 2998
They are different. One is an ieee standard (to_integer) and one is not standard VHDL (conv_integer).
Also, to_integer converts unsigned/signed type. Conv integer converts std_logic_vectors.
So, to do standard VHDL, you should use to_integer from numeric_std. You should never use std_logic_arith or std_logic_signed/unsigned
PLD, SPLD, GAL, CPLD, FPGA Design :: 04-27-2013 13:35 :: TrickyDicky :: Replies: 2 :: Views: 9910
ASIC Design Methodologies and Tools (Digital) :: 04-08-2013 20:06 :: dave_59 :: Replies: 2 :: Views: 764
I am a Ph.D student and quite new to OPNET. I am trying to work on the ieee 802.15.6 standard and am interested in developing a simulation for wireless body area networks employing IR-UWB sensors. Any knowledge regarding its implementation in OPNET would be really useful.
Thanks a lot!
Network :: 03-19-2013 10:50 :: Mridula15 :: Replies: 0 :: Views: 1598
Yes, encrypted Verilog files are ASCII. Unless the tool supports a standard encryption mechanism like ieee P1735, the Verilog source must be specifically encrypted for each tool that will need to read it.
ASIC Design Methodologies and Tools (Digital) :: 01-08-2013 18:31 :: dave_59 :: Replies: 5 :: Views: 3439
So the circuit actually can't determine if one of its inputs is in the Z state.
Right. Z is only synthesizable on outputs. X is supported for definition of don't care.
Although not necessarily implemented by all synthesis tools, ieee 1364.1-2002 ieee standard for Verilog Register Transfer Level Synthesis gives a general id
PLD, SPLD, GAL, CPLD, FPGA Design :: 11-16-2012 16:36 :: FvM :: Replies: 3 :: Views: 2031
Get some dicent camera with higher speed. standard camera will give delays. Also shutter must have adequate speed.
DIY Eye in the Sky
RF, Microwave, Antennas and Optics :: 11-15-2012 21:33 :: tpetar :: Replies: 5 :: Views: 680
802.11 (trade mark) is the ieee standard for wireless local area networks
Microcontrollers :: 08-23-2012 19:07 :: horace1 :: Replies: 3 :: Views: 544
you cannot do unsigned+ with std_logic_signed.
they are different.
std_logic_signed works on std_logic_vectors. It is NOT part of the VHDL standard. You cannot do unsigned arithmatic in the same file.
numeric_std works on signed and unsigned types. It is part of the VHDL standard. It makes for clearer code and you can do signed and unsigned in the
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-22-2012 06:44 :: TrickyDicky :: Replies: 2 :: Views: 1698
as a note, you should NOT use std_logic_arith and numeric_std in the same file as they conflict. Numeric_std is the ieee standard library.
PLD, SPLD, GAL, CPLD, FPGA Design :: 08-16-2012 15:04 :: TrickyDicky :: Replies: 3 :: Views: 685
There is a ieee (not Synopsys) standard for UPF
ieee 1801™ standard for Design and Verification of Low-Power Integrated Circuits, the Unified Power Format (UPF)
So, different tools of different vendors may support it. For example, from Synopsys, it can be read by VCS (with MVSIM), MVRC, DesignCompiler, IC Compiler, (...)
ASIC Design Methodologies and Tools (Digital) :: 07-23-2012 10:55 :: oratie :: Replies: 10 :: Views: 1971
i am looking for Wimax standard for CPE can any one guide me which standards i need to look in for latest release , there are lot versio in ieee pls help me to select latest one.
ieee Std 802.16-2009, as amended by
ieee Std 802.16j-2009 (amendment to ieee 802.16-2009) (...)
RF, Microwave, Antennas and Optics :: 07-18-2012 11:58 :: disisku_22 :: Replies: 0 :: Views: 594
This is an artifact of the way current synthesis tools want to see DFF modeled as a single process.
Artifact is a good word for this contradiction in terms - using the edge keyword for a level sensitive event.
But the latest with ieee 1364.1 standard for Verilog Register Transfer Level Synthesis, the syntax has been accept
PLD, SPLD, GAL, CPLD, FPGA Design :: 07-10-2012 20:58 :: FvM :: Replies: 8 :: Views: 2918