Search Engine www.edaboard.com
1 Threads found on edaboard.com: Standard Layout Table
After synthesis you can check your pre-layout timing of the synthesized circuit.
After floorplan routing and all you must check LVS and DRC of your GDS.
Inputs contains RTL file, sdc file .lef files cap table files and standard library files.
ASIC Design Methodologies and Tools (Digital) :: 12-16-2014 05:25 :: kenambo :: Replies: 1 :: Views: 409