13 Threads found on edaboard.com: Star Routing
why to verify timing after routing stage in physical design?
why to verify timing after star-RCXT Extraction in physical design?
Please give me the answer
ASIC Design Methodologies and Tools (Digital) :: 11-19-2012 06:59 :: nithin.j38 :: Replies: 1 :: Views: 561
I am using DDR3 in Flyby Topology but due to space constarint in board I have to place my DDRs one over another.
What I need to know is can I place DDR3 in this way and have the connection of addr,command and control signals in star topology (like we do in DIMM modules) or do I need to maintain flyby topology for that. The addr, cmmd an
PCB Routing Schematic Layout software and Simulation :: 12-21-2011 01:22 :: Anonymous_Ricky :: Replies: 2 :: Views: 4454
I am little bit confused about the routing/wiring to form a star ground.
I have a designed a signal averager (box car averager) circuit with few digital ICs (10 numbers) 74ls00, 74ls04, 74ls244, 74ls393 and analog ICs (26numbers) (like lF356 and LF398 e.t.c). I have made two individual grounds for those type and called as analog ground (
Analog Circuit Design :: 06-08-2011 03:20 :: drkjreddy :: Replies: 7 :: Views: 2137
i know that i should be carefull in the way i route vdd and vss, but that's all i know,
can somebeody give me the big issues with routing vdd and vss
ps: it's an analog block
i have heard about ground planes star connections, avoiding supply loops , can somebody clarify for me those concepts or/and give a good reference or link abou
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-17-2010 11:55 :: MohEllayali :: Replies: 2 :: Views: 840
I am routing a address line A0. It comes from the processor and connected to 2 DDR2 modules.i am following star topology. So I scheduled nets and formed a T junction.Now what i have to do is to match the length to each of the DDR2 what could be done to match the entire T connection.
PCB Routing Schematic Layout software and Simulation :: 04-18-2008 02:24 :: Hooda :: Replies: 5 :: Views: 1347
star topology is used for DDR2 designs chk out this one
PCB Routing Schematic Layout software and Simulation :: 03-14-2008 04:18 :: venkat_kvr :: Replies: 1 :: Views: 2254
If your Astro file have CapModel or CapTable definition, it means you have tlu model for RC extraction in Astro. You can use it to do placement and routing.
The .itf file is TLU+ model.(use star-RCXT transfer .itf to TLU+ model) The TLU+ model accuracy is more than TLU model.
ASIC Design Methodologies and Tools (Digital) :: 03-01-2008 02:51 :: chyau :: Replies: 3 :: Views: 1565
Hello board, I want to route a signal between 2 adjacent boards(track length is about 6 inch), output of board A will be input of board B. I deally I do not want to have difference between level of these two signals more than 10uV in two different boards. though I have used star configuration of GND and thick GND tracks(60 mil) for each board but G
PCB Routing Schematic Layout software and Simulation :: 08-21-2007 10:55 :: fala :: Replies: 0 :: Views: 1104
you already askede in this topic:
star topology or daisy chain.
PCB Routing Schematic Layout software and Simulation :: 05-20-2007 11:28 :: buenos :: Replies: 1 :: Views: 1127
If it is 2stage flash ADC, it should be fast ADC, isn't it ?
So, single ended is a non-sense, because the digital will make a lot of noise that will come on to signal.
If you keep on working with single ended, split as much as you can analog and digital, especially within the ADC. Split the power supplies, use star-routing. Finally fill any blank
Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-21-2006 23:33 :: okguy :: Replies: 7 :: Views: 1101
If you are routing in single/double side PCB go for star or Multi drop routing topology. Avoid Daisy Chin.
You dont have to worry in case of Multilayer board.Vcc Plane takes care of it.
PCB Routing Schematic Layout software and Simulation :: 08-16-2006 22:42 :: centiago :: Replies: 1 :: Views: 936
Filler cell won't fix the metal density, but as already explain, fix nwell.
The filler cell is only required between std cell, not mandatory for start row to the first std cell ( same idea to the end of the row).
And the filler cell is not needed to finish the power std cell connection.
Filler cell don't impact the timing because the filler cells s
ASIC Design Methodologies and Tools (Digital) :: 02-28-2013 02:13 :: rca :: Replies: 24 :: Views: 3093
Thanks a lot mate.
Actually i am using cadence First encounter for routing. Now for doing manual routes for PLL's i was told to do routing in star formation.
So thats why i was totally confused as to why this requirement was there.
If any one else can comment it would be very much appreciated
Ehh... you design PLL-
ASIC Design Methodologies and Tools (Digital) :: 02-26-2006 08:31 :: xxargs :: Replies: 5 :: Views: 993