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11 Threads found on edaboard.com: Startup Ptat
You could start with just what "didn't work" means. A result you didn't like, or failure to produce a result at all? bandgap / ptat loops without explicit startup mechanisms, can easily converge in one testbench and fail in another, because when they start up they're doing so on "numerical noise" which depends on the circuit matrix and algorithm
The trick is, your startup "boot current" must do a couple of things reliably - - must push current into a gain node, up to and above the point where that gain will pull in and lock the current loop. This gain and minimum boot voltage vary a lot w/ temp, process and can be subject to "modeling laziness" (very low current operation often
mastericke is right, you need a loop gain of less than 1. The loop gain is given by gm2/(gm1)(1+gm2*Rs) As you can see, loop gain is guaranteed to be less than 1 in the stable state. You can verify this in simulation by running a transient, making sure that you include a startup circuit to bring the circuit to its stable operating point, c
... If all the nodes are zero, it will never startup Surely it will: When VDD is switched on (even if it rises slowly), C initially provides the necessary startup current. The limiting R isn't necessary, IMHO, because the pmos limits the current anyway. Could you explain it in detail? Why C provides
As for "Why?", presumably your circuit needs to work every time. Counting on some specific supply risetime, some leakage, etc. is a poor bet against a universe of mischief. The general theme for startup is, apply a bias to one of the legs that gets enough current flowing to enter the regenerative region of operation, but one that is enough
Hi For 1.5V supply I would not use the classical bandgap approach The classical approach will show some serious problems in the low-temp/slow corners, especially during startup ... Look out for some papers about low voltage bandgaps. The basic idea there is, that you add a ptat and an iptat current. THis current is injected into a (...)
Hi, Are you having the issue in simulation(pre tapeout) or in Silicon ?I think bandgap is a self biased circuit and hence the circuit will either operate as desired (with required current mirroring + bg voltage generation etc) or will not startup. So in general , a startup circuit is added in bandgap so that it does start up. Now assuming you h
Transient is the only way to do startup sims. You should ramp Vdd very slowly (1 second for 0-3.3v for example) and watch to make sure your circuit starts. Cold is usually worse if your circuit uses ptat currents since they are smaller at cold. Slower ramps are always worst case, because some circuits get "knocked into startup" by (...)
Increase your startup helper current injection and switch it off after the bandgap reach near its full voltage.
If the A or B is used as bias for gate of ptat current, i think the circuit will not work. Generally , the statup circuit generates the current for core circuit, once the core circuit work normally , the startup circuit is isolated from the core circuit. AS you draw , the A or B will effect the core circuit when the core circuit work normall
The main circuit is the ptat core. It is enclosed into a regulation loop which try to equalize the currents I1 and I2. The resulting current Iptat=I1=I2 is the ptat current. The equations for the ptat circuit is I1*R+VT*ln(I1/(a*IS))=VT*ln(I2/IS), "a" emitter area ratio the solution for I1=I2 is (...)